Vertilon SIB064 User manual

User Guide
Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
SIB064
64 Channel PMT Interface Board
Hamamatsu H8500D series

User Guide
Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Disclaimer
Vertilon Corporation has made every attempt to ensure that the information in this document is accurate and complete.
Vertilon assumes no liability for errors or for any incidental, consequential, indirect, or special damages including,
without limitation, loss of use, loss or alteration of data, delays, lost profits or savings, arising from the use of this
document or the product which it accompanies.
Vertilon reserves the right to change this product without prior notice. No responsibility is assumed by Vertilon for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication
or otherwise under the patent and proprietary information rights of Vertilon Corporation.
Copyright Information
© 2008 Vertilon Corporation
ALL RIGHTS RESERVED
No form of this document may be reproduced or transmitted in any form or byany means, electronic or mechanical, for
an
y
purpose without prior, express written consent from Vertilon Corporation.

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Table of Contents
General Safety Precautions........................................................................................................................5
Product Overview.......................................................................................................................................6
Specifications..............................................................................................................................................8
High Voltage Interface..............................................................................................................................10
Photomultiplier Tube Anode Circuits.........................................................................................................11
Last Dynode Preamplifier .........................................................................................................................11
Leading Edge Discriminator......................................................................................................................11
Constant Fraction Discriminator................................................................................................................12
Zero Slope Discriminator..........................................................................................................................14
Top and Bottom Views..............................................................................................................................15
Component Locations and Functions .......................................................................................................16
SIB Connector Pinout...............................................................................................................................18
Mechanical Information.............................................................................................................................19

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
List of Figures
Figure 1: Functional Block Diagram...........................................................................................................7
Figure 2: PMT High Voltage Interface Circuit ..........................................................................................10
Figure 3: Anode Circuit............................................................................................................................11
Figure 4: Leading Edge Discriminator Timing..........................................................................................12
Figure 5: Constant Fraction Discriminator Timing....................................................................................13
Figure 6: Zero Slope Discriminator Timing ..............................................................................................14
Figure 7: Top and Bottom Views..............................................................................................................15
Figure 8: Component Locations and Functions.......................................................................................16
Figure 9: FEM Printed Circuit Board Dimensions....................................................................................19
List of Tables
Table 1: Specifications...............................................................................................................................9
Table 2: Connectors................................................................................................................................17
Table 3: Jumpers, Switches, and Pots.....................................................................................................17
Table 4: Test Points.................................................................................................................................17
Table 5: Sensor Interface Board (SIB) Connectors..................................................................................18

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
General Safety Precautions
Use Proper Power Source
The SIB064 is powered with a +5V power source directly from Vertilon’s PhotoniQ multi-channel data acquisition
systems. Use with any other power source may result in damage to the product.
Operate Inputs within Specified Range
To avoid electric shock, fire hazard, or damage to the product, do not apply a voltage to any input outside of its specified
range.
Electrostatic Discharge Sensitive
Electrostatic discharges may result in damage to the SIB064. For these reasons, the SIB064 board is intended to be
operated in a user’s conductive instrument enclosure.
Do Not Operate in Wet or Damp Conditions
To avoid electric shock or damage to the product, do not operate in wet or damp conditions.
Do Not Operate in Explosive Atmosphere
To avoid injury or fire hazard, do not operate in an explosive atmosphere.

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Product Overview
The SIB064 multianode photomultiplier tube interface board provides the mechanical and electrical connectivity between
the Hamamatsu H8500D 64 anode PMT and external signal processing electronics such as Vertilon’s PhotoniQ
multichannel data acquisition systems. The H8500D is mounted to the bottom side of the SIB064 through 148 socket pins
that connect the PMT’s 64 anode signals, high voltage input, and last dynode output to the board. The anode signals are
routed to two connectors located on the top of the board that each connect to a specialized high density coaxial cable
assembly. This arrangement allows the SIB064 to be conveniently mounted directly into the user’s optical setup with the
PMT facing outward from the bottom of the board and the sensor interface board (SIB) cables exiting from the top. The
SIB cables carry the 64 anodes from the H8500D to the PhotoniQ where the charge from each is separately integrated,
digitized, and sent to a PC for display or further signal processing. The negative high voltage bias to the PMT’s cathode is
supplied directly from the PhotoniQ on a high voltage cable to a dedicated connector on the SIB064. For applications
utilizing the last dynode output of the H8500D, the SIB064 includes a two stage high speed preamplifier whose output is
available on an SMB connector. When critical timing and triggering are required, this output can be connected to a
separate high performance external discriminator. Alternatively, one of the three on-board discriminators can be used
when the timing requirements are not as stringent. The outputs from a leading edge, constant fraction, and zero slope
discriminator — which respectively generate trigger signals based on a threshold, percentage of pulse height, and pulse
peak — are each available on an SMB connector. Several user adjustments are included for optimizing system gain and
trigger thresholds for the discriminators.
The various functions on the SIB064 are described in greater detail on the following pages. When necessary, refer to the
functional block diagram shown in Figure 1 below.
•Mounting board for Hamamatsu H8500D 64 channel MAPMT
•Provides 64 channel interface to data acquisition systems
•Separate high voltage input for PMT cathode bias
•High speed preamplifier for last dynode output
•Leading edge, constant fraction, and zero slope discriminators
•Adjustable gain and discriminator thresholds
•100% compatible with Vertilon’s PhotoniQ multichannel DAQs
•No external power supply required

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Figure 1: Functional Block Diagram
VERTILON SIB064
H8500D PMT
SENSOR INTERFACE BOARD
AMP1
Rp
GAIN
ADJ
FRACTION
Cin
INV
AMP2 DELAY INV
AMP3
FRACTION
ADJ
DELAY CFD
THRESHOLD
COMP >
DQ
CLR
LEADING EDGE
THRESHOLD
COMP
LEADING
EDGE
DISCR
PREAMP
OUT
dv
dt
ZERO SLOPE
THRESHOLD
COMP >
DQ
CLR
INV
AMP4
CFD
DISCR
ZERO
SLOPE
DISCR
HAMAMATSU H8500D
8 X 8 MULTIANODE
PHOTOMULTIPLIER TUBE
P1
P2
P3
P31
P35
P63
P64
P34
P33
P32
P1
P2
P3
P31
P32
J1
SIB CONNECTOR
P35
P63
P64
P34
P33
ANODES
VB
DY12
DY11
DY10
DY9
DY8
DY7
DY6
DY5
DY4
DY3
DY2
DY1
J2
SIB CONNECTOR
K
HIGH VOLTAGE NETWORK
-HV
-HV
INPUT
HIGH
VOLTAGE
MONITOR
HVMON
J4
J5
J6
J7
J3
Rin
R
R

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Specifications
(Vsupply = +5.0V, TA= +25C, unless otherwise noted)
Description Sym Min Typ Max Units Notes
HIGH VOLTAGE
High Voltage Input Load Resistance 50 MΩMeasured at high voltage input connector, J3
HVMON to High Voltage Input Ratio 0.0015 ±20%
ANODE CIRCUITS
Quantity P1 - P64 64
Input Resistance R 2.2 MΩ
Input Bias Voltage VB +0.250 V Detector bias voltage supplied from PhotoniQ data
acquisition system
LAST DYNODE PREAMPLIFIER
Input Coupling Capacitance Cin 0.1 uF
Input Resistance Rin 50 Ω
Input Parallel Resistance Rp500 Ω
Amplifier #1 Gain A1 12.6 dB
Amplifier #2 Inverting Gain A2 6 dB Vin is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12).
Amplifier #2 Output Impedance 50 ΩMeasured at preamplifier output, J4
LEADING EDGE DISCRIMINATOR
Threshold Adjustment Vth1 -25 0 mV Referenced to baseline level at comparator input
Threshold to Output Delay (Vin=30mV) td1 5 nsec
Time Walk (Vin: 3mV to 30mV) -13 nsec
Time Walk (Vin: 30mV to 150mV) -3.0 nsec
Jitter (Vin: 10mV) 500 psec
Output on connector, J5.
Vin is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12). Threshold
(Vth1) set to 15mV below the baseline.
CONSTANT FRACTION DISCRIMINATOR
Delay D 5 nsec Standard delay element, other delays available.
Delay to Fraction Ratio 0.12 0.50 7 steps of 2 dB each
Steps: 0.12, 0.16, 0.20, 0.25, 0.31, 0.40, 0.50
Amplifier #3 Inverting Gain A3 +8.6 dB
Threshold Adjustment Vth2 0 +25 mV Referenced to baseline level at comparator input
Threshold to Output Delay (Vin=30mV) td2 6 nsec
Time Walk (Vin: 10mV to 100mV) -0.8 nsec
Jitter (Vin: 50mV) 500 psec
Output on connector, J6.
Vin is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12). Threshold
(Vth2) set to 15mV above the baseline. Fraction set to 0.50.

User Guide
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Description Sym Min Typ Max Units Notes
ZERO SLOPE DISCRIMINATOR
Differentiator First-Order Time Constant 3.3 nsec
Amplifier #4 Inverting Gain A4 10.4 dB
Threshold Adjustment Vth3 0 +25 mV Referenced to baseline level at comparator input
Threshold to Output Delay (Vin=30mV) td3 6 nsec
Time Walk (Vin: 20mV to 200mV) -1.5 nsec
Jitter (Vin: 100mV) 500 psec
Output on connector, J7.
Vin is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12). Threshold
(Vth3) set to 5mV above the baseline.
DISCRIMINATOR OUTPUTS
Output Impedance 50 Ω
Logic High Output Level VOH +4.3 +4.8 V (IOH = -32mA)
Logic Low Output Level VOL +0.2 +0.6 V (IOL = 32mA)
POWER
Supply Voltage Vsupply +4.9 +5.0 +5.1 V
Supply Current Isupply 75 mA (all comparators enabled)
Supply Current Isupply 55 mA (all comparators disabled)
DIMENSIONS
Width W 84 mm
Length L 102 mm (not including SMB connectors which extend past PCB edge)
Thickness T 2.5 mm (printed circuit board only)
Table 1: Specifications

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Typical Setup
A typical setup using a SIB064 is shown below. The Hamamatsu H8500D PMT is mounted to the SIB064 and positioned
to detect incoming light from a scintillator crystal or optical assembly. Two SIB cables connect the 64 anode outputs from
the SIB064 to a PhotoniQ IQSP482 or IQSP582 64 channel PMT data acquisition system. Through a USB 2.0 connection
the digitized output data from the PhotoniQ is sent to a PC for display, logging, or real time processing. Additional
connections between the SIB064 and PhotoniQ include a high voltage cable that provides up to 1400 volts of negative
bias to the H8500D cathode, and a trigger cable that supplies the trigger to the PhotoniQ from one of the SIB064’s three
discriminators. In an alternative configuration when precision timing is required, an external discriminator can be placed
between the SIB064 preamplifier output and the PhotoniQ trigger input.
Figure 2: Typical Setup
High Voltage Interface
The SIB064 employs the interface circuit shown below between the high voltage input connector, J3, and the high voltage
input to the H8500D. The monitor output (HVMON) allows the high voltage cathode bias for the PMT to be indirectly
monitored at a reduced voltage level. Voltage readings at the monitor point should be scaled by a factor of 667.
Calibration of the scale factor may be required.
Warning: The high voltage section of the SIB064 contains signals at voltage levels
that can exceed negative 1500 volts. Never touch a component or signal in this area.
Figure 3: PMT High Voltage Interface Circuit

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Photomultiplier TubeAnode Circuits
The 64 anode signals (P1 – P64) from the H8500D PMT are routed directly on the SIB064 to two specialized connectors
referred to as sensor interface board (SIB) connectors. Anodes P1 to P32 route to SIB connector J1 and anodes P33 to
P64 route to SIB connector J2. Each SIB connector mates to a proprietary low-noise, high density SIB cable assembly
that carries the 32 anode signals on coaxial connections to a Vertilon PhotoniQ 64 channel PMT data acquisition system.
Depending on the required speed and dynamic range, either a PhotoniQ IQSP482 high dynamic range system or an
IQSP582 high speed system can be used as the main data acquisition unit. To minimize the possibility of damage due to
ESD, the H8500D anodes each have a 2.2 Mohm shunt resistor to a common low impedance point. This point is biased
at a voltage equal to the bias voltage (VB) of the charge integrating transimpedance amplifiers on the PhotoniQ so that
the anodes can be DC coupled to them. Figure 4 below illustrates the equivalent circuit as seen by each PMT anode.
Figure 4: Anode Circuit
Last Dynode Preamplifier
This last dynode preamplier is an inverting, AC-coupled, two-stage configuration whose input is designed for small
positive voltage pulses from the last dynode (DY12) of the H8500D. The preamplifier’s output can be further processed
by three different discriminators on the SIB064 to generate trigger signals in sync with the pulse on the last dynode. For
specialized applications requiring external discrimination of the last dynode signal, the preamplifier output is available on
SMB connector, J4. The preamplifier should be disconnected from the PMT by removing jumper JP1 when the last
dynode signal is unused.
Leading Edge Discriminator
The leading edge discriminator is a simple timing circuit that generates a trigger signal when a charge pulse on the last
dynode output from the H8500D PMT exceeds a user-defined threshold. It is implemented using a high speed
comparator connected to the output of the last dynode preamplier. Referring to Figure 5, negative going pulses from the
preamplier are compared to a threshold that is adjusted using the “LEAD” potentiometer on the SIB064. A logic high is
generated on the comparator output (SMB connector, J5) after a small delay (td1) from when the pulse first crosses the
threshold, Vth1. The comparator switches back to a logic low when the pulse crosses the threshold from the opposite
direction as it returns back to the baseline level. Because the trigger point is sensitive to the pulse height, this
discriminator is typically used in applications that do not require precision timing. When not used, the leading edge
discriminator should be disabled by switching switch SW1-1 to the “OPEN” position.

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Figure 5: Leading Edge Discriminator Timing
Constant Fraction Discriminator
Unlike leading edge discriminators, a constant fraction discriminator (CFD) is capable of generating precisely timed
trigger signals that are relatively independent of input pulse height. The CFD accomplishes this by subtracting a
fraction of the input from a delayed version of the input such that the resulting signal always crosses zero at exactly
the same point in time. To minimize triggering on noise, the threshold is set just above the zero crossing point. The
timing diagram in Figure 6 below illustrates the technique as implemented on the SIB064. The CFD operates on the
output of the last dynode preamplifier although technically only the delayed version of the signal (DELAY) is taken
from the preamplifier output — the fractional part (FRACTION) is derived from the output of the first stage. The sum
of these two components results in the AMP3 signal which is fed directly to the threshold comparator. This
comparator, which to minimize noise triggering is only enabled when the output of the leading edge discriminator is
high, compares AMP3 to a user-adjustable threshold voltage (Vth2) to generate the CFD output signal. By adjusting
the delay time, fraction, and threshold (Vth2), the CFD can be made to trigger at any reasonable percentage of the
pulse height maximum. The SIB064 ships with a standard fixed delay of 5 nsec (other delays of up to 10 nsec can be
ordered separately) and seven preset fractions from 0.12 to 0.50 that are selectable using an on-board micro-rotary
switch (SW2). The trigger threshold is adjusted using the “CFD” potentiometer. The leading edge discriminator must
be enabled when using the CFD. When not used, the CFD can be disabled by switching switch SW1-2 to the
“OPEN” position.
PREAMP
OUTPUT
Vth1
td1
TRIGGER
POINT
THRESHOLD
POINT
LEAD
LAST
DYNODE

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Figure 6: Constant Fraction Discriminator Timing
PREAMP
OUTPUT
Vth2
td2
TRIGGER
POINT
THRESHOLD
POINT
CFD
LAST
DYNODE
DELAY
FRACTION
AMP3
Vth1
RESET
POINT

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Zero Slope Discriminator
The zero slope discriminator works by generating a trigger signal at the inflection point of the input pulse. It is this
point where the pulse is at its peak and its slope transitions from positive to negative. Since AMP4 effectively
operates on the derivative of the input pulse, its output crosses zero where the slope of the pulse is zero. This occurs
at the pulse peak as shown in Figure 7. The threshold comparator compares AMP4 to the user-adjustable threshold
(Vth3) to generate the trigger signal. Similar to the constant fraction discriminator, the comparator is only enabled
when the output of the leading edge discriminator is high. The zero slope discriminator is disabled by switching
switch SW1-3 to the “OPEN” position.
Figure 7: Zero Slope Discriminator Timing
PREAMP
OUTPUT
Vth3
td3
TRIGGER
POINT
THRESHOLD
POINT
ZERO
LAST
DYNODE
AMP4
Vth1
RESET
POINT

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Top and Bottom Views
Figure 8: Top and Bottom Views
1. High Voltage Input (J3) 6. Constant Fraction Discriminator Output (J6)
2. Preamp Output (J4) 7. Zero Slope Discriminator Output (J7)
3. Sensor Interface Board Connector (J1) 8. High Voltage Section
4. Sensor Interface Board Connector (J2) 9. H8500D Socket Connectors
5. Leading Edge Discriminator Output (J5) 10. H8500D High Voltage Input
4
7
8
3
5 6
9 10
1
2

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Component Locations and Functions
Figure 9: Component Locations and Functions
39
40
1
2
J1
39
40
1
2
J2
FRACTION
SW2
3
4
5
6
2
1
-HV
J3
C24
C23
C15
C16
C6
C5
C4
C7
U9
U2
U3
U6U5U4
U8U7
U10
R65 R52 R43 R30 R21 R1R3R8
R2
C12C21
C34
C17
C33
C22
C28
C29
C35
C32
C14
C13
C9 C8
C27 C26 C25
C30 C31 C20
C19 C18
C11
C3
C10
C2
C1
R110
R103 R101 R102
R91 R90 R89
R116
R115
R112
R111
R113
R109
R108
R107
R106
R105
R104
R121
R117
R122
R86
R88
R79 R78
R87
R81
R80
R77 R76 R75 R74
R96 R94 R92
R97 R95
R93
R100 R99 R98
R120R119R118
R7R6R5R4
R114
R85
R73
R69
R64
R60
R56
R51
R47
R42
R38
R34
R29
R25
R20
R16
R12
R84
R72
R68
R63
R59
R55
R50
R46
R41
R33
R28
R37
R24
R19
R15
R11
R83
R71
R67
R62
R58
R54
R49
R45
R40
R36
R32
R27
R23
R18
R14
R10
R82
R70
R66
R61
R57
R53
R48
R44
R39
R35
R31
R26
R22
R17
R13
R9
COMP PWR
SW1
1234
OPEN
DELAY
DL1
ZERO
J7
CFD
J6
LEAD
J5
PREAMP
J4
ZERO
VR3
CFD
VR2
LEAD
VR1
SP2
SP1
DELAY
+5V
VB
+MIDH
+MID
AMP3
AMP4
AMP2
AMP1
-HV
HVMON
ZERO
CFD
LEAD
GAIN
JP2
DY12
JP1
LOMID
-
+
HIGH VOLTAGE

User Guide
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
Name Function Description
J1 CHANNELS 1 - 32 Sensor interface board connector to SIB cable for channels 1 -32
J2 CHANNELS 33 - 64 Sensor interface board connector to SIB cable for channels 33 - 64
J3 -HV Negative high voltage bias input
J4 PREAMP Last dynode preamplifier output
J5 LEAD Leading edge discriminator output
J6 CFD Constant fraction discriminator output
J7 ZERO Zero slope discriminator output
Table 2: Connectors
Name Function Description
JP1 DY12 Last dynode output to preamplier input disconnect: remove jumper to disconnect
JP2 GAIN Constant fraction discriminator gain: default equals “LO”
SW1-1 COMP PWR - LEAD Power to leading edge discriminator: set to open to power down
SW1-2 COMP PWR - CFD Power to constant fraction discriminator: set to open to power down
SW1-3 COMP PWR - ZERO Power to zero slope discriminator: set to open to power down
SW1-4 COMP PWR - Reserved
SW2 FRACTION Constant fraction discriminator fraction: 0 = minimum, 6 = maximum
VR1 LEAD Leading edge discriminator threshold: clockwise increases threshold
VR2 CFD Constant fraction discriminator threshold: clockwise increases threshold
VR3 ZERO Zero slope discriminator threshold: clockwise increases threshold
DL1 DELAY Programmable delay element for constant fraction discriminator
Table 3: Jumpers, Switches, and Pots
Name Description
+5V Main +5V power to the SIB064 supplied by the PhotoniQ through SIB connectors J1 and J2.
VB Anode bias and reference voltage to the SIB064 supplied by the PhotoniQ through SIB connectors J1 and J2.
+MID Baseline voltage for last dynode signal processing chain. Nominally +2.5V.
+MIDH Internal reference voltage.
-HV PMT cathode bias. Warning: This is a high voltage point that can exceed negative 1500 volts.
HVMON Highly attenuated version of –HV used for indirectly monitoring PMT cathode bias.
AMP1 Output of amplifier #1 in last dynode signal processing chain.
AMP2 Output of amplifier #2 in last dynode signal processing chain.
AMP3 Output of amplifier #3 in constant fraction discriminator.
AMP4 Output of amplifier #4 in zero slope discriminator.
DELAY Output of constant fraction discriminator delay path. Reference to AMP2 to measure the delay.
LEAD Leading edge discriminator comparator output, positive (+) and negative (-).
CFD Constant fraction discriminator comparator output, positive (+) and negative (-).
ZER0 Zero slope discriminator comparator output, positive (+) and negative (-).
SP1 Reserved signal from the PhotoniQ on SIB connector J1.
SP2 Reserved signal from the PhotoniQ on SIB connector J2.
Table 4: Test Points

SIB064 PMT Interface Board H8500D Series
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Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886 /Tel: [phone] /Fax: [phone] /www.vertilon.com
SIB Connector Pinout
The SIB064 connectors and cables are fully compatible with all Vertilon PhotoniQ systems. For applications utilizing data
acquisition systems other than Vertilon’s PhotoniQ series, the pinout for connectors J1 and J2 is provided in Table 5 as a
reference.
J1 J2
Signal
Name Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin #
VB 1 HVMON 2 VB 1 HVMON 2
GND 3 GND 4 GND 3 GND 4
P16 5 P32 6 P48 5 P64 6
P15 7 P31 8 P47 7 P63 8
P14 9 P30 10 P46 9 P62 10
P13 11 P29 12 P45 11 P61 12
P12 13 P28 14 P44 13 P60 14
P11 15 P27 16 P43 15 P59 16
P10 17 P26 18 P42 17 P58 18
P9 19 P25 20 P41 19 P57 20
P8 21 P24 22 P40 21 P56 22
P7 23 P23 24 P39 23 P55 24
P6 25 P22 26 P38 25 P54 26
P5 27 P21 28 P37 27 P53 28
P4 29 P20 30 P36 29 P52 30
P3 31 P19 32 P35 31 P51 32
P2 33 P18 34 P34 33 P50 34
P1 35 P17 36 P33 35 P49 36
GND 37 GND 38 GND 37 GND 38
SP1 39 +5V 40 SP2 39 +5V 40
Table 5: Sensor Interface Board (SIB) Connectors