ARTERY AT32A403A Series User manual

AT32A403A Series Reference Manual
2022.11.11 Page 1 Rev 2.00
ARM®-based 32-bit Cortex®-M4F MCU+FPU with 256 to 1024 KB Flash, sLib,
USB, 2 CANs, 17 timers, 3 ADCs, 20 communication interfaces
Feature
Core: ARM®32-bit Cortex®-M4F CPU with FPU
−200 MHz maximum frequency, with a Memory
Protection Unit (MPU), single-cycle multiplication
and hardware division
−Floating Point Unit (FPU)
−DSP instructions
Memories
−256 to 1024 KBytes of Flash memory
−sLib: configure any part of main Flash as a library
area that is code executable but secured and non-
readable
−SPIM interface: extra interfacing up to 16 Mbytes of
external SPI Flash (as instruction/data memory)
−Up to 96 + 128 KBytes of SRAM
−External memory controller (XMC) with 2 Chip
Select, supporting multiplexed SRAM/NOR/PSRAM
and NAND memories
−LCD parallel interface, 8080/6800 modes
Clock, Reset, and Power management
−2.6 V ~ 3.6 V application supply and I/Os
−Power on reset (POR)/ low voltage reset (LVR), and
power voltage monitor (PVM)
−4 to 25 MHz crystal (HEXT)
−Internal 48 MHz factory-trimmed RC (accuracy 1%
at TA=25 °C, 2.5 % at TA=-40 to +105 °C), with
automatic clock calibration (ACC)
−Internal 40 kHz RC oscillator (LICK)
−32.768 kHz crystal oscillator (LEXT)
Low power consumption
−Sleep, Deepsleep, and Standby modes
−VBAT supply for RTC and 42 x 16-bit battery powered
registers (BPR)
3 x 12-bit 0.5 μs A/D converters, up to 16 channels
−Conversion range: 0 V to 3.6 V
−Triple sample and hold capability
−Temperature sensor
2 x 12-bit D/A converters
DMA: 14-channel DMA controller
−Peripherals supported: timers, ADCs, SDIOs,
I2Ss, SPIs, I2Cs, and USARTs
Debug Mode
−Serial wire debug (SWD) and JTAG interface
−Cortex®-M4F Embedded Trace Macrocell (ETMTM)
Up to 80 Fast I/O Interfaces
−37/51/80 multifunctional and bidirectional I/Os, all
mappable to 16 external interrupt vectors and almost 5
V-tolerant
−All fast I/Os, control registers accessible with fAHB speed
Up to 17 Timers
−Up to 8 x 16-bit general-purpose timers + 2 x 32-bit
general-purpose timers; each with 4IC/OC/PWM or
pulsecounter and quadrature (incremental) encoder
input.
−Up to 2 x 16-bit motor control PWMadvanced timers
with dead-time generator and emergency brake
−2 x Watchdogtimers
−SysTick timer: 24-bitdowncounter
−2 x 16-bit basic timers to drive the DAC
Up to 20 Communication Interfaces
−Up to 3 x I2C interfaces (SMBus/PMBus)
−Up to 8 x USARTs (ISO7816 interface, LIN, IrDA
capability, and modemcontrol)
−Up to 4 x SPIs (50 Mbit/s), all with I2Sinterface
multiplexed, I2S2/ I2S3 support full-duplex
−Up to 2 x CANinterfaces (2.0B Active)
−USB2.0 full-speed interface supporting Crystal-less
−Up to 2 x SDIO interfaces
CRC Calculation Unit
96-bit unique ID (UID)
Packages
−LQFP10014x14mm
−LQFP64 10x10 mm
−LQFP48 7x7 mm
−QFN48 6 x 6mm
List of Models
AT32A403A series: AEC-Q100 Grade 2 certified
Internal Flash
Model
1024 KBytes
AT32A403ACGU7, AT32A403ACGT7,
AT32A403ARGT7, AT32A403AVGT7
512 KBytes
AT32A403ACEU7, AT32A403ACET7,
AT32A403ARET7, AT32A403AVET7
256 KBytes
AT32A403ACCU7, AT32A403ACCT7,
AT32A403ARCT7, AT32A403AVCT7

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2023.07.10 Page 2 Rev 2.00
Contents
1System architecture...................................................................... 30
1.1 System overview..........................................................................32
1.1.1 ARM Cortex®-M4F processor ....................................................... 32
1.1.2 Bit band...................................................................................... 33
1.1.3 Interrupt and exception vectors .................................................... 35
1.1.4 System Tick (SysTick) ................................................................. 38
1.1.5 Reset ......................................................................................... 38
1.2 List of abbreviations for registers ..................................................39
1.3 Device characteristics information.................................................40
1.3.1 Flash memory size register .......................................................... 40
1.3.2 Device electronic signature.......................................................... 40
2Memory resources ........................................................................ 41
2.1 Internal memory address map.......................................................41
2.2 Flash memory..............................................................................42
2.3 SRAM memory.............................................................................43
2.4 Peripheral address map................................................................43
3Power control (PWC)..................................................................... 46
3.1 Introduction .................................................................................46
3.2 Main Features .............................................................................46
3.3 POR/LVR ....................................................................................46
3.4 Power voltage monitor (PVM)........................................................47
3.5 Power domain..............................................................................48
3.6 Power saving modes ....................................................................48
3.7 PWC registers .............................................................................50
3.7.1 Power control register (PWC_CTRL) ............................................ 50
3.7.2 Power control/status register (PWC_CTRLSTS) ............................ 51
4Clock and reset manage (CRM) ..................................................... 52
4.1 Clock ..........................................................................................52

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4.1.1 Clock sources ............................................................................. 52
4.1.2 System clock............................................................................... 53
4.1.3 Peripheral clock .......................................................................... 53
4.1.4 Clock fail detector ....................................................................... 54
4.1.5 Auto step-by-step system clock switch.......................................... 54
4.1.6 Internal clock output.................................................................... 54
4.1.7 Interrupts.................................................................................... 54
4.2 Reset..........................................................................................54
4.2.1 System reset............................................................................... 54
4.2.2 Battery powered domain reset...................................................... 55
4.3 CRM registers .............................................................................55
4.3.1 Clock control register (CRM_CTRL).............................................. 56
4.3.2 Clock configuration register (CRM_CFG) ...................................... 57
4.3.3 Clock interrupt register (CRM_CLKINT) ........................................ 59
4.3.4 APB2 peripheral reset register (CRM_APB2RST) .......................... 60
4.3.5 APB1 peripheral reset register (CRM_APB1RST) .......................... 62
4.3.6 APB peripheral clock enable register (CRM_AHBEN)..................... 63
4.3.7 APB2 peripheral clock enable register (CRM_AHB2EN) ................. 64
4.3.8 APB1 peripheral clock enable register (CRM_AHB1EN) ................. 66
4.3.9 Battery powered domain control register (CRM_BPDC).................. 67
4.3.10 Control/status register (CRM_CTRLSTS) ...................................... 68
4.3.11 Additional register1 (CRM_MISC1) ............................................... 69
4.3.12 Additional register2 (CRM_MISC2) ............................................... 69
4.3.13 Additional register3 (CRM_MISC3) ............................................... 70
4.3.14 Interrupt map register (CRM_INTMAP) ......................................... 70
5Flash memory controller (FLASH) ................................................. 71
5.1 Flash memory introduction............................................................71
5.2 Flash memory operation ...............................................................75
5.2.1 Unlock/lock ................................................................................. 75
5.2.2 Erase operation........................................................................... 76
5.2.3 Programming operation................................................................ 78
5.2.4 Read operation ........................................................................... 79
5.3 External memory operation ...........................................................79
5.4 User system data area operation...................................................79

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5.4.1 Unlock/lock ................................................................................. 79
5.4.2 Erase operation........................................................................... 79
5.4.3 Programming operation................................................................ 80
5.4.4 Read operation ........................................................................... 81
5.5 Flash memory protection ..............................................................81
5.5.1 Access protection........................................................................ 82
5.5.2 Erase/program protection............................................................. 82
5.6 Special functions .........................................................................82
5.6.1 Security library settings ............................................................... 82
5.7 Flash memory registers ................................................................84
5.7.1 Flash performance select register (FLASH_PSR) .......................... 84
5.7.2 Flash unlock register (FLASH_UNLOCK) ...................................... 84
5.7.3 Flash user system data unlock register (FLASH_USD_UNLOCK) ... 85
5.7.4 Flash status register (FLASH_STS) .............................................. 85
5.7.5 Flash control register (FLASH_CTRL)........................................... 85
5.7.6 Flash address register (FLASH_ADDR) ........................................ 86
5.7.7 User system data register (FLASH_USD)...................................... 86
5.7.8 Erase/program protection status register (FLASH_EPPS) .............. 86
5.7.9 Flash unlock register2 (FLASH_UNLOCK2)................................... 86
5.7.10 Flash status register2 (FLASH_STS2) .......................................... 87
5.7.11 Flash control register2 (FLASH_CTRL2) ....................................... 87
5.7.12 Flash address register2 (FLASH_ADDR2)..................................... 88
5.7.13 Flash unlock register3 (FLASH_UNLOCK3)................................... 88
5.7.14 Flash select register (FLASH_SELECT) ........................................ 88
5.7.15 Flash status register3 (FLASH_STS3) .......................................... 88
5.7.16 Flash control register3 (FLASH_CTRL3) ....................................... 88
5.7.17 Flash address register3 (FLASH_ADDR3)..................................... 89
5.7.18 Flash decryption address register (FLASH_DA)............................. 89
5.7.19 Flash security library status register (SLIB_STS0)......................... 89
5.7.20 Flash security library status register1 (SLIB_STS1)....................... 90
5.7.21 Flash security library password clear register (SLIB_PWD_CLR).... 90
5.7.22 Security library additional status register (SLIB_MISC_STS).......... 90
5.7.23 Security library password setting register (SLIB_SET_PWD).......... 91
5.7.24 Security library address setting register (SLIB_SET_RANGE) ........ 91
5.7.25 Security library unlock register (SLIB_UNLOCK) ........................... 91

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5.7.26 Flash CRC check control register (FLASH_CRC_CTRL) ................ 92
5.7.27 Flash CRC check result register (FLASH_CRC_CHKR).................. 92
6General-purpose I/Os (GPIOs)....................................................... 93
6.1 Introduction .................................................................................93
6.2 Function overview........................................................................93
6.2.1 GPIO structure ............................................................................ 93
6.2.2 GPIO reset status........................................................................ 94
6.2.3 General-purpose input configuration............................................. 94
6.2.4 Analog input/output configuration ................................................. 94
6.2.5 General-purpose output configuration........................................... 94
6.2.6 I/O port protection ....................................................................... 94
6.3 GPIO registers.............................................................................95
6.3.1 GPIO configuration register low (GPIOx_CFGLR) (x=A..E)............. 95
6.3.2 GPIO configuration register high (GPIOx_CFGHR) (A..E) .............. 96
6.3.3 GPIO input data register (GPIOx_IDT) (x=A..E)............................. 96
6.3.4 GPIO output data register (GPIOx_ODT) (x=A..E) ......................... 96
6.3.5 GPIO set/clear register (GPIOx_SCR) (x=A..E) ............................. 97
6.3.6 GPIO clear register (GPIOx_CLR) (x=A..E) ................................... 97
6.3.7 GPIO write protection register (GPIOx_WPR) (x=A..E) .................. 97
6.3.8 GPIO huge current control register (GPIOx_HDRV) (x=A..E).......... 97
7Multiplexed function I/Os (IOMUX) ................................................ 98
7.1 Introduction .................................................................................98
7.2 Function overview........................................................................98
7.2.1 IOMUX structure ......................................................................... 98
7.2.2 MUX Input configuration .............................................................. 99
7.2.3 MUX output or bidirectional MUX configuration ............................. 99
7.2.4 IOMUX map priority ..................................................................... 99
7.2.4.1 Hardware preemption ............................................................ 100
7.2.4.2 Debug port priority ................................................................ 100
7.2.4.3 Other peripheral output priority .............................................. 100
7.2.5 External interrupt/wake-up lines ..................................................100
7.3 Multiplexed input/output (IOMUX)................................................ 101
7.4 IOMUX registers ........................................................................ 109

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7.4.1 Event output control register (IOMUX_EVTOUT) ..........................109
7.4.2 IOMUX remap register (IOMUX_REMAP) .....................................110
7.4.3 IOMUX external interrupt configuration register1 (IOMUX_EXINTC1)112
7.4.4 IOMUX external interrupt configuration register2 (IOMUX_EXINTC2)113
7.4.5 IOMUX external interrupt configuration register3 (IOMUX_EXINTC3)113
7.4.6 IOMUX external interrupt configuration register4 (IOMUX_EXINTC4)114
7.4.7 IOMUX remap register2 (IOMUX_REMAP2) .................................115
7.4.8 IOMUX remap register3 (IOMUX_REMAP3) .................................115
7.4.9 IOMUX remap register4 (IOMUX_REMAP4) .................................116
7.4.10 IOMUX remap register5 (IOMUX_REMAP5) .................................116
7.4.11 IOMUX remap register6 (IOMUX_REMAP6) .................................117
7.4.12 IOMUX remap register7 (IOMUX_REMAP7) .................................119
7.4.13 IOMUX remap register8 (IOMUX_REMAP8) .................................121
8External interrupt/Event controller (EXINT) ................................ 122
8.1 EXINT introduction..................................................................... 122
8.2 Function overview and configuration procedure ............................ 122
8.3 EXINT registers ......................................................................... 123
8.3.1 Interrupt enable register (EXINT_INTEN).....................................123
8.3.2 Event enable register (EXINT_EVTEN) ........................................123
8.3.3 Polarity configuration register1 (EXINT_ POLCFG1).....................123
8.3.4 Polarity configuration register2 (EXINT_ POLCFG2).....................124
8.3.5 Software trigger register (EXINT_ SWTRG)..................................124
8.3.6 Interrupt status register (EXINT_ INTSTS) ...................................124
9DMA controller (DMA) ................................................................. 125
9.1 Introduction ............................................................................... 125
9.2 Main features ............................................................................ 125
9.3 Function overview...................................................................... 126
9.3.1 DMA configuration......................................................................126
9.3.2 Handshake mechanism ...............................................................126
9.3.3 Arbiter .......................................................................................127
9.3.4 Programmable data transfer width ...............................................127
9.3.5 Errors ........................................................................................128
9.3.6 Interrupts...................................................................................128

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9.3.7 Fixed DMA request mapping .......................................................128
9.3.8 Flexible DMA request mapping....................................................130
9.4 DMA registers............................................................................ 131
9.4.1 DMA interrupt status register (DMA_STS) ....................................132
9.4.2 DMA interrupt flag clear register (DMA_CLR) ...............................134
9.4.3 DMA channelx configuration register (DMA_CxCTRL) (x = 1…7) 136
9.4.4 DMA channelx number of data register (DMA_CxDTCNT) (x = 1…7)137
9.4.5 DMA channelx peripheral address register (DMA_CxPADDR) (x = 1…7)
137
9.4.6 DMA channelx memory address register (DMA_CxMADDR) (x = 1…7)137
9.4.7 Channel source register (DMA_SRC_SEL0) .................................137
9.4.8 Channel source register1 (DMA_SRC_SEL1) ...............................138
10 CRC calculation unit (CRC)......................................................... 139
10.1 CRC introduction ....................................................................... 139
10.2 CRC functional description ......................................................... 139
10.3 CRC registers............................................................................ 140
10.3.1 Data register (CRC_DT)..............................................................140
10.3.2 Common data register (CRC_CDT)..............................................140
10.3.3 Control register (CRC_CTRL)......................................................141
10.3.4 Initialization register (CRC_IDT) .................................................141
11 I2C interface ................................................................................ 142
11.1 I2C introduction.......................................................................... 142
11.2 I2C main features....................................................................... 142
11.3 I2C function overview ................................................................. 142
11.4 I2C interface .............................................................................. 143
11.4.1 I2C slave communication flow......................................................145
11.4.2 I2C master communication flow ...................................................147
11.4.3 Utilize DMA for data transfer.......................................................154
11.4.4 SMBus.......................................................................................154
11.4.5 I2C interrupt requests .................................................................156
11.4.6 I2C debug mode .........................................................................156
11.5 I2C registers .............................................................................. 157
11.5.1 Control register1 (I2C_CTRL1)....................................................157

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11.5.2 Control register2 (I2C_CTRL2)....................................................158
11.5.3 Own address register 1 (I2C_OADDR1) .......................................159
11.5.4 Own address register 2 (I2C_OADDR2) .......................................159
11.5.5 Data register (I2C_DT) ...............................................................160
11.5.6 Status register1 (I2C_STS1) .......................................................160
11.5.7 Status register 2 (I2C_STS2) ......................................................162
11.5.8 Clock control register (I2C_ CLKCTRL) .......................................163
11.5.9 I2C timer rise time register (I2C_TMRISE) ...................................163
12 Universal synchronous/asynchronous receiver/transmitter (USART)164
12.1 USART introduction ................................................................... 164
12.2 Full-duplex/half-duplex selector .................................................. 166
12.3 Mode selector............................................................................ 166
12.3.1 Introduction................................................................................166
12.3.2 Configuration procedure .............................................................166
12.4 USART frame format and configuration........................................ 169
12.5 DMA transfer introduction ........................................................... 170
12.5.1 Transmission using DMA ............................................................170
12.5.2 Reception using DMA .................................................................170
12.6 Baud rate generation.................................................................. 171
12.6.1 Introduction................................................................................171
12.6.2 Configuration .............................................................................171
12.7 Transmitter................................................................................ 172
12.7.1 Transmitter introduction..............................................................172
12.7.2 Transmitter configuration ............................................................172
12.8 Receiver ................................................................................... 173
12.8.1 Receiver introduction..................................................................173
12.8.2 Receiver configuration................................................................173
12.8.3 Start bit and noise detection .......................................................174
12.9 Interrupt requests ...................................................................... 175
12.10I/O pin control............................................................................ 176
12.11USART registers........................................................................ 176
12.11.1 Status register (USART_STS) ..................................................176
12.11.2 Data register (USART_DT).......................................................177

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12.11.3 Baud rate register (USART_BAUDR) ........................................177
12.11.4 Control register1 (USART_CTRL1) ...........................................178
12.11.5 Control register2 (USART_CTRL2) ...........................................179
12.11.6 Control register3 (USART_CTRL3) ...........................................180
12.11.7 Guard time and divider register (GDIV) .....................................181
13 Serial peripheral interface (SPI).................................................. 182
13.1 SPI introduction ......................................................................... 182
13.2 Function overview...................................................................... 182
13.2.1SPI description...........................................................................182
13.2.2 Full-duplex/half-duplex selector ..................................................183
13.2.3 Chip select controller..................................................................185
13.2.4 SPI_SCK controller ....................................................................186
13.2.5 CRC ..........................................................................................186
13.2.6 DMA transfer..............................................................................187
13.2.7 Transmitter ................................................................................187
13.2.8 Receiver ....................................................................................188
13.2.9 Motorola mode ...........................................................................188
13.2.10 Interrupt..................................................................................191
13.2.11 IO pin control ..........................................................................191
13.2.12 Precautions.............................................................................192
13.3 I2S functional description............................................................ 192
13.3.1 I2S introduction ..........................................................................192
13.3.2I2S full-duplex ............................................................................193
13.3.3 Operation mode selector.............................................................193
13.3.4 Audio protocol selector ...............................................................194
13.3.5 I2S_CLK controller .....................................................................195
13.3.6 DMA transfer..............................................................................198
13.3.7 Transmitter/Receiver ..................................................................198
13.3.8 I2S communication timings ..........................................................199
13.3.9 Interrupts...................................................................................199
13.3.10 IO pin control ..........................................................................200
13.4 SPI registers ............................................................................. 201
13.4.1 SPI control register1 (SPI_CTRL1) (Not used in I2S mode) ...........201
13.4.2 SPI control register2 (SPI_CTRL2) ..............................................202

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13.4.3 SPI status register (SPI_STS) .....................................................203
13.4.4 SPI data register (SPI_DT) .........................................................204
13.4.5 SPICRC register (SPI_CPOLY) (Not used in I2S mode).................204
13.4.6 SPIRxCRC register (SPI_RCRC) (Not used in I2S mode)..............204
13.4.7 SPITxCRC register (SPI_TCRC)..................................................204
13.4.8 SPI_I2S register (SPI_I2SCTRL) .................................................204
13.4.9 SPI_I2S prescaler register (SPI_I2SCLKP) ..................................205
14 Timer .......................................................................................... 206
14.1 Basic timer (TMR6 and TMR7) .................................................... 207
14.1.1 TMR6 and TMR7 introduction......................................................207
14.1.2 TMR6 and TMR7 main features ...................................................207
14.1.3 TMR6 and TMR7 function overview .............................................207
14.1.3.1 Counting clock...................................................................... 207
14.1.3.2 Counting mode ..................................................................... 207
14.1.3.3 Debug mode ......................................................................... 209
14.1.4 TMR6 and TMR7 registers ..........................................................209
14.1.4.1 TMR6 and TMR7 control register1 (TMRx_CTRL1)................... 210
14.1.4.2 TMR6 and TMR7 control register2 (TMRx_CTRL2)................... 210
14.1.4.3 TMR6 and TMR7 DMA/interrupt enable register (TMRx_IDEN) .. 211
14.1.4.4 TMR6 and TMR7 interrupt status register (TMRx_ISTS) ........... 211
14.1.4.5 TMR6 and TMR7 software event register (TMRx_SWEVT) ........ 211
14.1.4.6 TMR6 and TMR7 counter value (TMRx_CVAL) ........................ 211
14.1.4.7 TMR6 and TMR7 division (TMRx_DIV) .................................... 211
14.1.4.8 TMR6 and TMR7 period register (TMRx_PR) ........................... 211
14.2 General-purpose timer (TMR2 to TMR5) ...................................... 212
14.2.1 TMRx introduction ......................................................................212
14.2.2 TMRx main features ...................................................................212
14.2.3 TMRx functional overview ...........................................................213
14.2.3.1 Counting clock...................................................................... 213
14.2.3.2 Counting mode ..................................................................... 216
14.2.3.3 TMR input function................................................................ 219
14.2.3.4 TMR output function.............................................................. 221
14.2.3.5 TMR synchronization............................................................. 224
14.2.3.6 Debug mode ......................................................................... 227
14.2.4 TMRx registers...........................................................................227
14.2.4.1 Control register1 (TMRx_CTRL1) ........................................... 228

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14.2.4.2 Control register2 (TMRx_CTRL2) ........................................... 229
14.2.4.3 Slave timer control register (TMRx_STCTRL) .......................... 229
14.2.4.4 DMA/interrupt enable register (TMRx_IDEN) ........................... 230
14.2.4.5 Interrupt status register (TMRx_ISTS) .................................... 231
14.2.4.6 Software event register (TMRx_SWEVT) ................................. 232
14.2.4.7 Channel mode register1 (TMRx_CM1) .................................... 233
14.2.4.8 Channel mode register2 (TMRx_CM2) .................................... 235
14.2.4.9 Channel control register (TMRx_CCTRL) ................................ 236
14.2.4.10 Counter value (TMRx_CVAL) ............................................. 237
14.2.4.11 Division value (TMRx_DIV) ................................................ 237
14.2.4.12 Period register (TMRx_PR) ................................................ 237
14.2.4.13 Channel 1 data register (TMRx_C1DT) ............................... 237
14.2.4.14 Channel 2 data register (TMRx_C2DT) ............................... 237
14.2.4.15 Channel 3 data register (TMRx_C3DT) ............................... 238
14.2.4.16 Channel 4 data register (TMRx_C4DT) ............................... 238
14.2.4.17 DMA control register (TMRx_DMACTRL)............................. 238
14.2.4.18 DMA data register (TMRx_DMADT) .................................... 239
14.3 General-purpose timer (TMR9 to TMR14) .................................... 239
14.3.1 TMRx introduction ......................................................................239
14.3.2 TMRx main features ...................................................................239
14.3.2.1 TMR9 and TMR12 main features ............................................ 239
14.3.2.2 TMR10, TMR11, TMR13 and TMR14 main features .................. 239
14.3.3 TMRx functional overview ...........................................................240
14.3.3.1 Counting clock...................................................................... 240
14.3.3.2 Counting mode ..................................................................... 242
14.3.3.3 TMR input function................................................................ 243
14.3.3.4 TMR output function.............................................................. 245
14.3.3.5 TMR synchronization............................................................. 248
14.3.3.6 Debug mode ......................................................................... 249
14.3.4 TMR9 and TMR12 registers ........................................................249
14.3.4.1 Control register1 (TMRx_CTRL1) ........................................... 250
14.3.4.2 Slave timer control register (TMRx_STCTRL) .......................... 251
14.3.4.3 DMA/interrupt enable register (TMRx_IDEN) ........................... 251
14.3.4.4 Interrupt status register (TMRx_ISTS) .................................... 252
14.3.4.5 Software event register (TMRx_SWEVT) ................................. 252
14.3.4.6 Channel mode register1 (TMRx_CM1) .................................... 253
14.3.4.7 Channel control register (TMRx_CCTRL) ................................ 255
14.3.4.8 Counter value (TMRx_CVAL) ................................................. 256

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14.3.4.9 Division value (TMRx_DIV) .................................................... 256
14.3.4.10 Period register (TMRx_PR) ................................................ 256
14.3.4.11 Channel 1 data register (TMRx_C1DT) ............................... 256
14.3.4.12 Channel 2 data register (TMRx_C2DT) ............................... 256
14.3.5 TMR10, TMR11, TMR13 and TMR14 registers..............................257
14.3.5.1 Control register1 (TMRx_CTRL1) ........................................... 258
14.3.5.2 DMA/interrupt enable register (TMRx_IDEN) ........................... 258
14.3.5.3 Interrupt status register (TMRx_ISTS) .................................... 258
14.3.5.4 Software event register (TMRx_SWEVT) ................................. 259
14.3.5.5 Channel mode register1 (TMRx_CM1) .................................... 259
14.3.5.6 Channel control register (TMRx_CCTRL) ................................ 261
14.3.5.7 Counter value (TMRx_CVAL) ................................................. 261
14.3.5.8 Division value (TMRx_DIV) .................................................... 261
14.3.5.9 Period register (TMRx_PR) .................................................... 262
14.3.5.10 Channel 1 data register (TMRx_C1DT) ............................... 263
14.4 Advanced-control timers (TMR1 and TMR8) ................................. 263
14.4.1 TMR1 and TMR8 introduction......................................................263
14.4.2 TMR1 and TMR8 main features ...................................................263
14.4.3 TMR1 and TMR8 functional overview...........................................264
14.4.3.1 Counting clock...................................................................... 264
14.4.3.2 Counting mode ..................................................................... 267
14.4.3.3 TMR input function................................................................ 272
14.4.3.4 TMR output function.............................................................. 274
14.4.3.5 TMR break function............................................................... 278
14.4.3.6 TMR synchronization............................................................. 280
14.4.3.7 Debug mode ......................................................................... 281
14.4.4 TMR1 and TMR8 registers ..........................................................281
14.4.4.1 TMR1 and TMR8 control register1 (TMRx_CTRL1)................... 282
14.4.4.2 TMR1 and TMR8 control register2 (TMRx_CTRL2)................... 283
14.4.4.3 TMR1 and TMR8 slave timer control register (TMRx_STCTRL) . 284
14.4.4.4 TMR1 and TMR8 DMA/interrupt enable register (TMRx_IDEN) .. 285
14.4.4.5 TMR1 and TMR8 interrupt status register (TMRx_ISTS) ........... 286
14.4.4.6 Software event register (TMRx_SWEVT) ................................. 287
14.4.4.7 TMR1 and TMR8 channel mode register1 (TMRx_CM1)............ 288
14.4.4.8 Channel mode register2 (TMRx_CM2) .................................... 290
14.4.4.9 Channel control register (TMRx_CCTRL) ................................ 291
14.4.4.10 TMR1 and TMR8 counter value (TMRx_CVAL)..................... 294
14.4.4.11 TMR1 and TMR8 division value (TMRx_DIV) ....................... 294

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14.4.4.12 TMR1 and TMR8 period register (TMRx_PR) ....................... 294
14.4.4.13 TMR1 and TMR8 repetition period register (TMRx_RPR) ...... 294
14.4.4.14 TMR1 and TMR8 channel 1 data register (TMRx_C1DT)....... 294
14.4.4.15 TMR1 and TMR8 channel 2 data register (TMRx_C2DT)....... 294
14.4.4.16 TMR1 and TMR8 channel 3 data register (TMRx_C3DT)....... 295
14.4.4.17 TMR1 and TMR8 channel 4 data register (TMRx_C4DT)....... 295
14.4.4.18 TMR1 and TMR8 break register (TMRx_BRK) ...................... 295
14.4.4.19 TMR1 and TMR8 DMA control register (TMRx_ DMACTRL) .. 296
14.4.4.20 TMR1 and TMR8 DMA data register (TMRx_ DMADT) .......... 297
15 Window watchdog timer (WWDT) ................................................ 298
15.1 WWDT introduction .................................................................... 298
15.2 WWDT main features ................................................................. 298
15.3 WWDT functional overview ......................................................... 298
15.4 Debug mode.............................................................................. 299
15.5 WWDT registers ........................................................................ 299
15.5.1 Control register (WWDT_CTRL) ..................................................299
15.5.2 Configuration register (WWDT_CFG) ...........................................299
15.5.3 Status register (WWDT_STS)......................................................300
16 Watchdog timer (WDT) ................................................................ 301
16.1 WDT introduction ....................................................................... 301
16.2 WDT main features .................................................................... 301
16.3 WDT functional overview ............................................................ 301
16.4 Debug mode.............................................................................. 302
16.5 WDT registers ........................................................................... 302
16.5.1 Command register (WDT_CMD) ..................................................303
16.5.2 Divider register (WDT_DIV).........................................................303
16.5.3 Reload register (WDT_RLD)........................................................303
16.5.4 Status register (WDT_STS).........................................................303
17 Real-time clock (RTC) ................................................................. 304
17.1 RTC introduction........................................................................ 304
17.2 RTC main features ..................................................................... 304
17.3 RTC structure............................................................................ 304

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17.4 RTC functional overview............................................................. 305
17.4.1 Configuring RTC registers...........................................................305
17.4.2 Reading RTC registers ...............................................................306
17.4.3 RTC interrupts ...........................................................................306
17.5 RTC registers ............................................................................ 307
17.5.1 RTC control register high (RTC_CTRLH) .....................................307
17.5.2 RTC control register low (RTC_CTRLL) .......................................308
17.5.3 RTC divider register (RTC_ DIVH/RTC_DIVL) ..............................308
17.5.4 RTC divider counter register (RTC_DIVCNTH/RTC_DIVCNTL)......309
17.5.5 RTC counter value register (RTC_CNTH/RTC_CNTL) ...................309
17.5.6 RTC alarm register (RTC_TAH/RTC_TAL) ...................................309
18 Battery powered registers (BPR) ................................................ 310
18.1 BPR introduction........................................................................ 310
18.2 BPR main features..................................................................... 310
18.3 BPR functional overview............................................................. 310
18.4 BPR registers ............................................................................ 310
18.4.1 Battery powered data register x (BPR_DTx) (x = 1 … 42) .............311
18.4.2 RTC calibration register (BPR_ RTCCAL) ....................................311
18.4.3 BPR control register (BPR_ CTRL) ..............................................312
18.4.4 BPR control/status register (BPR_CTRLSTS)...............................313
19 Analog-to-digital converter (ADC)............................................... 314
19.1 ADC introduction ....................................................................... 314
19.2 ADC main features..................................................................... 314
19.3 ADC structure............................................................................ 314
19.4 ADC functional overview............................................................. 315
19.4.1 Channel management.................................................................315
19.4.1.1 Internal temperature sensor ................................................... 316
19.4.1.2 Internal reference voltage...................................................... 316
19.4.2 ADC operation process...............................................................316
19.4.2.1 Power-on and calibration ....................................................... 317
19.4.2.2 Trigger................................................................................. 317
19.4.2.3 Sampling and conversion sequence........................................ 318
19.4.3 Conversion sequence management .............................................319

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19.4.3.1 Sequence mode .................................................................... 319
19.4.3.2 Automatic preempted group conversion mode ......................... 319
19.4.3.3 Repetition mode.................................................................... 320
19.4.3.4 Partition mode ...................................................................... 320
19.4.4 Data management ......................................................................321
19.4.4.1 Data alignment ..................................................................... 321
19.4.4.2 Data read ............................................................................. 321
19.4.5 Voltage monitor..........................................................................321
19.4.6 Status flag and interrupts............................................................321
19.5 Master/Slave mode .................................................................... 322
19.5.1 Data management ......................................................................322
19.5.2Regular simultaneous mode ........................................................322
19.5.3 Alternate preempted trigger mode ...............................................323
19.5.4 Regular switch mode ..................................................................324
19.6 ADC registers............................................................................ 325
19.6.1 ADC status register (ADC_STS) ..................................................326
19.6.2 ADC control register1 (ADC_CTRL1) ...........................................326
19.6.3 ADC control register2 (ADC_CTRL2) ...........................................328
19.6.4 ADC sampling time register 1 (ADC_SPT1)..................................330
19.6.5 ADC sampling time register 2 (ADC_SPT2)..................................332
19.6.6 ADC preempted channel data offset register x
(ADC_PCDTOx) (x=1..4).......................................................................334
19.6.7 ADC voltage monitor high threshold register (ADC_VWHB)...........334
19.6.8 ADC voltage monitor low threshold register (ADC_VWLB).............334
19.6.9 ADC ordinary sequence register 1 (ADC_OSQ1) ..........................334
19.6.10 ADC ordinary sequence register 2 (ADC_ OSQ2) ......................334
19.6.11 ADC ordinary sequence register 3 (ADC_ OSQ3) ......................335
19.6.12 ADC preempted sequence register (ADC_ PSQ)........................335
19.6.13 ADC preempted data register x (ADC_ PDTx) (x=1..4) ...............335
19.6.14 ADC ordinary data register (ADC_ ODT) ...................................335
20 Digital-to-analog converter (DAC)............................................... 336
20.1 DAC introduction ....................................................................... 336
20.2 DAC main features..................................................................... 336
20.3 Design tips................................................................................ 336

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20.4 Function overview...................................................................... 337
20.4.1 Trigger events............................................................................337
20.4.2 Noise/Triangular-wave generation ...............................................337
20.4.3 DAC data alignment ...................................................................339
20.5 DAC registers............................................................................ 339
20.5.1 DAC control register (DAC_CTRL)...............................................339
20.5.2 DAC software trigger register (DAC_SWTRG) ..............................342
20.5.3 DAC1 12-bit right-aligned data holding register (DAC_D1DTH12R)342
20.5.4 DAC1 12-bit left-aligned data holding register (DAC_D1DTH12L) ..342
20.5.5 DAC1 8-bit right-aligned data holding register (DAC_ D1DTH8R) ..342
20.5.6 DAC2 12-bit right-aligned data holding register (DAC_D2DTH12R)342
20.5.7 DAC2 12-bit left-aligned data holding register (DAC_D2DTH12L) ..343
20.5.8 DAC2 8-bit right-aligned data holding register (DAC_D2DTH8R) ...343
20.5.9 Dual DAC 12-bit right-aligned data holding register (DAC_DDTH12R)343
20.5.10 Dual DAC 12-bit left-aligned data holding register (DAC_DDTH12L)343
20.5.11 Dual DAC 8-bit right-aligned data holding register (DAC_DDTH8R)343
20.5.12 DAC1 data output register (DAC_D1ODT) .................................343
20.5.13 DAC2 data output register (DAC_D2ODT) .................................343
21 CAN ............................................................................................ 344
21.1 CAN introduction ....................................................................... 344
21.2 CAN main features..................................................................... 344
21.3 Baud rate .................................................................................. 344
21.4 Interrupt management ................................................................ 347
21.5 Design tips................................................................................ 348
21.6 Function overview...................................................................... 348
21.6.1 General description ....................................................................348
21.6.2 Operating modes........................................................................349
21.6.3Test modes ................................................................................349
21.6.4 Message filtering........................................................................350
21.6.5 Message transmission ................................................................352
21.6.6 Message reception .....................................................................354
21.6.7 Error management......................................................................354
21.7 CAN registers............................................................................ 355
21.7.1 CAN control and status registers .................................................356

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21.7.1.1 CAN master control register (CAN_MCTRL) ............................ 356
21.7.1.2 CAN master status register (CAN_MSTS)................................ 357
21.7.1.3 CAN transmit status register (CAN_TSTS) .............................. 359
21.7.1.4 CAN receive FIFO 0 register (CAN_RF0) ................................ 361
21.7.1.5 CAN receive FIFO 1 register (CAN_RF1) ................................ 362
21.7.1.6 CAN interrupt enable register (CAN_INTEN) ........................... 363
21.7.1.7 CAN error status register (CAN_ESTS) ................................... 364
21.7.1.8 CAN bit timing register (CAN_BTMG) ..................................... 365
21.7.2 CAN mailbox registers ................................................................366
21.7.2.1 Transmit mailbox identifier register (CAN_TMIx) (x=0..2) ......... 366
21.7.2.2 Transmit mailbox data length and time stamp register (CAN_TMCx)
(x=0..2) 367
21.7.2.3 Transmit mailbox data low register (CAN_TMDTLx) (x=0..2) ..... 367
21.7.2.4 Transmit mailbox data high register (CAN_TMDTHx) (x=0..2) ... 367
21.7.2.5 Receive FIFO mailbox identifier register (CAN_RFIx) (x=0..1) .. 367
21.7.2.6 Receive FIFO mailbox data length and time stamp register
(CAN_RFCx) (x=0..1) ......................................................................... 368
21.7.2.7 Receive FIFO mailbox data low register (CAN_RFDTLx) (x=0..1)368
21.7.2.8 Receive FIFO mailbox data high register (CAN_RFDTHx) (x=0..1)368
21.7.3 CAN filter registers.....................................................................369
21.7.3.1 CAN filter control register (CAN_FCTRL) ................................ 369
21.7.3.2 CAN filter mode configuration register (CAN_FMCFG) ............. 369
21.7.3.3 CAN filter bit width configuration register (CAN_FBWCFG)....... 369
21.7.3.4 CAN filter FIFO association register (CAN_FRF) ..................... 369
21.7.3.5 CAN filter activation control register (CAN_ FACFG)................ 369
21.7.3.6 CAN filter bank i filter bit register (CAN_ FiFBx) (i=0..13; x=1..2)370
22 External memory controller ........................................................ 371
22.1 XMC introduction ....................................................................... 371
22.2 XMC main features .................................................................... 371
22.3 XMC architecture ....................................................................... 372
22.3.1 Block diagram ............................................................................372
22.3.2 Address mapping .......................................................................373
22.4 NOR/PSRAM ............................................................................. 374
22.4.1 Operation mode .........................................................................374
22.4.2 Access mode .............................................................................375
22.4.2.1 Read/write operation with the same timings ............................ 375

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22.4.2.2 Read/write operation with different timings.............................. 380
22.4.2.3 Multiplexed mode.................................................................. 388
22.4.2.4 Synchronous mode................................................................ 390
22.5 NAND ....................................................................................... 392
22.5.1 Operation mode .........................................................................392
22.5.2 Access timings...........................................................................393
22.5.3 ECC computation .......................................................................395
22.6 XMC registers............................................................................ 395
22.6.1 NOR Flash and PSRAM control registers .....................................396
22.6.1.1 SRAM/NOR Flash chip select control register 1 (XMC_BK1CTRL1)396
22.6.1.2 SRAM/NOR Flash chip select control register 4 (XMC_BK1CTRL4)397
22.6.1.3 SRAM/NOR Flash chip select timing register 1, 4
(XMC_BK1CTRL1, 4) ......................................................................... 399
22.6.1.4 SRAM/NOR Flash write timing register 1, 4 (XMC_BK1TMGWR1, 4)400
22.6.1.5 SRAM/NOR Flash extra timing register 1, 4 (XMC_EXT1, 4) ..... 400
22.6.2 NAND Flash control registers......................................................401
22.6.2.1 NAND Flash control register 2 (XMC_BK2CTRL) ..................... 401
22.6.2.2 Interrupt enable and FIFO status register 2 (XMC_BK2IS) ........ 402
22.6.2.3 Regular memory timing register 2 (XMC_ BK2TMGRG) ............ 402
22.6.2.4 Special memory timing register 2 (XMC_ BK2TMGSP) ............. 403
22.6.2.5 ECC value register 2 (XMC_ BK2ECC) ................................... 403
23 SDIO interface............................................................................. 404
23.1 SDIO introduction ...................................................................... 404
23.2 SDIO main features.................................................................... 404
23.3 SDIO main features.................................................................... 406
23.3.1 Card functional description .........................................................406
23.3.1.1 Card identification mode........................................................ 406
23.3.1.2 Data transfer mode ............................................................... 407
23.3.1.3 Erase................................................................................... 408
23.3.1.4 Protection management......................................................... 408
23.3.2 Commands and responses ..........................................................411
23.3.2.1 Commands ........................................................................... 411
23.3.2.2 Response formats ................................................................. 415
23.3.3 SDIO functional description ........................................................417
23.3.3.1 SDIO adapter ....................................................................... 418
23.3.3.2 Data BUF ............................................................................. 422

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23.3.3.3 SDIO AHB interface .............................................................. 422
23.3.3.4 Hardware flow control............................................................ 423
23.3.4 SDIO I/O card-specific operations ...............................................423
23.4 SDIO registers........................................................................... 424
23.4.1 SDIO power control register (SDIO_ PWRCTRL) ..........................424
23.4.2 SDIO clock control register (SDIO_ CLKCTRL) ............................425
23.4.3 SDIO argument register (SDIO_ARG) ..........................................426
23.4.4 SDIO command register (SDIO_CMD) .........................................426
23.4.5 SDIO command response register (SDIO_RSPCMD) ....................427
23.4.6 SDIO response 1..4 register (SDIO_RSPx) ..................................427
23.4.7 SDIO data timer register (SDIO_DTTMR).....................................427
23.4.8 SDIO data length register (SDIO_DTLEN)....................................427
23.4.9 SDIO data control register (SDIO_DTCTRL).................................428
23.4.10 SDIO data counter register (SDIO_DTCNTR) ............................429
23.4.11 SDIO status register (SDIO_STS).............................................429
23.4.12 SDIO clear interrupt register (SDIO_INTCLR)............................430
23.4.13 SDIO interrupt mask register (SDIO_INTEN) .............................431
23.4.14 SDIOBUF counter register (SDIO_BUFCNTR) ...........................433
23.4.15 SDIO data BUF register (SDIO_BUF)........................................433
24 Universal serial bus full-seed device interface (USBFS) ............. 434
24.1 USBFS introduction.................................................................... 434
24.2 USBFS clock and pin configuration.............................................. 434
24.2.1 USB clock configuration..............................................................434
24.2.2 USB pin configuration.................................................................434
24.3 USBFS functional description...................................................... 434
24.3.1 USB initialization........................................................................434
24.3.2 Endpoint configuration................................................................435
24.3.3 USB buffer.................................................................................435
24.3.4 Double-buffered endpoints..........................................................436
24.3.5 SOF output ................................................................................437
24.3.6 Suspend/Resume .......................................................................437
24.4 USB interrupts........................................................................... 437
24.5 USBFS registers ........................................................................ 437
24.5.1 USBFS endpoint n register (USBFS_EPTn), n=[0..7] ....................438

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24.5.2 USBFS control register (USBFS_CTRL).......................................439
24.5.3 USBFS interrupt status register (USBFS_INTSTS) .......................440
24.5.4 USBFS SOF frame number register (USBFS_SOFRNUM) .............441
24.5.5 USBFS device address register (USBFS_DEVADDR) ...................441
24.5.6 USBFS buffer table address register (USBFS_BUFTBL) ...............441
24.5.7 USBFS CFG control register (USBFS_CFG).................................441
24.5.8 USBFS transmission buffer first address register (USBFS_TnADDR)442
24.5.9 USBFS transmission data length register-n (USBFS_TnLEN)........442
24.5.10 USBFS reception buffer first address register-n (USBFS_RnADDR)442
24.5.11 USBFS reception data length register-n (USBFS_RnLEN)..........442
25 HICK auto clock calibration (ACC) .............................................. 443
25.1 ACC introduction ....................................................................... 443
25.2 Main features ............................................................................ 443
25.3 Interrupt requests ...................................................................... 443
25.4 Functional description ................................................................ 444
25.5 Principle.................................................................................... 445
25.6 ACC registers............................................................................ 446
25.6.1 Status register (ACC_STS) .........................................................446
25.6.2 Control register 1 (ACC_CTRL1) .................................................447
25.6.3 Control register 2 (ACC_CTRL2) .................................................448
25.6.4 Compare value 1 (ACC_C1) ........................................................448
25.6.5 Compare value 2 (ACC_C2) ........................................................448
25.6.6 Compare value 3 (ACC_C3) ........................................................449
26 Debug (DEBUG) .......................................................................... 450
26.1 Debug introduction..................................................................... 450
26.2 Debug and Trace ....................................................................... 450
26.3 I/O pin control............................................................................ 450
26.4 DEBUG registers ....................................................................... 451
26.4.1 DEBUG device ID (DEBUG_IDCODE)..........................................451
26.4.2 DEBUG control register (DEBUG_CTRL) .....................................452
27 Revision history.......................................................................... 454