Motorola SPX3BUM/D User manual

Welcome to Sandpoint, Motorola’s flexible processor development platform. Using Sandpoint
you can evaluate current Motorola host processors and integrated processors based on the
PowerPC architecture using MPMC (Motorola Processor PCI Mezzanine Cards). These cards
are interchangable and one Sandpoint platform can support numerous processor-specific
PPMC cards (but just one at a time).
This user’s manual covers the following issues:
Topic Page
Section 1, “Introduction” 2
Section 2, “Setup” 4
Section 3, “Configuration” 7
Section 4, “Programmers Model” 16
Section 5, “Initializing Sandpoint” 22
Section 6, “Development Issues” 23
Section 7, “Troubleshooting” 27
Section 8, “FAQ” 30
To locate any published errata or updates for this document, refer to the Motorola website.
User’s Manual
SPX3BUM/D
Rev. 1.2, 2/2003
Sandpoint Microprocessor
Evaluation System
User’s Manual

2 MOTOROLA
1 Introduction
The Sandpoint III motherboard, or “SP3” for short, is an evaluation baseboard which accepts one Motorola
Processor PMC (MPMC) or PrPMC card, as well as up to four PCI cards, and supplies typical PC-I/O
peripherals. Sandpoint provides a flexible base for the evaluation of new Motorola processor devices, and
for early software design for customer project using Motorola processors. Figure 1 shows a block diagram
of the Sandpoint III system.
Figure 1. Sandpoint III Block Diagram
Motorola
MPMC
Board
PCI Slots
Winbond
IDE
IDE
SuperIO
KBD
MSE
SPF100
COM1
COM2
PAR FLP
ROM1
ROM2 NVRM

MOTOROLA 3
1.1 Features
SP3 has the following features:
• One MPMC slot for a processor board (PrPMC compatible with PCI arbitration extensions).
• Two 32-bit PCI slots (5V)
• Two 32/64-bit PCI slots (5V)
• PMC and PCI slots auto-sense/auto-select 33 or 66 MHz operation.
• Two standard 16650-compatible ESD-protected serial ports.
• IEEE 1284 parallel port.
• Floppy disk port.
• Two ATA33 bus-master IDE ports.
• PS/2 mouse and keyboard connectors.
• BBVRAM; 8K bytes
•Real-TimeClock.
• Switch-selectable operating modes.
• Advanced Power Controller (“soft on/off”).
• LED monitors for critical functions.
The I/O subsystem is identical to that of the Sandpoint 2 and the “EC” version of the older Yellowknife
development platform. When properly configured, software written for these platforms should operate
identically when executed on a Sandpoint 3.

4 MOTOROLA
2 Setup
Sandpoint 3 is shipped ready to run the DINK debugger software. If you will be running other operating
systems, refer to the respective installation and setup instructions. Many OSes will communicate using the
same serial port DINK does, so the following setup may apply as well.
To setup your system, you will need the following material:
• Sandpoint 3 system
• Mac, PC or workstation running a terminal program.
• Null-modem cable.
Figure 2. Sandpoint III Setup Diagram
STEP 1
Connect the Sandpoint to a 120 VAC source using the supplied AC power code. For international operation
at 240 VAC, replace the connector with an appropriately-keyed power cable.
STEP 2
Turn the power supply on using the switch at the back of the Sandpoint chassis near the power cord. The
system will not turn on at this time.
STEP 3
Attach a null-modem cable between the Sandpoint COM1 port (top-most as shown in Figure 2) to the PC
(or workstation) serial port (usually COM1).
STEP 4
Startup a terminal emulator program. Common terminal emulators include “Hyperterminal”, available for
free with most Windows PCs, and many commercial programs such as Hayes “SmartComm”. Setup the PCs
terminal program to use the following settings:
• 9600 Baud
• 8 Bits
• No Parity
1
COM1 COM2
1
COM1 COM2
',1.!!JR

MOTOROLA 5
•1StopBit
• No Handshaking
• Terminal Emulation: any
STEP 5
Turn on the Sandpoint by pushing the power switch on the front of the chassis. DINK will start and print a
banner:
###### ### # # # # ##### #####
# # # ## # # # # # # #
# # # # # # # # # #
# # # # # # ## ##### #####
# # # # # # # # # #
# # # # ## # # # # #
###### ### # # # # ##### #######
( ( ( ( (AltiVec) ) ) ) )
Version : 12.2, Metaware Build
Released : Jan 31, 2001
Written by : Motorola’s RISC Applications Group, Austin, TX
System : Sandpoint with Altimus/Talos (MPMC60x/7xx/74xx)
Processor : MPC7400 V2.8 @ 500 MHz, Memory @ 100 MHz
Memory : Map B (CHRP), 00000000...03FFFFFF
Copyright Motorola Inc. 1993-2001
Refer to ‘history.c’ for release info, changes, errata and fixes.
DINK32_MAX >>
At this point, DINK is ready to accept user commands such as downloading and starting code or assembling
user programs. Refer to the DINK User’s Manual for more details on using DINK. If you are using another
ROM, such as for an OS, follow the instructions for the ROM.

6 MOTOROLA
2.1 Null Modem Cable
Since both Sandpoint 3 and the PC or workstation it communicates with are computers and therefore are
DTEs (Data Terminal Equipments), a special serial cable known as a null-modem cable is required. These
cables are readily available from computer supply stores. In addition, it is simple to make, as shown in
Figure 3.
Figure 3. Null Modem Diagram
Once the cable is available or constructed, attach one end to the Sandpoint COM1 port and the other to the
PC/Workstation. Either end will work with either computer.
DB9 Female
Back View
1
59
6
2
3
48
7
DB9 Female
Back View
1
59
6
2
3
48
7

MOTOROLA 7
3 Configuration
Sandpoint 3 is shipped ready to run the DINK firmware by default. The following configuration options are
preset:
• MPMC is the PCI arbiter.
• MPMC is the interrupt controller using Serial-EPIC.
Occasionally, however, software will require other configurations, which Sandpoint supports to a limited
extent. This is often done to make a Sandpoint more closely resemble the target development platform.
Configurable features include:
• Using an external PCI arbiter instead of the PMC-resident arbiter.
• Using the 8259 PIC in the Winbond instead of the PMC interrupt controller.
• PnP (Plug-and-Play) PC I/O devices can remain uninitialized and ‘virtually’ disappear.
Another reason to change the configuration is to use the legacy modes for Sandpoint 2 compatibility. Refer
to Appendix A for details on legacy configurations. All options on Sandpoint 3 are set via two ‘DIP’
switches, as shown in Figure 4.
Figure 4. Sandpoint 3 in an ATX Chassis
POWER
SUPPLY
WINBOND
WINBOND SW2
SW1
POWER
SWITCH

8 MOTOROLA
The switches have the same orientation; with the system standing vertically, the switches operate as shown
in Figure 5
Figure 5. Sandpoint 3 SW1/SW2 Configuration Switches
All configuration switches should be changed with the power off; changes only take effect on a system
power-on reset. The system pushbutton reset is not necessarily sufficient.
3.1 SW1 Options
SW1 is located near the bottom of the Sandpoint 3 board, near the end of the fourth PCI slot. It controls the
features shown in Table 1:
Table 1. Sandpoint 3 SW1 Options
Switch Name Definition Default
1 ROMSEL ROM Selection
2 ROM1WP ROM1 Write Protect
3 reserved reserved
4 FRCPCI33 Force PCI to 33MHz
5 EXTCLK Use external clock
6 SSCLK Spread-Spectrum Clock

21
RIGHT = ON
LEFT = OFF

MOTOROLA 9
3.1.1 ROMSEL
The “ROMSEL” switch may be used to select between the primary and secondary flash device (if any) on
the Sandpoint 3.
NOTE: Not all Sandpoint 3’s have a secondary flash.
NOTE: The RMODE switch (see Section 3.3.2) overrides this switch.
3.1.2 ROM1WP
The “ROM1WP” switch may be used to write-protect the secondary (backup) PCI-hosted bootROM, if any.
This primary ROM normally contains the DINK debugger, but with the backup ROM protected, users may
overwrite the boot ROMs with development code and still return to DINK as a backup measure.
NOTE: Not all Sandpoint 3’s have a secondary flash.
3.1.3 Reserved
Switch SW2-3 is reserved and has no function.
7 SSRNG Spread-Spectrum Range
8 PSON Force Power Supply ON
Table 2. Sandpoint 3 ROMSEL Option
ROMSEL Definition Notes
SW1-1
On (right) Primary ROM (29F040) is used for PCI boot
option. Normal mode.
Off (left) SecondaryROM (28F800) is used for PCI boot
option.
Table 3. Sandpoint 3 ROM1WP Switch
ROM1WP Definition Notes
SW1-2
On (right) ROM1 may be read to or written from. Use to store OS code.
Off (left) ROM1 is write-protected.
Table 1. Sandpoint 3 SW1 Options
Switch Name Definition Default

10 MOTOROLA
3.1.4 FRCPCI33
The “FRCPCI33” switch may be used to cause the PCI bus to operate at 33 MHz regardless of the status of
the M66EN signal, which normally allows the PCI bus to automatically select 66 MHz PCI. This switch is
normally enabled, forcing only 33 MHz operation since the Winbond component does not support 66 MHz
operation.
It may be possible to operate the PCI bus at 66 MHz if software does not use the Winbond or the ISA bus.
3.1.5 EXTCLK
The “EXTCLK” switch allows the user to switch from the standard, on-board 33/66 MHz PCI bus clock
generator, from which all other clocks are derived, to an externally-supplied clock signal. This allows testing
the system at different frequencies other than the standard 33 MHz or 66 MHz frequencies supported.
The clock source must be attached to the coaxial SMA connector on the board,and the clocksignal supplied
must meet the requirements listed in Table 6.
NOTE: Care must be used that the devices receiving the clock are capable of and are configured to operate
at the new clock speed. In particular, Motorola processors have internal PLLs which require a minimum
clock input to operate properly.
NOTE: The external clock source must be on before power is applied to the Sandpoint.
Table 4. Sandpoint 3 FRCPCI33 Switch
Force PCI33 Definition Notes
SW1-4
On (right) Force 33 MHz PCI only. Normal mode.
Off (left) Allow automatic 33/66 MHz PCI. Experimental purposes only.
Table 5. Sandpoint 3 EXTCLK Switch
EXTCLK Definition Notes
SW1-5
On (right) Normal clock mode Normal mode.
Off (left) Accept clock from SMA connector. Use for testing.
Table 6. Sandpoint 3 External Clock
Requirements
Parameter Value
ZIN 50 Ω
VIN 3V

MOTOROLA 11
3.1.6 SSCLK
The spread-spectrum enable (“SSCLK”) switch allows the user to enable and evaluate the spread-spectrum
clock generator (SSCG) option. If enabled, the SSCG modulates the PCI base clock frequency by a
selectable amount (see Section 3.1.7).
NOTE: The Sandpoint system is not guaranteed to operate if the SSCLK switch is set; this is for testing
purposes only.
3.1.7 SSRNG
The spread-spectrum range (“SSRNG”) switch allows the user to change the amount of modulation applied
to the PCI clock signals if the SSCG is enabled (see Section 3.1.6).
3.1.8 PSON
The “PSON” switch allows the user to force the system to power up whenever AC power is applied to the
system power supply. Normally, the system power is controlled with the APC in the SuperIO chip, and
power is controlled through the chassis switch, motherboard pushbutton, or APC under software control. If
PSON is selected, the system remains on until external power is removed.
Table 7. Sandpoint 3 SSCLK Switch
SSCLK Definition Notes
SW1-6
On (right) PCI clocks are modulated by -1.25% or -3.75%. Use for testing.
Off (left) Normal PCI clocks. Normal mode.
Table 8. Sandpoint 3 SSRNG Switch
SSRNG Definition Notes
SW1-7
On (right) -3.75% modulation:
66 MHz PCI:63.5 ... 66.0 MHz
33 MHz PCI:31.8 ... 33.0 MHz
Normal mode.
Off (left) -1.25% modulation:
66 MHz PCI:65.2 ... 66.0 MHz
33 MHz PCI:32.6 ... 33.0 MHz
Table 9. Sandpoint 3 PSON Switch
PSON Definition Notes
SW1-8
On (right) Force power on always. Normal mode.
Off (left) Normal power control mode

12 MOTOROLA
3.2 SW2 Options
SW2 is located near the top of the Sandpoint 3 board, near the socketed flash ROM socket, between the
PMC and the floppy connector. This switch controls the features shown in Table 10:
3.2.1 RESERVED
These switches are reserved. On SP3 systems prior to serial #6000, or those without a revision “C” label,
these switches implemented the AMODE arbitration mode select switches. These options are no longer
supported and older SP3 systems should be upgraded.
SP3 exclusively uses the Winbond as the system arbiter; requests are assigned as follows:
WB_REQ(0) = PMC_REQ(0)
WB_REQ(1) = SLOT_REQ(1)
WB_REQ(2) = SLOT_REQ(2)
WB_REQ(3) = SLOT_REQ(3)
WB_REQ(4) = SLOT_REQ(4)
And grants are handled correspondingly.
Table 10. Sandpoint 3 SW2 Options
Switch Name Definition Default
1 & 2 RESERVED none
3 ILEGACY Interrupt Legacy Modes
4 & 5 IMODE Interrupt Architecture
6 RMODE ROM Mode
7&8 USER User Options

MOTOROLA 13
3.3 ILEGACY
The ILEGACY switch is used to select between standard SP3 interrupt connections and support for legacy
interrupt connections.
3.3.1 IMODE
The IMODE switches are connected to the SPF FPGA to configure the PCI interrupt connections.
3.3.1.1 IMODE Serial
When IMODE is set such that Serial is selected, the SPF100 enables an internal serial multiplexer that works
with the serial demultiplexer in the EPIC portion of the MPC107 or MPC824X on MPMC cards. This allows
many interrupts to be conveyed to the MPMC than would normally be possible with the four allocated pins.
shows the serial ‘slot’ corresponding to each external interrupt
Table 11. Sandpoint 3 ILEGACY Switches
ILEGACY Definition Notes
SW2-3
On (right) Standard SP3 Interrupt Modes Default
Off (left) Legacy Sandpoint 1/2 Interrupt Modes See Appendix B
Table 12. Sandpoint 3 IMode Switches
IMODE[0:1] Definition Notes
SW2-4 SW2-5
On (right) On (right) Serial Default.
On (right) Off (left) Wire-OR
Off (left) On (right) Slot Not available on all systems.
Off (left) Off (left) reserved
Table 13. Sandpoint 3 Serial Interrupt Slot Assignment
Slot Interrupt Source Note
0 SIOINT Inverted, so active low
1 reserved reserved
2 SLOT #1 INTA# from each slot.
3 SLOT #2
4 SLOT #3
5 SLOT #4
6 WinBond INTA# No specific function

14 MOTOROLA
3.3.1.2 IMODE WireOR
When IMODE is set such that the WireOR option is selected, the MPMC will merge all interrupt inputs into
one, and the SPF100 work in tandem to provide arbitration handling for all possible PCI devices. Requests
are assigned as follows:
PMC_INT(0) = SLOT_INT(1) OR
SLOT_INT(2) OR
SLOT_INT(3) OR
SLOT_INT(4) OR
SIOINT (inverted).
The other MPMC interrupt pins (1 to 3) are not asserted. Software must generally poll known devices to
clear the interrupt status, so Wire-OR is a very weak architecture but it is effective in checking that interrupt
signalling is setup properly, and suitable for embedded systems with minimal interrupt requirements.
3.3.1.3 IMODE Slots
NOTE: This mode is only available with the updated SPF100r2 or SPF100Z VHDL equation set, and is
present on updated SPX3 systems with serial numbers after 5150.
When IMODE is set such that the Slots option is selected, the MPMC will accept interrupts from the four
PCI slots, and ignore the Winbond and SuperIO devices. This mode is appropriate for systems which will
not be using such devices and want all PCI slot interrupts. Interrupts are connected as shown in Table 14.
For single-interrupt cards (the vast majority), there is a one-to-one correspondence between the slot and the
PMC interrupt input (shown in bold entries in Table 14.).
7 WinBond INTB# No specific function
8 WinBond INTC# IDE Interrupt
9 WinBond INTD# IDE Interrupt
10 reserved reserved
11
12
13
14
15
Table 14. . Sandpoint 3 PCI Slot Sharing
Slot 1 Slot 2 Slot 3 Slot 4 Bus Destination
INTA# INTD# INTC# INTB# SLOT_INT(1) PMC INT(0)
INTB# INTA# INTD# INTC# SLOT_INT(2) PMC INT(1)
INTC# INTB# INTA# INTD# SLOT_INT(3) PMC INT(2)
INTD# INTC# INTB# INTA# SLOT_INT(4) PMC INT(3)
Table 13. Sandpoint 3 Serial Interrupt Slot Assignment
Slot Interrupt Source Note

MOTOROLA 15
3.3.2 RMODE
The RMODE switch is used to select an alternate method of addressing the dual flash devices.
NOTE: This switch overrides the ROMSEL switch (see Section 3.1.1).
NOTE: Not all Sandpoint 3’s have a secondary flash.
3.3.3 USER
The USER switches are connected to the SuperIO GPIO port #1, bits 2 and 3, respectively. Sandpoint 3
makes no use of these switch settings, they are provided for user-defined functions.
See Section 4 for details on reading the GPIO port.
Table 15. Sandpoint 3 RMode Switches
RMODE Definition Notes
SW2-6
On (right) ROMSEL governs ROM/Flash access Default
Off (left) Primary ROM: 0xFFF0_0000 ... 0xFFFF_FFFF
Secondary ROM: 0xFF80_0000 ... 0xFFEF_FFFF
Table 16. Sandpoint 3 USER Switches
USER[0:1] Definition Notes
SW2-7 SW2-8
On (right) On (right) GPIO1 = ”XXXX00XX” Default
On (right) Off (left) GPIO1 = ”XXXX01XX”
Off (left) On (right) GPIO1 = ”XXXX10XX”
Off (left) Off (left) GPIO1 = ”XXXX11XX”

16 MOTOROLA
4 Programmers Model
This section describes support information which may be useful to hardware or software designers who are
using Sandpoint 3.
4.1 Address Map
Table 17 shows the general address map of the Sandpoint 3, and Table 18 shows the specific location of
ISA/PCI I/O addresses. Both tables assume Map “B” (CHRP), which is the default and officially
encouraged standard.
NOTES:
1. Requires memory control registers to be properly programmed (MCCR[1:4], MS[E]AR[1:2], ME[E]AR[1:2], MBEN).
2. MPC107 or MPC8245 only.
3. Only software-enabled PCI devices appear in this space.
4. Only software-enabled PCI/ISA I/O devices appear in this space.
The detailed address map in Table 18 assumes that the PnP devices have not been changed from the default
locations.
Table 17. Global Address Map
START END Definition Notes
0000_0000 3FFF_FFFF SDRAM 1
4000_0000 77FF_FFFF reserved
7800_0000 7BFF_FFFF RCS3 ROM space 2
7C00_0000 7FFF_FFFF RCS2 ROM space 2
8000_0000 FCFF_FFFF PCI memory 3
FD00_0000 FDFF_FFFF PCI/ISA memory
FE00_0000 FEBF_FFFF PCI/ISA I/O space 4
FEC0_0000 FEDF_FFFF PCI configuration
address register
FEE0_0000 FEEF_FFFF PCI configuration data
register
FEF0_0000 FEFF_FFFF Interrupt Acknowledge
FF00_0000 FF7F_FFFF RCS1 ROM space
FF80_0000 FFFF_FFFF RCS0 ROM space
(Boot ROM)
Table 18. Detailed ISA I/O Address Map
Start End Mode Device Register Notes
FE00_0000 --- R/W WB DMA Channel 0 Base/Current Address

MOTOROLA 17
FE00_0001 --- R/W WB DMA Channel 0 Base/Current Word
FE00_0002 --- R/W WB DMA Channel 1 Base/Current Address
FE00_0003 --- R/W WB DMA Channel 1 Base/Current Word
FE00_0004 --- R/W WB DMA Channel 2 Base/Current Address
FE00_0005 --- R/W WB DMA Channel 2 Base/Current Word
FE00_0006 --- R/W WB DMA Channel 3 Base/Current Address
FE00_0007 --- R/W WB DMA Channel 3 Base/Current Word
FE00_0008 --- R WB DMA Controller 1 Status
W DMA Controller 1 Command
FE00_0009 --- W WB DMA Controller 1 Request
FE00_000A --- W WB DMA Controller 1 Mask
FE00_000B --- W WB DMA Controller 1 Mode
FE00_000C --- W WB DMA Controller 1 Clear Byte Pointer
FE00_000D --- W WB DMA Controller 1 Master Clear
FE00_000E --- W WB DMA Controller 1 Clear Mask
FE00_000F --- W WB DMA Controller 1 Write All Mask
FE00_0010 FE00_001F unassigned
FE00_0020 --- R/W WB PIC 1 Command
FE00_0021 --- R/W WB PIC 1 Command
FE00_0022 FE00_003F unassigned
FE00_0040 --- R/W WB Counter 0
FE00_0041 --- R/W WB Counter 1
FE00_0042 --- R/W WB Counter 2
FE00_0043 --- W WB Timer/Counter Control
FE00_0044 FE00_005F unassigned
FE00_0060 --- R/W SIO Keyboard Controller Data 1
FE00_0061 --- R/W WB NMI Status/Control
FE00_0062 FE00_0063 unassigned
FE00_0064 --- R/W SIO Keyboard Controller Command 1
FE00_0065 FE00_006F unassigned
FE00_0070 --- R/W SIO RTC/APC Index 1
--- W WB RTC Index (shadow)
Table 18. Detailed ISA I/O Address Map
Start End Mode Device Register Notes

18 MOTOROLA
FE00_0071 --- unassigned
FE00_0072 --- R/W SIO NVRAM Address
FE00_0073 --- R/W SIO NVRAM Data
FE00_0074 --- R/W SIO External NVRAM Address (MSB) 3
FE00_0075 --- R/W SIO External NVRAM Address (LSB) 3
FE00_0076 --- R/W SIO External NVRAM Data 3
FE00_0077 ---
FE00_0078 FF80_0079 R/W WB BIOS Timer
FE00_007A FF80_007B R/W WB BIOS Timer Reserved
FE00_007C FE00_007F unassigned
FE00_0080 --- - WB DMA Reserved Page
FE00_0081 --- R/W WB DMA Memory Page 2
FE00_0082 --- R/W WB DMA Memory Page 3
FE00_0083 --- R/W WB DMA Memory Page 1
FE00_0084 FF80_0086 - WB DMA Reserved Page
FE00_0087 --- R/W WB DMA Memory Page 0
FE00_0088 --- - WB DMA Reserved Page
FE00_0089 --- R/W WB DMA Memory Page 6
FE00_008A --- R/W WB DMA Memory Page 7
FE00_008B --- R/W WB DMA Memory Page 5
FE00_008C FF80_008E - WB DMA Reserved Page
FE00_008F FE00_0091 unassigned
FE00_0092 --- R/W WB Port 92: System Reset
FE00_0093 FE00_009F unassigned
FE00_00A0 --- R/W WB PIC 2 Command
FE00_00A1 --- R/W WB PIC 2 Command
FE00_00A2 FE00_00BF unassigned
FE00_00C0 --- R/W WB DMA Channel 4 Base/Current Address
FE00_00C1 --- R/W WB DMA Channel 4 Base/Current Word
FE00_00C2 FE00_00C3 unassigned
FE00_00C4 --- R/W WB DMA Channel 5 Base/Current Address
FE00_00C5 unassigned
Table 18. Detailed ISA I/O Address Map
Start End Mode Device Register Notes

MOTOROLA 19
FE00_00C6 --- R/W WB DMA Channel 5 Base/Current Word
FE00_00C7 unassigned
FE00_00C8 --- R/W WB DMA Channel 6 Base/Current Address
FE00_00C9 unassigned
FE00_00CA --- R/W WB DMA Channel 6 Base/Current Word
FE00_00CB unassigned
FE00_00CC --- R/W WB DMA Channel 7 Base/Current Address
FE00_00CD unassigned
FE00_00CE --- R/W WB DMA Channel 7 Base/Current Word
FE00_00CF unassigned
FE00_00D0 R WB DMA Controller 2 Status
"W WB DMA Controller 2 Command
FE00_00D3 unassigned
FE00_00D2 --- W WB DMA Controller 2 Request
FE00_00D3 unassigned
FE00_00D4 --- W WB DMA Controller 2 Mask
FE00_00D5 unassigned
FE00_00D6 --- W WB DMA Controller 2 Mode W
FE00_00D7 unassigned
FE00_00D8 --- W WB DMA Controller 2 Clear Byte Pointer
FE00_00D9 unassigned
FE00_00DA --- W WB DMA Controller 2 Master Clear
FE00_00DB unassigned
FE00_00DC --- W WB DMA Controller 2 Clear Mask
FE00_00DD unassigned
FE00_00DE --- W WB DMA Controller 2 Write All Mask
FE00_00DF FE00_00EF unassigned
FE00_00F0 --- W WB Coprocessor Error
FE00_00F1 FE00_015B unassigned
FE00_015C --- R/W SIO PnP Index Register
FE00_015D --- R/W SIO PnP Data Register
FE00_015E FE00_016F unassigned
Table 18. Detailed ISA I/O Address Map
Start End Mode Device Register Notes

20 MOTOROLA
FE00_0170 FE00_0177 R/W WB IDE Channel 2 Primary
FE00_0178 FE00_01EF unassigned
FE00_01F0 FE00_01F7 R/W WB IDE Channel 1 Primary
FE00_01F8 FE00_0277 unassigned
FE00_0278 FE00_027F R/W SIO Parallel Port Registers 1
FE00_0280 FE00_02F7 unassigned
FE00_02F8 FE00_02FF R/W SIO COM2 UART Registers 1
FE00_0300 FE00_0375 unassigned
FE00_0376 --- R/W WB IDE Channel 2 Secondary
FE00_0377 FE00_03F1 unassigned
FE00_03F2 FE00_03F3 R/W SIO FDC Floppy Registers 1
FE00_03F4 FE00_03F5 unassigned
FE00_03F6 --- R/W WB IDE Channel 1 Secondary
FE00_03F7 unassigned
FE00_03F8 FE00_03FF R/W SIO COM1 UART Registers 1
FE00_0400 FE00_0409 unassigned
FE00_040A --- R WB DMA Scatter/Gather Interrupt Status
FE00_040B --- W WB DMA Controller 1 Extended Mode
FE00_040C FE00_0414 unassigned
FE00_0415 --- W WB DMA Scatter/Gather Channel 5 Command
FE00_0416 --- W WB DMA Scatter/Gather Channel 6 Command
FE00_0417 --- W WB DMA Scatter/Gather Channel 7 Command
FE00_0418 FE00_041C unassigned
FE00_041D --- R WB DMA Scatter/Gather Channel 5 Status
FE00_041E --- R WB DMA Scatter/Gather Channel 6 Status
FE00_041F --- R WB DMA Scatter/Gather Channel 7 Status
FE00_0420 FE00_0433 unassigned
FE00_0434 FE00_0437 R/W WB DMA Scatter/Gather Channel 5 Table
Pointer
FE00_0438 FE00_043B R/W WB DMA Scatter/Gather Channel 6 Table
Pointer
FE00_043C FE00_043F R/W WB DMA Scatter/Gather Channel 7 Table
Pointer
Table 18. Detailed ISA I/O Address Map
Start End Mode Device Register Notes