Vitrek V15X-AA11 Manual

Model V15X-AA11
1
Installation and Setup
The Model V15X-AA11 is shipped in an anti-static bag with a styrofoam packing container.
Carefully remove the module from its anti-static bag and prepare to set the various options to
conform to the operating environment. Make sure that all anti-static precautions are taken to
avoid damaging the module.
For an initial test the V15X-AA11 and the VME Single Board Computer (SBC) may be plugged
together without any modification needed.
The following chart shows the strap/switch selections along with their default configurations.
If any of the user requirements vary from the default configuration, consult the following
sections for changing the parameter. Please refer to Appendix A of this manual for the location
of the straps and switches on the V15X-AA11.
Selectable Parameter Default Value
Slot0/Non-Slot0 Configuration Slot 0 Configuration
Logical Address 0
System Controller Enabled
Slot0 Configuration
The V15X-AA11 may be configured as a Slot0 controller or as a non-Slot0 controller. The
V15X-AA11 is shipped from the factory as a Slot0 controller. Several strap and switch setting
must be set to enable the V15X-AA11 Slot0 functionality. Refer to the SBC manual for
enabling the System Controller.
The V15X-AA11 must first be setup as system controller to assume the responsibilities of a
Slot0 controller. A switch setting on the V15X-AA11 must be set. The switch on the V15X-
AA11 is labeled SW2 and the switch location of interest is position 1. This switch must be
placed in the OPEN (1) position to allow the V15X-AA11 to function as a Slot0 controller. This
switch controls the direction of the VXIbus signals SYSCLK and BCLR. If the V15X-AA11
adapter is configured as a system controller, the must also be configured the same way.
The next selection to be made concerns the VXIbus MODID (Module ID) signal and an internal
signal on the V15X-AA11 indicating Slot0 operation. These selections are made via three of the
switch positions of switch SW2. Position 2 controls the internal indication for Slot0 operation.
This switch must be set to the OPEN (1) position for Slot0 operation. Position 3 of switch SW2
controls the MODID signal 825 ohm pulldown resistor. When the V15X-AA11 is in a Slot0
position, this switch must be set to the OPEN (1) position to disconnect the resistor from the
MODID signal since this resistor is provided on the VXI chassis backplane for the Slot0
position.

Model V15X-AA11
2
Position 4 of switch SW2 controls the connection of the 16.8Kohm pullup resistor to the MODID
signal. When the V15X-AA11 is configured as a Slot0 device, this switch position must be
CLOSED (0) to allow the MODID signal to be terminated with the pull-up resistor
The remaining setup of the V15X-AA11 adapter concerns the VXIbus signal CLK10. The
CLK10 signal is a 10 Megahertz timing clock generated by the Slot0 controller. A differential
ECL driver drives this signal onto the VXIbus. A set of straps on the V15X-AA11 adapter
controls whether this signal is sourced onto VXI by the internal clock of the V15X-AA11 or not
sourced by the V15X-AA11. To alter the selection, two straps must be moved. The V15X-AA11
is configured at the factory to source the CLK10 signal from the internal clock. This is enabled
by placing the two CLK10 straps into the INTERNAL position. You need to enable this for
Slot0 operation.
This concludes the configuration of the V15X-AA11 adapter for Slot0 operation. The SBC must
also be configured to operate as a system controller. Please refer to the SBC manual for
strap/switch locations along with a description of changing operating parameters.
Non-Slot0 Configuration
To setup the V15X-AA11 as a non-Slot0 device, the module must first be disabled from being
the system controller. The system controller function is usually an operation provided by a
Slot0 controller. A switch setting on the V15X-AA11 must be set. The switch on the V15X-
AA11 is labeled SW2 and the switch location of interest is position 1. This switch must be
placed in the CLOSED (0) position to allow the V15X-AA11 to function as a non-Slot0 device.
This switch controls the direction of the VXIbus signals SYSCLK and BCLR. Setting this
switch to the CLOSED (0) position enables the V15X-AA11 to receive the SYSCLK and BCLR
signals for non-Slot0 applications. If the V15X-AA11 adapter is not configured as a system
controller, the SBC must also be configured the same way.
The next selections to be made concerns the VXIbus MODID (Module ID) signal and an
internal signal on the V15X-AA11 indicating Slot0 operation. These selections are made via
three of the switch positions of switch SW2. Position 2 controls the internal indication for Slot0
operation. This switch must be set to the CLOSED (0) position for non-Slot0 operation.
Position 3 of switch SW2 controls the MODID signal 825 ohm pulldown resistor. If the V15X-
AA11 is to operate in a non-Slot0 configuration, this switch must be set to the CLOSED (0)
position allowing the pulldown resistor to connect to the MODID signal.
Position 4 of switch SW2 controls the connection of the 16.8Kohm pull-up resistor to the
MODID signal. When the V15X-AA11 is to be used in a non-Slot0 configuration, this switch
position must be set to the OPEN (1) position to disconnect the pull-up resistor from the
MODID signal.
The remaining setup of the V15X-AA11 adapter concerns the VXIbus signal CLK10. The
CLK10 signal is a 10 Megahertz timing clock generated by the Slot0 controller. A set of straps
on the V15X-AA11 adapter controls whether this signal is sourced onto VXI by the internal
clock of the V15X-AA11 or not sourced by the V15X-AA11. To alter the selection, two straps
must be moved. The V15X-AA11 is configured at the factory to source the CLK10 signal from
the internal clock. To disable driving CLK10, place the two CLK10 straps into the NC position.
This concludes the configuration of the V15X-AA11 adapter for non-Slot0 operation. The SBC

Model V15X-AA11
3
must also be configured to disable the system controller portion of the SBC. Please refer to the
SBC manual for strap/switch locations along with a description of changing operating
parameters.
Logical Address
The V15X-AA11 may be configured to operate as either a Slot0 controller or a non-Slot0
controller. When the V15X-AA11 is the Slot0 controller, it must be located in the left-most slot
(Slot0) and be set for Logical Address 0. If the V15X-AA11 is not the Slot0 controller, it may be
located in any other slot in the chassis and set for Logical Address 1 through 255. To statically
assign a Logical Address to the V15X-AA11, simply set the 8-position DIP switch to the desired
Logical Address in the range of 1 through 254. This sets the Logical Address of the V15X-AA11
and may only be altered by changing the setting on the DIP switch.
The V15X-AA11 may also be Dynamically Configured. A device that is Dynamically Configured
must have its Logical Address set to 255 (FF16). A device that is Dynamically Configured has
its Logical Address set by the Resource Manager when the Logical Address Register of the
V15X-AA11 is written. Dynamic Configuration is used to avoid conflicts in setting up a devices’
Logical Addresses. The Resource Manager makes use of the feature of the VXIbus to address
the various devices set at Logical Addresses of 255. This is accomplished by using the MODID
(Module Identification) signal, which provides a geographic addressing mechanism to each
individual slot location. A normal A16 address space transfer cycle is executed to a device with
its MODID signal asserted. This differentiates one device at Logical Address 255 from another.
After the device is addressed geographically, it is written with a new Logical Address number
assigned by the Resource Manager. Dynamic Configuration eliminates the need to preassign
Logical Addresses in a VXI chassis, as long as they are all set to 255 and allocated by the
Resource Manager.
The V15X-AA11 contains a set of 8 DIP switches used to set the Logical Address. These
switches represent a binary combination of numbers in the range of 0 to 255. The switch
settings are made by depressing each Logical Address switch to the desired location. A switch
that is in the OPEN position yields a bit set to a one. A switch that is in the CLOSED position
yields a bit set to a zero. The left-most switch corresponds to Logical Address bit 128 and the
right-most switch corresponds to Logical Address bit 1. Please refer to Appendix A for the
location and setting of the Logical Address switches. The following diagram shows the bit
pattern for the A16 Logical Base Address.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11
LA
128
LA
64
LA
32
LA
16
LA
8
LA
4
LA
2
LA
1000000
Bits 15 and 14 are set to one (VXI defined).
Bits 13 through 6 are user selectable using the Logical Address switches LA128 - LA1.
Bits 5 though 0 are set to 0 to indicate the beginning of a 64 byte block.
For statically configured devices, the setting of the Logical Address switches locks the devices’
Configuration Registers in A16 address space. Each device has an allocated configuration

Model V15X-AA11
4
address space of 64 bytes. The Logical Base Address of a device in A16 address space may then
be calculated using the following equation:
A16 Base Address = 0xC000 + (Logical Address shifted left 6 places)
For example, the A16 Base Address of a device set for Logical Address 2 is 0xC080. For a
device set to Logical Address 2, the following bit pattern is established for the base address.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1100000010000000
CLK10 Signal Generation
The VXIbus CLK10 signal is a 10 Megahertz differential ECL clock driven onto the bus by the
Slot0 controller. If the V15X-AA11 is used as a Slot0 controller, it must be configured to drive
this VXIbus signal. The signal source may be generated internally by the V15X-AA11.
A set of six straps, located near the P1/P2 connector for VXI, is used to configure the source of
the CLK10 signal. This set of straps actually controls the 2 CLK10 signals, +CLK10 and -
CLK10. When the straps are installed in the INT (INTERNAL) position, the CLK10 signals
are driven by a clock source on the V15X-AA11. If the V15X-AA11 is to be located in a non-
Slot0 position in the chassis, the CLK10 signals must be disabled from driving CLK10 by
placing the 2 sets of straps into the NC (NO CONNECTION) position.
Installation
After all the user selectable configuration parameters have been setup, the module may then be
inserted into the VXI chassis. If the V15X-AA11 is configured for Slot0 operation, insert the
V15X-AA11 into the left-most slot (Slot0) of the VXI chassis. For a non-Slot0 configuration,
insert the V15X-AA11 into any slot in the range of 1 through 13.
CAUTION: TURN OFF MAINFRAME POWER BEFORE INSERTING OR
REMOVING A VXIbus MODULE.
WARNING: REMEMBER TO REMOVE THE INTERRUPT ACKNOWLEDGE AND BUS GRANT DAISY CHAIN JUMPERS BEFORE
INSERTING A VXI MODULE
The VXIbus backplane must be properly configured before inserting a VXI module and applying
power. The Interrupt Acknowledge jumper must be removed from the slot in which the VXI
module is to be inserted. The Bus Grant jumpers must also be removed from the slot in which
the VXI module is to be inserted. All unoccupied slot locations must have the Interrupt
Acknowledge and Bus Grant jumpers installed so that the interrupt and grant continuity is not
disrupted by any open slots. When using backplanes that auto-configure, these steps are not

Model V15X-AA11
5
necessary since the installation of a VXI module in the chassis makes the required
configuration occur.
VXIbus Configuration Registers and Operational Registers
The following table shows the various registers located in A16 space for the V15X-AA11 Slot 0
Controller.
A16 Offset Write Access Read Access
0016 Logical Address Register Identification
0216 Reserved Device Type Register
0416 Status/Control Register Status/Control Register
0616 Reserved Reserved
0816 Write Signal Register Protocol Register
0A16 Reserved Response Register
0C16 Reserved Reserved
0E16 Data Low Register Data Low Register
1016 Reserved Reserved
1216 Reserved Reserved
1416 Reserved Reserved
1616 Reserved Reserved
1816 Reserved Reserved
1A16 Reserved Reserved
1C16 Reserved Reserved
1E16 Reserved Reserved
2016 Reserved Suffix High Register
2216 Reserved Suffix Low Register
2416 Reserved Serial Number High Register
2616 Reserved Serial Number Low Register
2816 Module ID Register Module ID Register
2A16 Reserved Interrupt Status Register
2C16 Interrupt Control Register Interrupt Control Register
2E16 Trigger Interrupt Mask Trigger Interrupt Source
3016 Trigger Interrupt Source Clear Reserved
3216 Trigger Source Register Reserved
3416 Trigger Timer Configuration Register Reserved
3616 Reserved Reserved
3816 SBC Slave Mode Configuration Reserved
3A16 Location Monitor Interrupt Control Register Interrupt Status ID Register
3C16 Miscellaneous Control Register Read Signal Register
3E16 Reserved Version Number Register
ID/Logical Address Register
The ID/Logical Address Register is a write/read register located at an offset of 0016 from the
A16 Logical Base Address. A read operation to this register returns the Device Class, the
addressing modes of the devices’ operational registers and the Manufacturers’ Identification. A

Model V15X-AA11
6
write operation to this register address is typically executed by the Resource Manager during a
Dynamic Configuration allocation sequence. During the sequence, the Resource Manager
allocates a Logical Address to the V15X-AA11 by writing a logical address value to the least
significant eight bits of this register. The format and bit assignments of this register are
shown in the following diagram. Since this register has write-only and read-only bits, two bit
patterns are shown.
On read transactions: 00h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only 1011111100101001
Class =
Extended Addressing Mode = A16 KineticSystems' Manufacturer ID = F2916 (3881)
Bit(s) Mnemonic Meaning
15:14 Device Class These bits are set to reflect the Device Class of the V15X-AA11.
This bit combination indicates that the V15X-AA11 is a Message
Based Device.
13:12 Address Space These bits are set to reflect the addressing mode(s) of the V15X-
AA11’s operational registers. Since all the communication
registers of the V15X-AA11 appear in A16 address space, the bits
in this field are both set to one.
11:0 Manufacturer This field reflects the manufacturer of a VXI device. This value is
3881(F2916) for KineticSystems.
On write transactions: 00h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write-only Not Used Logical Address
Bit(s) Mnemonic Meaning
15:8 Not Used These 8 bits are not used. A write operation to these bits has no effect
on the V15X-AA11.
7:0 128-LA1 Logical Address 128 through 1 are write-only bits used to set the
V15X-AA11’s Logical Address during a Dynamic Configuration cycle
executed by the Resource Manager. A Dynamic Configuration
sequence is performed on a VXI module when its logical address has
been set to 255 (FF16).
Device Type Register
The Device Type Register is a read-only register located at an offset of 0216 from the A16
Logical Base Address of the V15X-AA11. This register contains the Model Code of the V15X-
AA11. Since the V15X-AA11 is an A16-only device, the entire 16-bits of this field is used for
the Model Code.

Model V15X-AA11
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Model Codes for VXI Slot0 devices must be in the range of 0016 to FF16. Model Codes for non-
Slot0 devices must be in the range of 10016 to FFFF16. When the V15X-AA11 is configured for
non-Slot0 operation, the Model Code returned in this register is 15216. When the V15X-AA11 is
configured for Slot0 operation, the 10016 bit is set to zero, yielding a Model Code of 5216.
V15X-AA11 Model Codes:
15216 for non-Slot0 configurations
5216 for Slot0 configurations
The following diagram shows the bit pattern for the Device Type Register for both Slot0 and
non-Slot0 configurations.
For Slot0 Configurations:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only0000000001010010
For non-Slot0 Configurations:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only0000000101010010
Status/Control Register
The Status/Control Register is a write/read register located at an offset of 0416 from the A16
Logical Base Address of the V15X-AA11. This register contains write-only, read-only and
write/read bits. This register is used to monitor the Module ID VXI signal, control the
assertion of SYSFAIL, control Soft Reset, and check the status of the Power-On Self Test. The
following two diagrams show the Status/Control Register, one for read accesses and one for
write.
For read operations executed to the Status/Control Register: 04h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-Write 0MOD
ID* 1111111111RDYPASS
SYS
INH
SFT
RST
Bit(s) Mnemonic Meaning
15 Not Used This bit is not used and read as a zero.
14 MODID* This bit is set to a one if the module is not selected with the MODID
line on the VXI P2 connector. A zero indicates that the module is
selected by the MODID signal.

Model V15X-AA11
8
Bit(s) Mnemonic Meaning
13:4 Not Used These bits are not used and read as zeros.
3 READY Ready is a read-only bit that is set to a one indicating successful
completion of register initialization.
2 PASS Pass is a read-only bit that is set to a one when the V15X-AA11 has
completed its power-on self-test without any errors. If an error occurs,
this bit is set to a zero and the SYSFAIL signal is asserted by the
V15X-AA11.
1 SYS INH SYSFAIL INHIBIT. Reading this bit as a one indicates that the V15X-
AA11 is prevented from driving the backplane SYSFAIL line.
0 SFT RST SFT RST This bit is read as a one when the V15X-AA11 has been
placed into the Soft Reset state. Writing this register with this bit set
to a zero removes the V15X-AA11 from the soft reset state.
For write operations executed to the Status/Control Register: 04h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write-only Not Used SYS
INH
SFT
RST
Bit(s) Mnemonic Meaning
15:2 Not Used These bits are not used for write operations.
1 SYS INH SYSFAIL INHIBIT is a write/read bit used to inhibit the V15X-AA11
from asserting the backplane signal SYSFAIL. Setting this bit to a
one disables the assertion of SYSFAIL and a zero enables the signal.
0 SFT RST SOFT RESET is a write/read bit used to reset the V15X-AA11.
Setting this bit to a one places the V15X-AA11 in the soft reset state
and writing the bit to a zero removes the V15X-AA11 from the reset
state.
Protocol Register
The Protocol Register is a read-only register located at an offset of 0816 from the A16 Logical
Base Address of the V15X-AA11. The Protocol Register is accessed by executing a read to this
address location and the Signal Register is accessed by writing to this location. The Protocol
Register is used to define the communication capabilities of the Message Based Device. The
following diagram shows the bit layout of the Protocol Register of the V15X-AA11.

Model V15X-AA11
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08h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only CMDR* SGNL
REG* MSTR*INTRFHS*11111111111
Bit(s) Mnemonic Meaning
15 CMDR* COMMANDER is a read-only bit that is set to a one for a device that
only capable of Message Based Servant functions. A zero in this bit
location indicates that the device is capable of both Commander and
Servant Message Based functions. The V15X-AA11 sets this bit to a
zero indicating it has both Commander and Servant capability.
14 SGNL-REG* SIGNAL REGISTER is a read-only bit that is set to a one for a device
that does not contain a Signal Register. Devices that contain a Signal
Register set this bit to a zero. Since the V15X-AA11 contains a
functional Signal Register, this bit is set to a zero
13 MSTR* MASTER is a read-only bit that is set to a one for devices that do not
have VMEbus mastering capability. A zero for this bit location
indicates the device has the ability to become a VMEbus master. The
V15X-AA11 has VMEbus mastering capability and sets this bit to a
zero.
12 INTR INTERRUPTER is a read-only bit that indicates whether the device
can generate interrupts. A zero in this bit location indicates no
interrupting ability and a one indicates that the device can generate
interrupts. The V15X-AA11 can generate interrupts and sets this bit
to a one.
11 FHS*FAST HANDSHAKE is a read-only bit used to indicate whether a Message
based devices’ data register supports the Fast Handshake Mode.
This bit is set to a one if Fast Handshake is not supported and a zero
if Fast Handshake is supported. The V15X-AA11 does not support
the Fast Handshake transfer mode and sets this bit to a one.
10 SHR MEM* SHARED MEMORY is a read-only bit used to indicate if a device
implements shared memory. A zero in this bit location indicates that
shared memory is supported and a one indicates that it is not. The
V15X-AA11 does contain some amount of shared memory, but it does
not comply with the VXI specification for Shared Memory. Therefore,
the V15X-AA11 sets this bit to a one.
9:0 Not Used These bits are not used by the V15X-AA11 and returned as ones.
Write Signal Register
The Write Signal Register is a write-only register located at an offset of 0816 from the A16
Logical Base Address of the V15X-AA11. A write operation to this register address accesses the

Model V15X-AA11
10
Signal Register. This register is used for device to device signaling. This register can be read
at offset 3C16 in A16 address space. A signal received from a device contains the devices’
Logical Address along with a field for device specific information. There are two different
formats for the Signal Register, depending on the value of the most significant bit (bit 15). The
following two diagrams show the various formats.
08h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write-only 0 Response Logical Address
08h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write-only 0 Event Logical Address
The fields shown for the two Signal Register patterns are as follows:
Response: This field reflects bits 14 through 8 of the device’s Response Register.
Event: This field reflects the event associated with the signal.
Logical Address: This field reflects the Logical Address of the device generating the signal.
Response Register
The Response Register is a read-only register located at an offset of 0A16 from the A16 Logical
Base Address of the V15X-AA11. This register is used to return the status of a device’s
communication registers and their associated functions. The following diagram shows the bit
layout for the Response Register on the V15X-AA11. 0Ah
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only 0100ERR*
READ
RDY
WRT
RDY 111111111
Bit(s) Mnemonic Meaning
15 Not Used This bit is not used and read as a zero.
14 Not Used This bit is not used and read as a one.
13:12 Not Used These two bits are not used by the V15X-AA11 and returned
as zeros.
11 ERR ERROR is a read-only bit used to signify when an error
occurs in one of the serial protocols and has not yet been
reported. This bit is set and cleared by using the
Miscellaneous Control
Register located at offset 3C16.

Model V15X-AA11
11
Bit(s) Mnemonic Meaning
10 READ RDY READ READY is a read-only bit that is set to a one indicating
that the device’s Data Register(s) contain data to be read.
This bit is set to a one by executing a write operation to the
Miscellaneous Control Register with the SET READ READY
bit set to a one. After the READ READY bit has been set, it
is cleared when the Data Low Register is read.
9 WRT RDY WRITE READY is a read-only bit that is set to a one
indicating that the device is ready for data transfers to its
Data Register(s). This bit is set to a one by executing a write
to the Miscellaneous Control Register with the SET WRITE
READY bit set to a one. After the Data Low Register is
written, the WRITE READY bit is cleared.
8:0 Not Used These bits are not used by the V15X-AA11 and read as ones.
Data Low Register
The Data Low Register is a write/read register located at an offset of 0E16 from the A16 Logical
Base Address of the V15X-AA11. This register is used communicate data between two Message
Based Devices. Accessing this register causes the appropriate flags to be set/cleared in the
Response Register. Please refer to the Response Register for additional information.
The following diagram shows the bit pattern for the Data Low Register. 0Eh
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-Write 0MOD
ID* 1111111111RDYPASS
SYS
INH
SFT
RST
Bit(s) Mnemonic Meaning
15:0 W/R15:0 WRITE/READ DATA 15 through 0 are write/read bits used
to communicate data between two Message Based Devices.
Suffix High Register
The Suffix High Register is a read-only register located at an offset of 2016 from the A16 Logical
Base Address of the V15X-AA11. This register is used in combination with the Suffix Low
Register to determine the module model number suffix. The Suffix High Register contains the
first two ASCII characters of the suffix and the Suffix Low Register contains the last two
characters. The suffix shown is for the V15X-AA11-AA11 module.
The bit pattern for the Suffix High Register is as follows: 20h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only0100000101000001

Model V15X-AA11
12
Suffix Low Register
The Module Suffix Low Register is a read-only register located at an offset of 2216 from the A16
Logical Base Address of the V15X-AA11. This register is used in combination with the Suffix
High Register to determine the module model number suffix. The Suffix Low Register contains
the last two ASCII characters of the suffix and the Suffix High Register contains the first two
characters. The suffix shown is for the V15X-AA11-AA11 module.
The bit pattern for the Suffix Low Register is as follows: 22h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-only0011000100110001
Serial Number High Register
The Serial Number High Register is a read-only register located at an offset of 2416 from the
A16 Logical Base Address of the V15X-AA11. This register is used in conjunction with the
Serial Number Low Register to define the serial number of the V15X-AA11. The following
diagram shows the bit pattern of the Serial Number High Register. 24h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-Only SN
31
SN
30
SN
29
SN
28
SN
27
SN
26
SN
25
SN
24
SN
23
SN
22
SN
21
SN
20
SN
19
SN
18
SN
17
SN
16
Serial Number Low Register
The Serial Number Low Register is a read-only register located at an offset of 2616 from the A16
Logical Base Address of the V15X-AA11. This register is used in conjunction with the Serial
Number High Register to define the serial number of the V15X-AA11. The following diagram
shows the bit pattern of the Serial Number Low Register. 26h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-Only SN
15
SN
14
SN
13
SN
12
SN
11
SN
10
SN
9
SN
8
SN
7
SN
6
SN
5
SN
4
SN
3
SN
2
SN
1
SN
0
Module ID Register
The Module ID Register is a write/read register located at an offset of 2816 from the A16 Logical
Base Address of the V15X-AA11. This register is only available when the V15X-AA11 is
configured as a Slot0 device. The Module ID Register is used to control the MODID geographic
addressing lines on the VXI P2 connector. Each of the 13 slots of a VXI chassis has an

Model V15X-AA11
13
individual line that can be asserted and monitored through the Module ID Register. Before any
of the MODID lines can be asserted by the V15X-AA11, the Output Enable bit (bit 13) of this
register must be set to a one. When the outputs are enabled, setting a MODID bit location to a
one asserts the corresponding MODID signal.
The data read from this register does not necessarily reflect the data written. Instead, a read
of this register returns the actual state of the MODID signals on the VXI backplane.
The following diagram shows the bit pattern for the Module ID Register. 28h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-Write 00
MID
ENA
MID
12
MID
11
MID
10
MID
9
MID
8
MID
7
MID
6
MID
5
MID
4
MID
3
MID
2
MID
1
MID
0
Bit(s) Mnemonic Meaning
15:14 Not Used These bits are not used and read as ones.
13 MID ENA MODID OUTPUT ENABLE is a write/read bit used to
enable/disable the V15X-AA11 from driving the MODID signals.
Setting this bit to a one enables the drivers and a zero disables
them.
12:0 MID12:0 MODULE ID 12 through 0 is write/read bits used to assert and
monitor the 13 MODID signals. Writing a bit to a one asserts
the corresponding module’s MODID signal.
Interrupt Status Register
The Interrupt Status Register is a read-only register located at an offset of 2A16 from the A16
Logical Base Address of the V15X-AA11. The contents of this register are enabled onto the
VMEbus during an interrupt acknowledge cycle. This register contains the Logical Address of
the V15X-AA11 in the lower 8-bits of the register and the upper 8-bits contains the
cause/status of the interrupt. The lower 8-bits of this register return the Logical Address of the
V15X-AA11 only for interrupt acknowledges cycles. An I/O read of this field returns all 8-bits
set to ones.
The V15X-AA11 has two interrupt sources. One of the sources is from a preselected VXI
Trigger input and the other source is from Location Monitors. The VXI interrupt sources are
enabled through the Trigger Interrupt Mask Register located at offset 2E16. The Location
Monitor interrupt sources are enabled through the Location Monitor Interrupt Control Register
located at an offset of 3A16. These two registers must be appropriately enabled before the
V15X-AA11 can generate an interrupt source. The interrupt source(s) may then generate a
VXI interrupt request when interrupts are enabled in the Interrupt Control Register located at
an offset of 2C16.

Model V15X-AA11
14
The interrupt acknowledges cycle executed by the Interrupt Handler reads a 16-bit value from
the V15X-AA11. The lower 8-bits of this data reflects the Logical Address of the device
generating the interrupt. The upper 8-bits reflects the cause of the interrupt. Of the upper 8-
bits, only 2 of them are used by the V15X-AA11. Once an interrupt acknowledges cycle occurs,
the interrupt source bits that were set in this register when the interrupt vector was read are
reset to zero. This will also occur when the Interrupt Status Register is read.
The format of the Interrupt Status Register is as follows: 2Ah
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read-Only 000000LOC
MON
TRG
IN
LA
128
LA
64
LA
32
LA
16
LA
8
LA
4
LA
2
LA
1
Bit(s) Mnemonic Meaning
15:10 Not Used These bits are not used and read as zeros.
9 LOC MON LOCATION MONITOR INTERRUPT SOURCE is a read-and-
clear bit that is set when an interrupt source is generated by
one of the Location Monitor Interrupts enabled in the Location
Monitor Interrupt Control Register. To find out the actual
cause of the location monitor interrupt, the Location Monitor
Interrupt Control Register must be consulted.
8 TRG IN TRIGGER IN INTERRUPT SOURCE is a read-and-clear bit
that is set when an interrupt source is generated by one of the
enabled trigger input interrupt sources in the Trigger Interrupt
Mask Register. To find out the actual cause of the trigger input
interrupt, the Trigger Interrupt Source Register must be
consulted.
7:0 LA128:1 LOGICAL ADDRESS 128 through 1 return the Logical Address
of the V15X-AA11 during an interrupt acknowledge cycle to the
V15X-AA11. An I/O read of these bits return all ones.
Interrupt Control Register
The Interrupt Control Register is a write/read register located at an offset 2C16 from the A16
Logical Base Address of the V15X-AA11. This register is used to configure the V15X-AA11 for
interrupt sourcing. The Interrupt Request Level, Interrupt Enable, and Interrupt Source Mask
are contained in this register.
The format and description of the Interrupt Control Register are shown in the following
diagram. 2Ch
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Model V15X-AA11
15
Read-Write 111111
LOC
MON*
TRG
IN*
IR
ENA* 1IRQ S3
ORQ
S2
IRQ
S1 111
Bit(s) Mnemonic Meaning
5:10 Not Used These bits are not used and read as ones.
9 LOC MON* LOCATION MONITOR INTERRUPT ENABLE is a write/read
bit used to enable and disable the generation of a VXI interrupt
when one of the Location Monitor interrupt sources are enabled
in the Location Monitor Interrupt Control Register. Setting
this bit to a one disables the Location Monitor interrupts and a
zero enables the interrupt.
8 TRG IN* TRIGGER IN INTERRUPT ENABLE is a write/read bit used to
enable and disable the generation of a VXI interrupt when one
of the enabled interrupt sources in the Trigger Interrupt Mask
is generated. Setting this bit to a one disables the interrupts
and a zero enables the interrupt.
7 IR ENA* INTERRUPT REQUEST ENABLE is a write/read bit used to
enable/disable the V15X-AA11 from generating an interrupt
request to the VMEbus. Setting this bit to a one disables the
V15X-AA11 from generating an interrupt request and a zero
enables the interrupt request.
6 Not Used This bit is not used and read as a one.
5:3 IRQS3:1 INTERRUPT REQUEST SELECT 3 through 1 are write/read
bits used to select the desired interrupt request level that the
V15X-AA11 asserts when an interrupt is sourced.
The following chart shows the interrupt request level selections.
IRQ S3 IRQ S2 IRQ S1 Interrupt Request Level
000 IRQ7
001 IRQ6
010 IRQ5
011 IRQ4
100 IRQ3
101 IRQ2
110 IRQ1
111 Disconnected
2:0 Not Used These bits are not used and read as ones.
Trigger Interrupt Mask/Trigger Interrupt Source Register

Model V15X-AA11
16
The Trigger Interrupt Mask/Trigger Interrupt Source Register is located at an offset of 2E16
from the A16 Logical Base Address of the V15X-AA11. This register serves two purposes,
depending on the direction of the transfer. A write operation to this register address accesses
the Trigger Interrupt Mask Register. This register is used to enable and disable interrupts to
the VXI bus on the occurrence of a trigger condition. Trigger conditions include the 8 VXI TTL
Trigger lines, the two ECL VXI Trigger lines. A mask bit is set to a one to enable the interrupt
source and set to a zero to disable the source.
The second register at this address is the Trigger Interrupt Source Register. This read-only
register is used to determine which trigger event caused the interrupt source. Each bit read as
a one was involved in generating the trigger interrupt source. After an interrupt has been
generated and acknowledged, the Trigger Interrupt Source Clear Register must be written with
data to clear the individual interrupt source.
The following two diagrams show the two registers.
Trigger Interrupt Mask Register (Write-Only): 2Eh
151413129876543210
Write-Only Not Used ECL
TG1
ECL
TG0
TTL
TG7
TTL
TG6
TTL
TG5
TTL
TG4
TTL
TG3
TTL
TG2
TTL
TG1
TTL
TG0
Bit(s) Mnemonic Meaning
15:12 Not Used These bits are not used and setting them to ones does not have
any effect on the V15X-AA11.
9:8 ECL TG1:0 ECL TRIGGER 1 and 0 are write-only bits used to enable the
generation of a VXI interrupt when the corresponding VXI ECL
Trigger line is asserted. A bit set to a one enables the interrupt
source and a zero disables the interrupt source.
7:0 TTL TG1:0 TTL TRIGGER 7 and 0 are write-only bits used to enable the
generation of a VXI interrupt when the corresponding VXI TTL
Trigger line is asserted. A bit set to a one enables the interrupt
source and a zero disables the interrupt source.
Trigger Interrupt Source Register (read-only): 2Eh
151413129876543210
Read-Only 0000
ECL
TG1
ECL
TG0
TTL
TG7
TTL
TG6
TTL
TG5
TTL
TG4
TTL
TG3
TTL
TG2
TTL
TG1
TTL
TG0
Bit(s) Mnemonic Meaning
15:12 Not Used These bits are not used and read as zeros.
9:8 ECL TG1:0 ECL TRIGGER INTERRUPT 1 and 0 are read-only bits that

Model V15X-AA11
17
Bit(s) Mnemonic Meaning
are read as a one when the V15X-AA11 has received the
assertion of the corresponding VXI ECL Trigger line and the
Interrupt Mask bit was enabled. Reading this bit as a zero
indicates that the ECL Trigger line is not generating an
interrupt source.
9:8 TTL TG7:0 TTL TRIGGER INTERRUPT 7 through 0 are read-only bits
that are read as a one when the V15X-AA11 has received the
assertion of the corresponding VXI TTL Trigger line and the
Interrupt Mask bit was enabled. Reading this bit as a zero
indicates that the TTL Trigger line is not generating an
interrupt source.
Trigger Interrupt Source Clear Register
The Trigger Interrupt Source Cleat Register is a write-only register located at an offset of 3016
from the A16 Logical base Address of the V15X-AA11. This register is used to clear the
Interrupt Source bits in the Trigger Interrupt Source Register once they have been set by the
receipt of a preselected trigger input. Any bit location set to a one when writing to this register
clears the corresponding Interrupt Source bit. Any bit set to a zero has not effect on the
Interrupt Source. The following diagram shows the bit layout for the Trigger Interrupt Source
Clear Register. 30h
15 14 13 12 10 9 8 7 6 5 4 3 2 1 0
Write-Only Not Used Not
Used
ECL
TG1
ECL
TG0
TTL
TG7
TTL
TG6
TTL
TG5
TTL
TG4
TTL
TG3
TTL
TG2
TTL
TG1
TTL
TG0
Bit(s) Mnemonic Meaning
15:12 Not Used These bits are not used. Any write to these bit locations have
no effect on the V15X-AA11.
9:8 ECL TG1:0 CLEAR ECL TRIGGER INTERRUPT SOURCE 1 and 0 are
write-only bits used to clear the corresponding ECL trigger
interrupt source once set by the assertion of the signal.
7:0 TTL TG7:0 CLEAR TTL TRIGGER INTERRUPT SOURCE 7 through 0
are write-only bits used to clear the corresponding TTL trigger
interrupt source once set by the assertion of the signal.
Trigger Source Register
The Trigger Source Register is a write-only register located at an offset of 3216 from the A16
Logical Base Address of the V15X-AA11. This register is used to source the VXI ECL, VXI
TTL. This register allows the trigger signals to be either asserted, negated or pulsed. The
binary combination of bits 15 and 14 of this register determine what action is to be taken on

Model V15X-AA11
18
the selected trigger signals. The following chart shows the binary combination of the control
bits and the effect they have on the selected trigger signals.
CNTL1 CNTL0 Effect On Trigger Signal
0 0 Assertion
01 Negation
10 Pulse
11 Reserved
When a trigger is asserted through the Trigger Source Register, it remains asserted until
either a reset condition occurs or the Trigger Source Register is written to negate the trigger
signal. A pulsed output lasts for approximately 1.5 microseconds.
The following diagram shows the bit pattern for the Trigger Source Register. 32h
151413129876543210
Write-Only CNTL 1 Not Used ECL
TG1
ECL
TG0
TTL
TG7
TTL
TG6
TTL
TG5
TTL
TG4
TTL
TG3
TTL
TG2
TTL
TG1
TTL
TG0
Bit(s) Mnemonic Meaning
15:14 CNTL1:0 CONTROL 1 and 0 are write-only bits used to define the
operation to be performed on the requested trigger signal. The
binary combination of these bits determine what action to take
on the selected trigger signals. The previous chart shows the
required binary combinations to set, clear and pulse the trigger
signals.
13:12 Not Used These bits are not used and may be written with any data
pattern.
9:8 ECL TG1:0 ECL TRIGGER 1 and 0 are set to a one when writing to this
register to allow the selected operation specified by the control
bits to occur to the VXI ECL Trigger lines. Any trigger bit set
to a zero when writing to this register has no effect on the
trigger signal itself.
7:0 TTL TG7:0 TTL TRIGGER 7 through 0 are set to a one when writing to
this register to allow the selected operation specified by the
control bits to occur to the VXI TTL Trigger lines. Any trigger
bit set to a zero when writing to this register has no effect on
the trigger signal itself.
Trigger Timer Configuration Register
The Trigger Timer Configuration Register is a write-only register located at an offset of 3416
from the A16 Logical Base Address of the V15X-AA11. This register is used to configure the
timer interval and specify the trigger signals to assert once the Trigger Timer expires. The
Trigger Timer, which is a 32-bit modulo-n type counter, can be tied to any or all of the trigger

Model V15X-AA11
19
signals. At a predetermined interval, the enabled trigger signals are pulsed for a period of
approximately 1.5 microseconds.
The actual register accessed through this A16 address offset is determined by the four most
significant bits of the Miscellaneous Control Register at offset 3C16. The binary combination of
these four bits specify the register to be accessed as shown in the following table.
RSEL3 RSEL2 RSEL1 RSEL0 Register Accessed
0 0 0 0 Trigger Timer Low
0 0 0 1 Trigger Timer High
0010 Reserved
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1 0 0 0 Trigger Timer Control
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
A Trigger Timer is configured by first loading the Trigger Timer High Register and Trigger
Timer Low Register. The Trigger Timer Low Register is used in conjunction with the Trigger
Timer High Register for establishing the timer interval. This 32-bit counter is programmable
from 2 microseconds to 429 seconds in 100 nanosecond increments. The data value loaded into
the combination of the Trigger Timer Low and High Registers is the number of 100 nanosecond
increments between trigger assertions. For example, to obtain an interval of 1 millisecond, the
32-bit timer must be loaded with data set to 10000 (271016). Therefore, the Trigger Timer High
Register is loaded with 0 and the Trigger Timer Low Register is loaded with 10000 (271016).
The following diagram shows the bit pattern for the Trigger Timer High Register. 34h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write-Only TMR
31
TMR
30
TMR
29
TMR
28
TMR
27
TMR
26
TMR
25
TMR
24
TMR
23
TMR
22
TMR
21
TMR
20
TMR
19
TMR
18
TMR
17
TMR
16
Bit(s) Mnemonic Meaning
15:0 TMR31:16 TIMER DATA 31 through 16 are write-only bits used to establish the
interval at which trigger signals are asserted. This register is used in
combination with the Trigger Timer Low Register to determine the
number of 100 nanosecond increments between trigger assertion.

Model V15X-AA11
20
The following diagram shows the bit pattern for the Trigger Timer Low Register. 34h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Write-Only TMR
15
TMR
14
TMR
13
TMR
12
TMR
11
TMR
10
TMR
9
TMR
8
TMR
7
TMR
6
TMR
5
TMR
4
TMR
3
TMR
2
TMR
1
TMR
0
Bit(s) Mnemonic Meaning
15:0 TMR15:0 TIMER DATA 15 through 0 are write-only bits used to establish the
interval at which trigger signals are asserted. This register is used in
combination with the Trigger Timer High Register to determine the
number of 100 nanoseconds increments between trigger assertion.
The Trigger Timer Control Register contains an enable bit that allows the timer to operate.
This register also contains the 10 trigger source bits which determine the trigger signals to
assert once the timer expires. Any trigger signal bit set to a one in this register is asserted
once the timer expires. The following diagram shows the bit layout for the Trigger Timer
Register.
34h
151413129876543210
Write-Only TMR
ENA Not Used ECL TG1
ECL
TG0
TTL
TG7
TTL
TG6
TTL
TG5
TTL
TG4
TTL
TG3
TTL
TG2
TTL
TG1
TTL
TG0
Bit(s) Mnemonic Meaning
15 TMR ENA TIMER ENABLE is a write-only bit used to enable and disable the timer
from operating. Setting this bit to a one enables the timer and a zero
disables the timer.
14:12 Not Used These bits are not used and may be written with any data pattern.
9:8 ECL TG1:0 VXI ECL TRIGGER1 and 0 are write-only bits used to enable the
assertion of the corresponding VXI ECL Trigger signal once the timer
expires. A zero in a bit location prevents the signal from being asserted
once the timer expires.
7:0 TTL TG7:0 VXI TTL TRIGGER7 through 0 are write-only bits used to enable the
assertion of the corresponding VXI TTL Trigger signal once the timer
expires. A zero in a bit location prevents the signal from being asserted
once the timer expires.
SBC Slave Mode Enable Register