Remarks:
(1) Unit: CLK=1/fCLK, it is the duration for scanning a pixel; H=th, it is the duration for
scanning a line;
(2) It is necessary to keep tvp+tvb=12 and thp+thb=43 in sync mode. DE mode is
unnecessary to keep it.
From the figure above, we can learn that:
The total time for scanning a line is: th = thp + thb + thd + thf; in the period of thd, when a
clock plus comes, a pixel data will be transmitted via the parallel data interface. And there
are 480 pixels each line for this LCD, so thd=480;
The duration for scanning a frame is: tv = tvp + tvb + tvd + tvf;Hsync can be regarded as
the clock of vertical signals. A clock cycle of Hsync refers to the duration for LCD
displaying a line. When a falling edge comes in Hsync, a new line will be displayed in the
LCD. However, the actual data transmission only occurs in the period of tvd. And the LCD
will display the new line in this case.There are 272 lines for this LCD, so tvd = 272.
Other parameters can be modified as required, according to the specificationslisted in the
tables above.
2. Hardware description