XIAMEN OCULAR GDM12864A User manual
User’s Guide
GDM12864A
™
LCM
(Liquid Crystal Display Module)
XIAMEN OCULAR LCD DEVICES CO., LTD.
??????????????
South 5F., Guang Xia Bldg. Torch Hi-tech
Develop. Area, Xiamen, China 361006
Tel: (0592)6026045 Fax: (0592)6026021
GDM12864A LCM Use’s Guide
Contents
Chapter 1. Introduction to ITM-12864A LCM
1
Features 1
Mechanical Specifications 1
Temperature Characteristics 1
External Dimensions 2
Application Diagram 3
Electro-Optical characteristics 4
Interface Pin Connections 5
Electrical Absolute Maximum Rating (KS0107B) 6
DC Electrical Characteristics (KS0107B) 6
Electrical Absolute Maximum Rating (KS0108B) 7
DC Electrical Characteristics (KS0108B) 7
Chapter 2. Driver IC (KS0107B) Function Description 8
Introduction 8
AC Characteristics 9
Master Mode 9
Slave Mode 10
Functional Description 11
RC Oscillator 11
Timing Generation Circuit 11
Data Shift & Phase Select Control 12
Chapter 3. Driver IC (KS0108B) Function Description 13
Introduction 13
AC Characteristics 13
Operating Principles & Methods 16
Display Control Instruction 19
Chapter 1 Introduction to GDM12864A LCM 1
CHAPTER 1
Introduction to ITM-12864A LCM
ITM-12864A is a dot matrix graphic LCD module which is fabricated by low power COMS
technology. It can display 128*64 dots size LCD panel using a 128*64 bit-mapped Display Data
RAM (DDRAM). It interfaces with an 8-bit microprocessor.
Features
?? Display format: 128*64 dots matrix graphic
?? STN yellow-green mode
?? Easy interface with 8-bit MPU
?? Low power consumption
?? LED back-light
?? Viewing angle: 6 O’clock
?? Driving method : 1/64 duty , 1/6.7 bias
?? LCD driver IC: KS0108B(2 ?)?KS0107B
?? Connector: Zebra
Mechanical Specifications
Item Dimension Unit
Module Size(W*H*T) 93.0*70.0*10.0 mm
Viewing Area(W*H) 72.0*40.0 mm
Number of Dots 128.0*64.0 PCS
Dot Size(W*H) 0.48*0.48 mm
Dot Pitch(W*H) 0.52*0.52 mm
Module Size With B/L 93.0*70.0*15.0 mm
Temperature Characteristics
Parameter Symbol Rating Unit
Operating temperature Topr 0 ~ +50 ?
Storage temperature Tstg -20 ~ +70 ?
Chapter 1 Introduction to GDM12864A LCM 2
Figure 1. External Dimensions
PIN 1 2 3 4 5 6 7 8 9 10
SIGNAL Vss VDD
V0 D/I R/W
E DB0
DB1
DB2
DB3
PIN 11 12 13 14 15 16 17 18 19 20
SIGNAL DB4
DB5
DB6
DB7
CS1
CS2
RES
VEE
A K
*NOTE: 1.All units are mm.
2.Tolerances unless otherwise specified ?0.2.
INTECH LCD MODULE ITM-12864A
Chapter 1 Introduction to GDM12864A LCM 3
Figure 2. Application Diagram
CS2B
DB[0:7]
RESETB
CS1B
S64
S1
CS3
RS
E
RW
12
V3
KS0108B
(Bottom view)
VSS
VSS
VEE
V4
V5
CLK1
CL2
CLK2
M
FRM
V0
V1
V2
VDD
ADC
VEE
SEG64
DB[0:7]
RESETB
CS1B
CS3
CS2B
RESETB
DB[0:7]
CS2
CS1
E
RW
RS
12
RS
RW
E
SEG1 .... C1C64 CCRR
ADC
VEE
VSS
V3
MPU
VSS
V5
V4
V0
V2
V1
VDD
S1 S64
KS0108B
(Bottom view) CLK2
CL2
FRM
CLK1
M
VSS
V4
V3
V5
V1
V0
V2
VEE
V4
V5
V2
V3
VDD
V0
V1
FS
DS1
VSS
DS2
MS
PCLK2
VDD
SHL
CL2
CLK2
CLK1
FRM
M
KS0107B
SEG128
LCD panel
(128X64)
SEG65 ....
. .
COM64
COM1
*Note
1/64 duty, 1/6.7 bias
VDD>V1>V2>V3>V4>V5>VEE
Chapter 1 Introduction to GDM12864A LCM 4
Electro-Optical characteristics
TN Type (Twisted Nematic )
Item Symbol Min. Typ. Max. Unit Condition Note
?2 -?1
Viewing Angle f40 --deg. Cr = 2.0 1,2
Contrast Ratio Cr -4--?=20?
f= 0?3
Response Time (rise) tR-110 -ms ?=20?
f= 0?4
Response Time (fall) tF-110 -ms ?=20?
f= 0?4
STN Type (Super Twisted Nematic )
Item Symbol Min. Typ. Max. Unit Condition Note
?2 -?1
Viewing Angle f70
-90 -+90 deg. Cr = 2.0 1,2
Contrast Ratio Cr -4--?=20?
f= 0?3
Response Time (rise) tR-110 -ms ?=20?
f= 0?4
Response Time (fall) tF-110 -ms ?=20?
f= 0?4
4.Definitionofopticalresponse
3.DefinitionofcontrastCr
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tF
tR
Time
Driving Voltage
SetPoint
Cr=(A/B)pNegative:P=-1
Positive:P=+1
Non-
Selected
Dots
Dots
selected
Chapter 1 Introduction to GDM12864A LCM 5
Interface Pin Connections
Pin
No. Symbol I/O Type
Description
1VSS Supply Ground
2VDD Supply Power supply
3V0 Supply LCD driver supply voltage
4D/I Data input/output pin of internal shift register
MS SHL DIO1 DIO2
H H Output Output
H L Output Output
L H Input Output
L L Output Input
5R/W Read or Write
RW Description
H Data appears at DB[7:0] and can be read by the CPU while
E= H CS1B=L,CS2B=L and CS3=H.
L Display data DB[7:0] can be written at falling edge of E
when CS1B=L, CS2B=L and CS3=H.
6EEnable signal
E Description
H Read data in DB[7:0] appears while E= “High”.
L Display data DB[7:0] is latched at falling edge of E.
7DB0
8DB1
9DB2
10 DB3
11 DB4
12 DB5
13 DB6
14 DB7
I/O Data bus [0~7]
Bi-directional data bus
15
16 CS1
CS2 IChip selection
When CS1=H,CS2=L, select IC1
When CS1=L,CS2=H, select IC2
17 RESETB IReset signal.
When RSTB=L
?1?ON/OFF register becomes set by 0.(display off)
?2?display start line register becomes set by 0 (Z-address 0 set, display
from line 0)
?3?After releasing reset , this condition can be changed only by
instruction.
18 VEE Power VEE is connected by the same voltage.
19 ABack-light anode
20 KBack-light cathode
Chapter 1 Introduction to GDM12864A LCM 6
Electrical Absolute Maximum Ratings (KS0107B)
Parameter Symbol Rating Unit Note
Operating voltage VDD -0.3 ~ +7.0 V*1
Supply voltage VEE VDD-19.0 ~ VDD+0.3V*4
VB-0.3 ~ VDD+0.3 V*1,2Driver supply voltage VLCD VEE-0.3 ~ VDD+0.3 V*3,4
*Notes:
*1. Based on VSS = 0V
*2. Applies to input terminals and I/O terminals at high impedance. (Except V0L, V1L, V4L, and
V5L)
*3. Applies to V0L, V1L, V4L, and V5L.
*4. Voltage level: VDD=V0=V1=V2=V3=V4=V5=VEE
DC Electrical Characteristics(KS0107B)
(VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85?)
Item Symbo
lCondition Min. Typ. Max. Unit Note
Operating voltage VDD -4.5 -5.5 V
VIH -0.7VDD -VDD *1Input voltage VIL -VSS -0.3VD
D
VOH IOH= -0.4mA VDD-0.4 --*2output voltage VOL IOL= 0.4mA --0.4
Input leakage current
ILKG VIN= VDD ~ VSS -1.0 -+1.0 ?A*1
OSC Frequency fosc Rf=47kO±2%
Cf=20pF±5% 315 450 585 kHz
On Resistance
(Vdiv-Ci) RONS VDD-VEE=17V
Load current±150?A--1.5 kO
IDD1 Master mode
1/128 Duty --1.0 mA *3Operating current
IDD2 Master mode
1/128 Duty --0.2 *4
Supply Current IEE Master mode
1/128 Duty --0.1 *5
Operating
fop1
Master mode
External Duty 50
-
600
kHz
Frequency fop2 Slave mode 0.5 -1500
Notes
*1. Applies to input terminals FS, DS1, DS2, CR, SHL, MS and PCLK2 and I/O terminals DIO1,
DIO2, M , and CL2 in the input state.
*2. Applies to output terminals CLK1, CLK2 and FRM and I/O terminals DIO1, DIO2, M , and
CL2 in the output state.
*3. This value is specified about current flowing through VSS.
Internal oscillation circuit: Rf=47kO, cf=20pF
Each terminals of DS1, DS2, FS, SHL, and MS is connected to VDD and out is no load.
*4. This value is specified about current flowing through VSS.
Each terminals is DS1, DS2, FS, SHL, PCLK2 and CR is connected to VDD,MS is connected to VSS
and CL2, M, DIO1 is external clock.
*5. This value is specified about current flowing through VEE, Don’t connect to VLCD (V1~V5).
Chapter 1 Introduction to GDM12864A LCM 7
Electrical Absolute Maximum Ratings(KS0108B)
Parameter Symbol Rating Unit Note
Operating voltage VDD -0.3 ~ +7.0 V*1
Supply voltage VEE VDD-19.0 ~ VDD+0.3 V*4
VB-0.3 ~ VDD+0.3 V*1,3Driver supply voltage VLCD VEE-0.3 ~ VDD+0.3 V*2
*Notes:
*1. Based on VSS = 0V
*2. Applies the same supply voltage to VEE. VLCD=VDD-VEE.
*3. Applies to M, FRM, CLK1,CLK2, CL, RESETB, ADC, CS1B, CS2B,CS3, E, R/W, RS and
DB0~DB7.
*4. Applies V0L,V2L,V3L and V5L.
Voltage level: VDD=V0=V1=V2=V3=V4=V5=VEE
DC Electrical Characteristics(KS0108B)
(VDD= 4.5 to 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= -30 to +85?)
Item Symbol Condition Min. Typ. Max. Unit Note
Operating voltage VDD -4.5 -5.5 V
VIH1 -0.7VDD -VDD *1Input High voltage VIH2 -2.0 -VDD *2
VIL1 -0-0.3VD
D*1Input Low voltage
VIL2 -0-0.8 *2
Output High Voltage VOH IOH= -0.2mA 2.4 --*3
Output Low Voltage VOL IOL= 1.6mA --0.4 *3
Input leakage current ILKG VIN= VSS ~ VDD -1.0 -+1.0 ?A*4
Three-state (OFF)
Input Current ITSL VIN= VSS ~ VDD -5.0 -5.0 *5
Driver Input leakage
current IDIL VIN= VEE ~ VDD -2.0 2.0 *6
On Resistance
(Vdiv-Ci) RONS VDD-VEE=15V
Load current±100?A--7.5 kO*8
IDD1 During Display --0.1 mA *7Operating current IDD2 During Access
Access Cycle=1MHz --0.5 *7
Notes
*1. CL, FRM, M, RSTB, CLK1, CLK2
*2. CS1B, CS2B, CS3, E, R/W, RS, DB0~DB7
*3. DB0~DB7
*4. Except DB0~DB7
*5. DB0~DB7 at high impedance
*6. V0, V1, V3, V3, V4, V5
*7. 1/64 duty , FCLK=250KHZ, Frame Frequency=70HKZ, Output: No Load
*8. VDD-VEE=15.5V
V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L
64CH Common Driver For Dot Matrix LCD 8
©1998 Intech LCD Group Ltd.
CHAPTER 2
Driver IC Function Description
KS0107 Driver IC
64COM graphic driver for dot matrix LCD
Introduction
The KS0107B is an :CD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic
display systems.
This device provides 64 shift registers and 64 output drivers.
It generates the timing signal to control the KS0108B (64 channel segment drover.).
The KS0107B is fabricated by low power CMOS high voltage process technology, and is composed
of the liquid crystal display system in combination with the KS0108B (64 channel segment drover.).
64CH Common Driver For Dot Matrix LCD 9
©1998 Intech LCD Group Ltd.
AC Characteristics (VDD=4.5~5.5V, Ta=-30?~+85?)
1. Master mode (MS=VDD, PCLK2=VDD, Cf=20pF, Rf=47KO)
tWHC
tWHC
t
W
L
C
t
SU
t
DH
t
S
U
t
D
t
D
t
DM
t
D
2
1
t
D
1
2
t
W
H
2
t
W
H
1
t
WL1
t
R
t
F
t
R
t
F
t
D
M
t
D
F
CL2
DIO1(SHL=VDD)
D
I
O
2
(
S
H
L
=
V
S
S
)
DIO2(SHL=VDD)
D
I
O
1
(
S
H
L
=
V
S
S
)
FRM
M
CLK1
CLK2
0.7VDD
0.7VDD
0.3VDD
0.3VDD
Characteristic Symbol Min Typ Max Unit
Data Setup Time tSU 20 --
Data Hold Time tDH 40 --
Data Delay Time tD5--
FRM Delay Time tDF -2-2
M Delay Time tDM -2-2
CL2 Low Level Width tWLC 35 --
CL2 High Level Width tWHC 35 --
?s
CLK1 Low Level Width tWL1 700 --
CLK2 Low Level Width tWL2 700 --
CLK1 High Level Width tWH1 2100 --
CLK2 High Level Width tWH2 2100 --
CLK1-CLK2 Phase Difference tD12 700 --
CLK2-CLK1 Phase Difference tD21 700 --
CLK1,CLK2 Rise/Fall Time tR/tF --150
ns
64CH Common Driver For Dot Matrix LCD 10
©1998 Intech LCD Group Ltd.
Slave mode (MS=VSS)
CL2
(PLK2=VSS)
CL2
(PLK2=VDD)
DIO1(SHL=VDD)
DIO2(SHL=VSS)
I
n
p
u
t
D
a
t
a
DIO1(SHL=VDD)
DIO2(SHL=VSS)
OutputData
t
W
L
C
2
t
W
L
C
t
W
H
C
1
0.3V
D
D
0.7V
D
D
t
W
L
C
1
t
F
t
R
t
S
U
t
R
t
F
t
D
t
H
C
L
0.7V
D
D
0.3V
D
D
0.3V
D
D
0.7V
D
D
t
H
Characteristics Symbol Min Typ Max Unit Note
CL2 Low Level Width tWLC1 450 --PCLK2=VSS
CL2 High Level Width tWHC1 150 --PCLK2=VSS
CL2 Low Level Width tWLC2 150 --PCLK2=VDD
CL2 High Level Width tWHL 450 --PCLK2=VDD
Data Setup Time tSU 100 --
Data Hold Time tDH 100 --
Data Delay Time tD--200 *1
Output Data Hold Time tH10 --
CL2 Rise/Fall Time tR/tF--30
ns
*1: Connect load CL=30pF
30pF
OUTPUT
64CH Common Driver For Dot Matrix LCD 11
©1998 Intech LCD Group Ltd.
FUNCTIONAL DESCRIPTION
1.RC Oscillator
The RC Oscillator generates CL2, M, FRM, of the KS0107B and CLK1, CLK2 of the KS0107B by the
oscillation resister R and capacitor C.
When selecting the master/slave, oscillation circuit is as following:
1) Master Mode
KS0107B
KS0107B
RR CRCR CC
R
f
C
f
openopenExternalclock
2) Slave Mode
KS0107B
RCR C
open
openVDD
2.Timing Generation circuit
It generates CL2, M, FRM, CLK1, and CLK2 by the frequency from oscillation circuit.
1) Selection of Master/Slave (M/S)
When M/S is “H”, it generates CL2, M, FRM, CLK1, and CLK2 internally. When M/S is “L”,
it operates by receiving M, CLK2 from master device.
2) Frequency Selection (FS)
To adjust FRM by 70Hz, the oscillation frequency should be as following:
FS Oscillation Frequency
HfOSC=430KHz
LfOSC=215KHz
In the slave mode, it is connected to VDD.
64CH Common Driver For Dot Matrix LCD 12
©1998 Intech LCD Group Ltd.
3) Duty Selection (DS1, DS2)
It provides various duty selection according to DS1, DS2.
DS1 DS2 DUTY
L1/48LH1/64
L1/96HH1/128
3. Data shift & Phase Select Control
1) Phase Selection
It is a circuit to shift data on synchronization or rising edge or falling edge of the CL2 according
to PCLK2.
PCLK2 Phase Selection
HData shift on rising edge of CL2
LData shift on falling edge of CL2
2) Data shift Direction Selection
When M/S is connected to VDD, DIO1 and DIO2 terminal is only output.
When M/S is connected to VSS, it depends on the SHL.
MS SHL DIO1 DIO2 Direction of Data
HOutput Output C1~C64HLOutput Output C64~C1
HInput Output DIO1~C1~C64~DIO2LLOutput Input DIO2~C64~C1~DIO1
64CH Segment Driver For Dot Matrix LCD 13
©1998 Intech LCD Group Ltd.
CHAPTER 3
Driver IC Function Description
KS0108 Driver IC
64 SEG graphic driver for dot matrix LCD
Introduction
The KS0108B is an LCD driver LSI with 64 channel outputs for dot matrix liquid crystal graphic
display systems. This device consists of the display RAM, 64 bit data latch 64 bit drivers and decoder
logics. It has the internal display RAM for storing the display data transferred from a 8 bit micro
controller and generates the dot matrix liquid crystal driving signals corresponding to stored data. The
KS0108B composed of the liquid crystal display system in combination with the KS0107B(64
common driver).
AC Characteristics (VDD=4.5~5.5V ,VSS=0V, Ta=-30?~+85?)
(1)Clock Timing
Characteristic
Symbol
Min
Typ
Max
Unit
CLK1, CLK2 Cycle Time
t
CY
2.5
-
20
?
s
CLK1
‘
LOW
’
Level Width
t
WL1
625
-
-
CLK2
‘
LOW
’
Level Width
t
WL2
625
-
-
CLK1
‘
HIGH
’
Level Width
t
WH1
1875
-
-
CLK2
‘
HIGH
’
Level Width
t
WH2
1875
-
-
CLK1
-
C
LK2 Phase Difference
t
D12
625
-
-
CLK2
-
CLK1 Phase Difference
t
D21
625
-
-
CLK1, CLK2 Rise Time
t
R
-
-
150
CLK1, CLK2 Fall Time t
F
--150
ns
64CH Segment Driver For Dot Matrix LCD 14
©1998 Intech LCD Group Ltd.
tFtF
tWL2
tCY
tWH2
tD21
tD12
tWL1
tR
tF
tWH1
tCY
CLK1
CLK2
0.3VDD
0.7VDD
0.7VDD
0.3VDD
(2).Display Control Timing
Characteristic
Symbol
Min
Typ
Max
Unit
FRM Delay Time
t
DF
-
2
-
2
M Delay Time
t
DM
-
2
-
2
CL
‘
LOW
’
Level Width
t
WL
35
-
-
CL
‘
HIGH
’
Level Width
t
WH
35 --
us
tWL
tWH
tDFtDF
tDM
0.7V
D
D
0.3V
D
D
0.3VDD
0.7VDD
0.3VDD
0.7V
D
D
M
FRM
CL
64CH Segment Driver For Dot Matrix LCD 15
©1998 Intech LCD Group Ltd.
(3). MPU Interface
Characteristic
Symbol
Min
Typ
Max
Unit
E Cycle
t
C
1000
-
-
E High Level Width
t
WH
450
-
-
E L
ow Level Width
t
WL
450
-
-
E Rise Time
t
R
-
-
25
E Fall Time
t
F
-
-
25
Address Set
-
Up Time
t
ASU
140
-
-
Address Hold Time
t
AH
10
-
-
Data Set
-
Up Time
t
SU
200
-
-
Data Delay Time
t
D
-
-
320
Data Hold Time (Write)
t
DHW
10
-
-
Data Hold Time (Read) t
DHR
20 --
ns
tDSUtDHW
tASU
tASU
tAH
tAH
tRtF
tWL
tWH
tC
DB0~DB7
CS1B,CS2B
CS3,RS
R/W
E
MPUWritetiming
64CH Segment Driver For Dot Matrix LCD 16
©1998 Intech LCD Group Ltd.
tWL
tC
tF
tR
tAH
tAHtASU
tASU
tWH
tD
tWH
MPUReadtiming
DB0~DB7
CS1B,CS2B
CS3,RS
R/W
E
OPERATING PRINCIPLES & METHODS
1. I/O Buffer
Input buffer controls the status between the enable and disable of chip. Unless the CS1B to CS3 is in
active mode, Input or output of data and instruction does not execute. Therefore internal state is not
change. But RSTB and ADC can operate regardless CS!B-CS3.
2. Input register
Input register is provided to interface with MPU which is different operating frequency. Input register
stores the data temporarily before writing it into display RAM.
When CS1B to CS3 are in the active mode, R/W and RS select the input register. The data from MPU
is written into input register. Then writing it into display RAM. Data latched for falling of the E signal
and write automatically into the display data RAM by internal operation.
3. Output register
Output register stores the data temporarily from display data RAM when CS1B, CS2B and CS3 are in
active mode and R/W and RS=H, stored data in display data RAM is latched in output register. When
CS1B to CS3 is in active mode and R/W=H , RS=L, status data (busy check) can read out.
To read the contents of display data RAM, twice access of read instruction is needed. In first access,
data in display data RAM is latched into output register. In second access, MPU can read data which is
latched. That is to read the data in display data RAM, it needs dummy read. But status read is not
needed dummy read.
64CH Segment Driver For Dot Matrix LCD 17
©1998 Intech LCD Group Ltd.
RS R/W Function
LInstructionLHStatus read (busy check)
LData write (from input register to display data RAM )HHData read (from display data RAM to output register)
4. Reset
The system can be initialized by setting RSTB terminal at low level when turning power on, receiving
instruction from MPU. When RSTB becomes low, following procedure is occurred.
1. Display off
2. Display start line register become set by 0.(Z-address 0)
While RSTB is low, No instruction except status read can by accepted. Therefore, execute other
instructions after making sure that DB4= (clear RSTB) and DB7=0 (ready) by status read instruction.
The conditions of power supply at initial power up are shown in table 1.
Table 1. Power Supply Initial Conditions
Item Symbol Min Typ Max Unit
Reset Time tRS 1.0 --us
Rise Time tR--200 ns
0.3VDD
0.7VDD
VDD
RSTB
tR
tRS
4.5[V]
5. Busy flag
Busy flag indicates that KS0108B is operating or no operating. When busy flag is high, KS0108B is in
internal operating .
When busy flag is low, KS0108B can accept the data or instruction.
DB7indicates busy flag of the KS0108B.
BusyFlag
E
TBusy
fCLKisCLK1,CLK2Frequency
1/fCLK<TBusy<3/fCLK
64CH Segment Driver For Dot Matrix LCD 18
©1998 Intech LCD Group Ltd.
6. Display On/Off Flip-Flop
The display on/off flip-flop makes on/off the liquid crystal display. When flip-flop is reset (logical low),
selective voltage or non selective voltage appears on segment output terminals. When flip-flop is set
(logic high), non selective voltage appears on segment output terminals regardless of display RAM data.
The display on/off flip-flop can changes status by instruction. The display data at all segment disappear
while RSTB is low.
The status of the flip-flop is output to DB5 by status read instruction.
The display on/off flip-flop synchronized by CL signal.
7. X Page Register
X page register designates pages of the internal display data RAM.
Count function is not available. An address is set by instruction.
8. Y address counter
Y address counter designates address of the internal display data RAM. An address is set by instruction
and is increased by 1 automatically by read or write operations of display data.
9. Display Data RAM
Display data RAM stores a display data for liquid crystal display. To indicate on state dot matrix of
liquid crystal display , write datra1. The other way , off state, writes 0.
Display data RAM address and segment output can be controlled by ADC signal.
ADC=H => Y-address 0: S1~Y address 63: S64
ADC=L => Y-address 0: S64~Yaddress 63: S1
ADC terminal connect the VDD or VSS.
10. Display Start Line Register
The display start line register indicates of display data RAM to display top line of liquid crystal display.
Bit data (DB<0.5>) of the display start line set instruction is latched in display start line register.
Latched data is transferred to the Z address counter while FRM is high, presetting the Z address
counter.
It is used for scrolling of the liquid crystal display screen.
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