Xilinx Virtex-6 FPGA User manual

Virtex-6 FPGA
Connectivity Kit
Getting Started Guide
UG664 (v1.4) July 6, 2011
XPN 0402826-03

Virtex-6 FPGA Connectivity Kit Getting Started www.xilinx.com UG664 (v1.4) July 6, 2011
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Revision History
The following table shows the revision history for this document.
Date Version Revision
02/26/10 1.0 Initial Xilinx release.
06/11/10 1.1 Removed references to specific release numbers for the ISE Design Suite, where
applicable. Replaced Figure 1, Figure 22, Figure 23, Figure 24, Figure 25, Figure 26, and
Figure 27.
Removed update DVD from Connectivity Kit Contents. Added “in loopback mode” to
step b, page 31. Removed DDR3 from Raw Data Path bullet in step 2a on page 33. In
step 2b on page 33, changed the minimum value of the range from 128 to 64 for the XAUI
and Raw Data paths and changed the Raw Data path option to one Packet Size instead
of a minimum and a maximum. In step 2c on page 35, indicated to click Start test.
Added the note under Figure 26. Replaced the “ISE 11.1 Software Installation” and
“ISE 11.4 Software Update Installation” sections with a link to the Installation, Licensing,
and Release Notes document. In step 8, page 40, removed the ISE Design Suite release
number from the path. In Modifying the Virtex-6 FPGA Targeted Reference Design,
added the note on page 42. Changed the command in step 4c on page 42. Changed the
names of the BIT and MCS files in step 5d on page 43. Removed “double-click” from the
Windows based script in step 8c on page 44. Removed sentence about the command
shell opening from step 8d on page 44. Added the Next Steps section.
08/10/10 1.2 In step 4c on page 42, changed the filename to mig3_5.xco from mig3_4.xco. In
Table 2, changed the implementation software tool entry to ISE Design Suite.
10/05/10 1.3 Added information for AXI4 protocol.
07/06/11 1.4 Removed descriptions of Virtex-6 FPGA Connectivity TRD being available in non-AXI4
protocol version throughout. Replaced v6_trd_quickstart with v6_trd_lin_quickstart.
Added Windows platform to Board and Connectivity Targeted Reference Design
Features. Updated step 6c on page 14. Added Install Windows Driver. Updated
Figure 21. Added Install Linux Driver heading before step 12 on page 27.

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07/06/11 1.4
(Cont’d)
Updated step 1 on page page 33. Removed Figure 25: Launch the Performance Monitor
and Status GUI, and Figure 26: Run v6_trd_quickstart. Corrected coregen command in
step 4c on page 42. Updated ending step instruction from step 8 to step 6 in Test Setup.
Added Windows Driver. Added Linux Driver heading before step 1 on page 56.
Updated step 2a and step 3a on page 56. Updated Table 1. Updated Figure 52 Figure 54,
and Figure 61.
Date Version Revision

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Virtex-6 FPGA Connectivity Kit
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Connectivity Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
What is Inside the Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
What is Available Online . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Getting Started with the Connectivity Targeted Reference Design Demo. . . . . 10
Board and Connectivity Targeted Reference Design Features . . . . . . . . . . . . . . . . . . . 10
Hardware Demonstration Setup Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Install Windows Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Install Linux Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Evaluating the Virtex-6 FPGA Connectivity TRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Installation and Licensing of ISE Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Downloading and Installing Tool Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Modifying the Virtex-6 FPGA Targeted Reference Design . . . . . . . . . . . . . . . . . . . 42
Hardware Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Software Modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Windows Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Linux Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Next Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Connectivity TRD Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
PCI Express. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Packet DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Multiport Virtual FIFO and Memory Controller Block. . . . . . . . . . . . . . . . . . . . . . . . . . 60
XAUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Software Device Driver and Software Application/GUI Files and Scripts . . . . . . . . . . . 62
Simulating the Connectivity TRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Reusing the DMA IP from Northwest Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Modifications to the Connectivity TRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Getting Started with the Virtex-6 FPGA IBERT Reference Design . . . . . . . . . . . . 64
IBERT Hardware Demonstration Setup Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Reference Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Installation is Complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Warranty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table of Contents

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Preface
About This Guide
This Getting Started Guide describes the contents of the Virtex®-6 FPGA Connectivity Kit
and provides instructions on how to start developing connectivity systems using
Virtex-6 FPGAs.
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/support/documentation/index.htm.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
Use this site for technical support regarding the installation and use of the product license
file.
Additional Support
For questions regarding products within your Product Entitlement Account or if the email
notification was received in error, send an email message to your regional Customer
Service Representative:
• Canada, USA, and South America: [email protected]
• Europe, Middle East, and Africa: eucase[email protected]
• Asia Pacific including Japan: [email protected]

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Preface: About This Guide

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Virtex-6 FPGA Connectivity Kit
Introduction
The Virtex®-6 FPGA Connectivity Kit provides a comprehensive, high-performance
Connectivity Development and Demonstration platform using the Virtex-6 family for
high-bandwidth and high-performance applications in multiple market segments. The kit
enables designing with common serial standards, such as PCI Express®, XAUI, and
proprietary serial standards through the SMA interface.
Note: The screen captures in this document are conceptual representatives of their subjects and
provide general information only. For the latest information, see the Xilinx® ISE® Design Suite.
Connectivity Kit Contents
This section describes the kit deliverables provided in the box and indicates what can be
found on the Xilinx website.
What is Inside the Box
The kit consists of these elements:
• Virtex-6 LX240T FPGA-based ML605 Evaluation Board with:
• One FMC Connectivity daughter card
• One CX4 loopback module
• Universal 12V power supply
• Two USB A/Mini-B cables (used for download and debug)
• One CompactFlash card (2 GB)
• One DVI-to-VGA adapter
• One Ethernet Cat5 cable
• Four SMA cables
• One SATA cable and one SATA loopback cable
• Xilinx ISE Design Suite DVD, including:
• ISE Foundation™ software with ISE Simulator
• PlanAhead™ Design and Analysis Tool
• Embedded Development Kit (EDK)
• Xilinx Platform Studio (XPS)
• Software Development Kit (SDK)
• ChipScope™ Pro Tool

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Getting Started with the Connectivity Targeted Reference Design Demo
• One USB stick containing reference designs, documentation, and demos
• Operating System: Fedora 10 LiveCD
• Virtex-6 FPGA Connectivity Kit documentation:
• Welcome letter
• Hardware setup guide
• This Getting Started Guide
What is Available Online
Refer to the Xilinx website for this information:
• License for ISE Design Suite: Embedded Edition
•http://www.xilinx.com/getproduct
•http://www.xilinx.com/tools/faq.htm
• Connectivity Kit home page with documentation and reference designs:
http://www.xilinx.com/v6connkit
This home page provides information on:
• USB stick contents (the current version of the data on the USB stick is available
here)
• Schematics, Gerber, and board bill of materials (BOM)
• Additional detailed documentation
• Technical Support
http://www.xilinx.com/support
Getting Started with the Connectivity Targeted Reference Design
Demo
The Virtex-6 FPGA Connectivity Kit comes with a pre-built demonstration of the
Virtex-6 FPGA Connectivity Targeted Reference Design (TRD) available on Platform Flash.
The demo can be run before any additional tools are installed for an overview of the
features of the ML605 Evaluation Board using a connectivity targeted reference design in
the Virtex-6 LX240T FPGA.
Board and Connectivity Targeted Reference Design Features
The Virtex-6 FPGA Connectivity TRD (see Figure 1) demonstrates the main integrated
components in a Virtex-6 FPGA. The Integrated Endpoint Block for PCI Express and GTX
transceivers work together in an application with additional IP cores, such as a Northwest
Logic Packet DMA engine for the PCI Express interface, XAUI LogiCORE™ IP, and
Memory controller IP generated using the Memory Interface Generator (MIG).

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Getting Started with the Connectivity Targeted Reference Design Demo
The Virtex-6 FPGA Connectivity TRD features these components:
• Virtex-6 FPGA Integrated Block for PCI Express core configured as a
4-lane at 5 Gb/s or 8-lane at 2.5 Gb/s Endpoint for PCI Express, v2.0
• A performance monitor tracks the PCIe® data bandwidth by measuring data bus
utilization on:
• AXI4-Stream interface
• Packet DMA for PCI Express from Northwest Logic, a multichannel DMA that:
• Supports full-duplex operation with independent transmit and receive paths
• Provides a packetized interface on the backend similar to LocalLink
• Monitors data transfers in the receive and transmit directions
• Provides a control plane interface to access user-defined registers
• Multiport Virtual FIFO
• The Memory Interface Controller is delivered through the Virtex-6 FPGA Memory
Interface Generator (MIG) tool.
• The virtual FIFO is a highly efficient layer around the native interface of the
Virtex-6 FPGA Memory Controller and an external DDR3 memory device.
• XAUI LogiCORE IP that utilizes serial I/O transceivers to provide a throughput of up
to 10 Gb/s
XAUI TX and XAUI RX blocks align data as per the XGMII format.
• Control logic to interface between the DMA and the multiport Virtual FIFO.
X-Ref Target - Figure 1
Figure 1: Block Diagram of the Virtex-6 FPGA Targeted Reference Design
Packet
DMA
Software Hardware
C2SS2C C2SS2C
x4 PCIe Link @ 5.0 Gb/sor
x8PCIe Link @ 2.5 Gb/s
Third Party IP FPGA Logic
64-bit AXI4-Stream Interface @ 250 MHz
Register
Interface
Performance
Monitor
User Space
Registers
Packet
Control
with CRC
S2C_Ctrl
S2C_Data
64
GTX Transceivers
x4 @ 5 Gb/s/ x8@ 2.5 Gb/s
Integrated Block for PCI Express, v2.0
Wrapper for PCI Express
Base DMA Driver
Raw DataDriver XAUI Driver
GUI
Xilinx IPIntegrated Blocks
Native
Interface
of DDR3
Memory
Controller
Multiport
Virtual
FIFO
UG664_01_092810
Control
WR_Data
64
C2S_Ctrl
C2S_Data
64
XGMII
TX
XAUI
GTX Transceivers
Control
RD_Data
64
Control
Data
64
XGMII
RX
Control
WR_Data
64
Control
Data
64
@400 MHz
@200 MHz
@250 MHz
@156.25 MHz@250 MHz@250 MHz
@250 MHz@250 MHz
@156.25 MHz
DDR3
64
Control
RD_Data
64
Control
Control
S2C_Ctrl
S2C_Data
64
Control
WR_Data
64
C2S_Ctrl
C2S_Data
64
Raw Data
Loopback
Control
RD_Data
64
Control
WR_Data
64
256
256
Control
RD_Data
64
Packet
Control
with CRC
Generator
Checker

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Getting Started with the Connectivity Targeted Reference Design Demo
• Software driver for 32-bit Windows and 32-bit Linux platforms:
• Configures the hardware design parameters
• Generates and consumes traffic
• Provides a Graphical User Interface (GUI) to report status and performance
statistics
Hardware Demonstration Setup Instructions
This section describes how to set up the hardware demonstration for the Virtex-6 FPGA
Connectivity TRD. This demonstration outlines a bridging function between PCIe and
XAUI protocols. It also provides accesses to an onboard DDR3 memory.
1. Equipment Checklist: The following equipment is required to run the hardware
demonstration:
• Virtex-6 FPGA Connectivity Kit
• PC system with a x8 PCIe slot on the motherboard, CD ROM drive, and a USB
port
• Monitor, keyboard, and mouse
2. Inadequate Equipment: Run the alternate demonstration.
If there is no access to any of the equipment in step 1, refer to Getting Started with the
Virtex-6 FPGA IBERT Reference Design, page 64 to alternately bring up the ML605
board included in the Virtex-6 FPGA Connectivity Kit. Otherwise, continue with the
PCIe to XAUI protocol demonstration in step 3.
3. Completion of Hardware Setup Guide Checkpoint:
If the instructions in the Virtex-6 FPGA Connectivity Kit Hardware Setup Guide have
already been completed to bring up the Virtex-6 FPGA Connectivity Kit, proceed to
Evaluating the Virtex-6 FPGA Connectivity TRD, page 33; otherwise, continue to
step 4.
4. Hardware Setup I: Board setup and configuration.
The ML605 board is shipped with the FMC Connectivity daughter card attached to the
FMC_HPC connector (see Figure 2). To run the Connectivity TRD demonstration, you
need to externally loop back the XAUI data through a CX4 loopback connector
provided in the connectivity kit.
a. Verify the switch settings are correct:
-SwitchS1:1=OFF,2=OFF,3=OFF,4=ON
-Switch S2: 1 = ON, 2 = OFF, 3 = OFF, 4 = ON, 5 = ON, 6 = OFF
b. Verify that Jumper J42 has pins 3-4 shorted.
c. Plug in the CX4 loopback connector:
-Remove the plastic pin protector.
-Plug in the CX4 loopback connector on the FMC Connectivity daughter card’s
J2 connector (see Figure 3).

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Getting Started with the Connectivity Targeted Reference Design Demo
X-Ref Target - Figure 2
Figure 2: ML605 and FMC Connectivity Daughter Card
X-Ref Target - Figure 3
Figure 3: CX4 Connector
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Switch S1
J2
J42
Switch S2
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CX4 Loopback Connector
J2

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Getting Started with the Connectivity Targeted Reference Design Demo
5. Hardware Setup II: Connect the power connector:
a. Turn the PC system off.
b. Connect the 12V ATX power supply’s available 4-pin disk-drive-type power
connector of the PC system to the board (J25).
Caution! Using any power supply connector other than the 4-pin inline connector results in
damage to the PC system and the ML605 board.
c. The power switch SW2 should be switched to the ON position (away from the
bracket edge of the ML605 board) as shown in Figure 4.
6. Hardware Setup III: Insert the ML605 board into an empty PCIe slot:
a. Identify a x8 or a x16 PCIe slot on the PC motherboard.
b. Insert the ML605 board with FMC daughter card and CX4 loopback module in the
PCIe slot through the PCIe x8 edge connector.
c. On power-up, the connectivity targeted reference design for PCIe to XAUI is
loaded from the Platform Flash.
After the hardware setup is complete, the user can choose to install the Windows driver or
the Linux driver. Proceed to Install Linux Driver, page 27 to verify the design on the
Fedora 10 operating system.
X-Ref Target - Figure 4
Figure 4: 12V ATX Power Supply Connector
UG664_04_022310
J60 SW2J25

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Getting Started with the Connectivity Targeted Reference Design Demo
Install Windows Driver
7. Ignore the Found New Hardware Wizard:
a. Power the PC system on and wait for the operating system (OS) to load.
b. The system recognizes a new PCIe endpoint card connected to it and starts the
Found New Hardware Wizard.
c. Click on Cancel to close the wizard (Figure 6).
X-Ref Target - Figure 5
Figure 5: Insert the ML605 Board into the PCIe Slot
UG664_05_011610
X-Ref Target - Figure 6
Figure 6: Ignore Found New Hardware Wizard
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8. Copy the contents of the USB flash drive:
a. The reference design files are provided on the USB flash drive delivered with the
connectivity kit.
b. Insert the USB flash drive into a USB connector of the PC system and copy the
v6_pcie_10Gdma_ddr3_xaui_axi folder to the PC system.
Note: Ensure that the path where the v6_pcie_10Gdma_ddr3_xaui_axi folder is located does
not have spaces.
9. Install the drivers and GUI:
a. Navigate to the v6_pcie_10Gdma_ddr3_xaui_axi folder.
b. Double click on x_v6_trd_setup.exe (Figure 7).
X-Ref Target - Figure 7
Figure 7: Run x_v6_trd_setup.exe
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Getting Started with the Connectivity Targeted Reference Design Demo
c. The InstallShield wizard for the Virtex-6 FPGA Connectivity TRD is launched
(Figure 8). Click on Next to select the setup type.
X-Ref Target - Figure 8
Figure 8: InstallShield Wizard is Launched
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Getting Started with the Connectivity Targeted Reference Design Demo
d. Select Typical to set C:\Program Files as the destination directory where
driver files will reside. Click on Next and confirm the Setup Type selection
(Figure 9).
X-Ref Target - Figure 9
Figure 9: Set Directory to which the Driver Files are Copied
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Getting Started with the Connectivity Targeted Reference Design Demo
e. Click on Next. When the InstallShield wizard completes, click on Finish
(Figure 10). At the end of this install process, the driver and GUI files are copied to
the C:\Program Files\Xilinx Inc\Virtex6 folder. Also, a shortcut to the
Xilinx Performance Monitor (xpmon) GUI is available on the desktop.
X-Ref Target - Figure 10
Figure 10: InstallShield Wizard Copies GUI and Driver Files into Program Files
when Done
UG664_61_060811

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Getting Started with the Connectivity Targeted Reference Design Demo
10. Load the drivers:
a. After the InstallShield wizard completes, Add Hardware Wizard is launched
(Figure 11). Click on Next.
X-Ref Target - Figure 11
Figure 11: Launch Add Hardware Wizard
UG664_62_052011