Xilinx AC701 Si5324 Guide
November 2014
AC701 Si5324 Design
XTP231
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Revision History
Date Version Description
11/24/14 10.0 Recompiled for 2014.4.
10/08/14 9.0 Recompiled for 2014.3.
06/09/14 8.0 Recompiled for 2014.2.
04/16/14 6.0 Recompiled for 2014.1.
12/18/13 5.0 Recompiled for 2013.4.
10/23/13 4.0 Recompiled for 2013.3. Converted to IPI.
06/19/13 3.0 Recompiled for 2013.2. AR55431 and AR55738 fixed.
04/03/13 2.0 Recompiled for 2013.1. Added AR55431 and AR55738.
02/04/13 1.0 Initial version. As per AR54044, added 2012.4 device pack.
Overview
Xilinx AC701 Board
Software Requirements
AC701 Setup
Reducing Jitter with the Si5324
Compile AC701 Si5324 Design
References
Note: This presentation applies to the AC701
AC701 Si5324 Design Description
Description
–The Si5324 application uses an EDK MicroBlaze system to change the settings
for the Si5324 chip on the AC701 board via IIC
–Note: This design illustrates the relative differences of a Jitter Attenuator device
in Bypass mode or in PLL mode. Neither the Evaluation board nor the design
are for characterization purposes. Please see the Silicon Labs web site for
Jitter Attenuator device data.
Reference Design Source
–AC701 Si5324 Design Files (2014.4 C) ZIP file
–Available through http://www.xilinx.com/ac701
Note: Presentation applies to the AC701
Xilinx AC701 Board
Vivado Software Requirements
Xilinx Vivado Design Suite 2014.4, Design Edition
Note: Presentation applies to the AC701
AC701 Setup
Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent)
connector on the AC701 board
–Connect this cable to your PC
–Power on the AC701 board
AC701 Si5324 Setup
Unzip the AC701 Si5324 Design Files (2014.4 C) ZIP file
–Available through http://www.xilinx.com/ac701
Note: Presentation applies to the AC701
Reducing Jitter with the Si5324
Reducing Jitter with the Si5324
A means of measuring
jitter is required for this
section
A LeCroy 816Zi-A Scope
was used (stock photo
shown)
Note: Presentation applies to the AC701
Reducing Jitter with the Si5324
Connect SMA cables to J33 and J34, USER_GPIO_P/N
Connect these cable to your oscilloscope
Reducing Jitter with the Si5324
Open a Vivado Tcl Shell:
Start →All Programs →Xilinx Design Tools →Vivado 2014.4 →
Vivado 2014.4 Tcl Shell
Note: Presentation applies to the AC701
Reducing Jitter with the Si5324
Download the “bypass” bitstream with Vivado
In the Vivado Tcl Shell type:
cd C:/ac701_si5324/ready_for_download
source bypass_download.tcl
Note: Presentation applies to the AC701
Reducing Jitter with the Si5324
LeCroy Oscilloscope setup
Press the Default Setup followed by the Auto Setup twice
Reducing Jitter with the Si5324
Adjust the Horizontal knob until you have 5 μs/div
Reducing Jitter with the Si5324
From the LeCroy scope menu, select Analysis → Serial Data…
Reducing Jitter with the Si5324
Select “Quick View”
Reducing Jitter with the Si5324
Set the inputs to Input1-Input2 and the Data to match your setup and
click OK
Reducing Jitter with the Si5324
Click the Close button
Reducing Jitter with the Si5324
Note that the DCD (Duty Cycle Distortion) is 53.6 ps
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