Xilinx XtremeDSP Spartan-3A DSP 3400A... User manual

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XtremeDSP™
Development
Platform:
User Guide [optional]
UG498 (v2.2) November 17, 2008 [optional]
XtremeDSP™
Development Platform:
Spartan-3A DSP 3400A
Edition
User Guide
UG498 (v2.2) November 17, 2008
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XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
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contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
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Revision History
The following table shows the revision history for this document.
Date Version Revision
6/2007 0.1 Preliminary version.
7/2007 0.2 Added appendix.
7/2007 0.3 Updated version for final review.
8/2007 1.0 • Updated FMC information.
• Updated support information.
• Added FPGA pin assignments for DDR2 interface.
• Added FPGA pin assignments for USB/System ACE interface.
9/2007 1.1 Added Known Issues section: Limitation of DDR2 clock rate to 133 MHz; Soft Touch
connector not compliant with Agilent probes; FMC connector is in violation of some
rules of the standard.
10/2007 1.2 • Updated Table 20 (Serial Port FPGA Pin Assignments) and modified layout to reflect
change in corporate image.
• Updated for XtremeDSP Spartan-3A DSP Development Board Revision D.
10/2007 2.0 Updated for XtremeDSP Spartan-3A DSP Development Board Revision.
1/2008 2.1 Updated with new clock generator configuration.
11/17/08 2.2 • Ported to Xilinx template.
• Updated Table 12 (FMC Pin G3 is attached to net 1_CLK0_C2M_N).
• Updated to account for PS6 being the power supply used for FMC 2 adjustable voltage.
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Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 1: Introduction
Spartan-3A DSP 3400A Edition Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Spartan-3A DSP 3400A Edition Board Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Board Parts: Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Individual Board Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Board Parts: Bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FMC Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR2 Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR2 Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DDR2 Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
MIG Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
I2C Bus Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 2: Configuration Options
JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
System ACE Controller Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Board Flash Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SPI Flash Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 3: Programming the IDT Clock Chip
Downloading to the Spartan-3A DSP 3400A Edition Board. . . . . . . . . . . . . . . . . . . 49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Appendix: Technical Specifications
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Maximum Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table of Contents
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Chapter 1: Introduction
Figure 1-1: Spartan-3A DSP 3400A Edition Board Block Diagram. . . . . . . . . . . . . . . . . . . 17
Figure 1-2: Top View of Spartan-3A DSP 3400A Edition Board . . . . . . . . . . . . . . . . . . . . . 18
Figure 1-3: Spartan-3A DSP 3400A Edition Board Power Supply . . . . . . . . . . . . . . . . . . . 29
Figure 1-4: Bottom View of Spartan-3A DSP 3400A Edition Board . . . . . . . . . . . . . . . . . . 40
Chapter 2: Configuration Options
Figure 2-1: Spartan-3A DSP 3400A Edition Board JTAG Chain . . . . . . . . . . . . . . . . . . . . 47
Chapter 3: Programming the IDT Clock Chip
Figure 3-1: P2 IDT5V9885 JTAG Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 3-2: Programming the IDT5V9885 on the Spartan-3A DSP 3400A
Edition Board Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 3-3: Programming the IDT5V9885 on the Spartan-3A DSP 3400A
Edition Board Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Schedule of Figures
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Chapter 1: Introduction
Table 1-1: USB/System ACE Interface Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-2: AC'97 SoundMAX Codec Interface Pin Assignments . . . . . . . . . . . . . . . . . . . . 20
Table 1-3: DVI Interface Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-4: Default Ethernet PHY Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-5: Ethernet Interface Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-6: Memory Enable Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-7: PS/2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-8: Soft Touch Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-9: FMC #1 Expansion Connector Pin Assignments (1) . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-10: FMC #1 Expansion Connector Pin Assignments (2) . . . . . . . . . . . . . . . . . . . . . 27
Table 1-11: FMC #2 Expansion Connector Pin Assignments (1) . . . . . . . . . . . . . . . . . . . . . 30
Table 1-12: FMC #2 Expansion Connector Pin Assignments (2) . . . . . . . . . . . . . . . . . . . . . 31
Table 1-13: Reset Connection Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 1-14: Clock Generator Default Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 1-15: I2C FPGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 1-16: FPGA Fan Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 1-17: FPGA I/O Bank Voltage Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 1-18: FPGA LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 1-19: User-defined Button FPGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 1-20: Serial Port FPGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 1-21: Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 1-22: User-defined DIP Switch FPGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . 37
Table 1-23: User-defined LED FPGA Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 1-24: Configuration DIP Switch Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 1-25: Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 1-26: Status LED Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 1-27: Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 1-28: FPGA DDR2 Interface Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 1-29: I2C Slave Device Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Schedule of Tables
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Preface
About This Guide
The XtremeDSP™ Development Platform: Spartan-3A DSP 3400A Edition User Guide provides
instructions for designing and accelerating the development of new products. The
XtremeDSP Development Platform: Spartan-3A DSP 3400A Edition board is an excellent
medium for consumer-oriented wireless and multimedia video applications, where cost-
efficient solutions are essential. Throughout the remainder of this guide, the development
board may be referred to as both the XtremeDSP Development Platform: Spartan-3A DSP
3400A Edition board and the Spartan-3A DSP 3400A Edition board.
Guide Contents
The User Guide contains the following chapters:
•Preface, “About this Guide” introduces the organization and purpose of the User
Guide and the conventions used in this document.
•Chapter 1, “Introduction,” identifies the major components, parts, and functionality
of the Spartan-3A DSP 3400A Edition board.
•Chapter 2, “Configuration Options,” provides an overview of the four configuration
methods available on the FPGA on the Spartan-3A DSP 3400A Edition board.
•Chapter 3, “Programming the IDT Clock Chip,” provides step-by-step instructions for
using the IDT software to generate a combination of clock frequencies and implement
them on the development board.
•Appendix, “Technical Specifications,” identifies the Spartan-3A DSP 3400A Edition
board technical specifications.
Additional Resources
To find additional documentation, see the Xilinx website at:
www.xilinx.com/support/documentation
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
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Preface: About This Guide
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Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold Literal commands that you enter
in a syntactical statement ngdbuild design_name
Italic font
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Square brackets [ ]
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
ngdbuild [
option_name ]
design_name
Braces { } A list of items from which you
must choose one or more lowpwr ={on|off}
Vertical bar | Separates items in a list of
choices lowpwr ={on|off}
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . . Repetitive material that has
been omitted
allow block block_name loc1
loc2 ... locn;
Convention Meaning or Use Example
Blue text Cross-reference link to a location
in the current document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
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Conventions
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Red text Cross-reference link to a location
in another document
See Figure 2-5 in the Virtex-II
Platform FPGA User Guide.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.
Convention Meaning or Use Example
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Preface: About This Guide
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Chapter 1
Introduction
This chapter identifies the major components, parts, and functionality of the Spartan-3A
DSP 3400A Edition board.
Spartan-3A DSP 3400A Edition Board Overview
Figure 1-1 displays a block diagram of the Spartan-3A DSP 3400A Edition board.
X-Ref Target - Figure 1-1
Figure 1-1: Spartan-3A DSP 3400A Edition Board Block Diagram
DVI
RJ45
10Base-T/100Base-TX/
1000Base-T Ethernet PHY
CompactFlash
CPLD
SPI
EEPROM
ZBT SRAM
(256 Mb)
FMC (34 diff/68 se)
36
FMC (34 diff/68 se)
USB
Peripheral USB
Controller
USB
Host
Spartan-3A
DSP FPGA
(XC3SD3400A)
SystemAce
LCD
(16x2 Pixels)
DDR2 SDRAM
(SODIMM)
DB9
(RS232)
FMC Expansion Module 2FMC Expansion Module 1
Video
Encoder
Audio
Codec
Clock
Generator
I
2
C EEPROM
Soft Touch
PS/2 Mouse
PS/2 Keyboard
Audio Mic In
Audio In
Audio Out
Audio Line Out
SP Dif Out
Platform
Flash Memory
Flash Memory
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Chapter 1: Introduction
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Spartan-3A DSP 3400A Edition Board Hardware
Board Parts: Top
Figure 1-2 illustrates the parts on the top of the Spartan-3A DSP 3400A Edition board. Each
numbered item in the diagram is followed by a numbered description.
X-Ref Target - Figure 1-2
Figure 1-2: Top View of Spartan-3A DSP 3400A Edition Board
2113 5 9 13 14
15
172426 23
27 25
28
29
31
33
32
20
10 12 81 4 7
6
35
34
21
36
22
30
1819 16
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Spartan-3A DSP 3400A Edition Board Hardware
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Individual Board Parts
1. USB Controller
The Cypress CY7C67300 embedded USB host controller provides high-speed USB
connectivity for the board, and supports host and peripheral modes of operation (see
“2. USB Peripheral Port” and “3. USB Host Port”). The USB controller also has two
Serial Interface Engines (SIE) that can be used independently. SIE1 is connected to the
USB host port (“3. USB Host Port”), and SIE2 is connected to the USB peripheral port
(“2. USB Peripheral Port”).
The USB controller is equipped with an internal microprocessor to assist in processing
USB commands. The firmware for this processor can be stored in its dedicated I2C
EEPROM (U41) or downloaded from a host computer through the USB peripheral port
(below). Jumper JP1 can be installed (shorting pins 1 and 2) to prevent the USB
controller from executing firmware stored in the I2C EEPROM. The FPGA pins used
for the USB interface are shared with the System ACE interface, as identified in
Table 1-1.
2. USB Peripheral Port
Type B connector, used to connect peripheral USB devices to the Spartan-3A DSP
3400A Edition board.
3. USB Host Port
Type A connector, used to connect a host device to the Spartan-3A DSP 3400A Edition
board.
Table 1-1: USB/System ACE Interface Pin Assignments
FPGA Pin Description FPGA Pin Description
AE13 sysace_clk_in (System ACE only) Y17 sace_usb_d_0
AE23 sace_mpce (System ACE only) AD21 sace_usb_d_1
AA18 sysace_mpbready (System ACE only) AA17 sace_usb_d_2
AB18 sysace_mpirq (System ACE only) AE21 sace_usb_d_3
W17 usb_csn (USB only) V16 sace_usb_d_4
AA9 usb_int (USB only) AC20 sace_usb_d_5
AD22 usb_reset (USB only) AD20 sace_usb_d_6
AC21 sace_usb_oen U16 sace_usb_d_7
V17 sace_usb_wen AF20 sace_usb_d_8
AF4 sace_usb_a_0 AE20 sace_usb_d_9
W9 sace_usb_a_1 AC19 sace_usb_d_10
Y9 sace_usb_a_2 AF19 sace_usb_d_11
AE3 sace_usb_a_3 AE19 sace_usb_d_12
AF3 sace_usb_a_4 AD19 sace_usb_d_13
V15 sace_usb_a_5 AC16 sace_usb_d_14
U15 sace_usb_a_6 AB16 sace_usb_d_15
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Chapter 1: Introduction
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4. AC'97 SoundMAX Codec
Analog Devices AD1981B. The device supports 16-bit stereo audio and sampling rates
up to 48 kHz. The sampling rate for recording and playback can also be different.
Table 1-2 defines the pin assignments.
5. DVI Connector
Used to connect an external video monitor (DVI or VGA) to the Spartan-3A DSP 3400A
Edition board. Table 1-3 defines the pin assignments.
Note: The VGA monitor can be connected to the development board with a
DVI-to-VGA adaptor (sold separately).
6. Display Controller Device
The DVI circuitry uses a Chrontel CH7301C capable of 24-bit color and 1600 ×
1200-pixel resolution. The display controller device drives the digital and analog
signals to the DVI connector (“5. DVI Connector”). The display controller device is
controlled through the I2C bus.
The DVI connector supports the I2C protocol, allowing the development board to read
monitor configuration parameters, which can then be read by the FPGA through the
I2C bus. See “I2C Bus Addressing,” page 42 for detailed information.
Table 1-2: AC'97 SoundMAX Codec Interface Pin Assignments
FPGA Pin Description
AC14 CODEC_BIT_CLK
AC15 CODEC_RESET_B
AB6 CODEC_SDATA_IN
AD14 CODEC_SDATA_OUT
W15 CODEC_SYNC
Table 1-3: DVI Interface Pin Assignments
FPGA Pin Description FPGA Pin Description
AE7 DVI_D_0 V10 DVI_D_10
AE6 DVI_D_1 U11 DVI_D_11
AC8 DVI_D_2 AD17 DVI_DE
AD7 DVI_D_3 AF25 DVI_GPOI1
AB7 DVI_D_4 AC11 DVI_H
AF5 DVI_D_5 AD15 DVI_RESET_B
AA10 DVI_D_6 AD11 DVI_V
W10 DVI_D_7 AC12 DVI_XCLK_N
Y10 DVI_D_8 AB12 DVI_XCLK_P
V11 DVI_D_9
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UG498 (v2.2) November 17, 2008
Spartan-3A DSP 3400A Edition Board Hardware
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7. Board Flash PROM
Xilinx XCF32P. This flash PROM is used to program the development board FPGA.
The flash PROM can hold up to two distinct configuration images (up to four
compressed configuration images) that can be accessed through the configuration DIP
switches. Requires that you use the same configuration DIP switches to configure the
FPGA from the platform flash PROM. See “33. Configuration DIP Switches” for
detailed information.
8. Ethernet PHY
Marvell Alaska 88E1111 PHY device. This PHY supports 10Base-T, 100Base-TX, and
1000Base-T (Gigabit) Ethernet. The PHY is connected to the board's Ethernet connector
(“9. Ethernet Port”). The Ethernet PHY is initialized under its default configuration
when the development board is turned on or reset. Jumper JP2 selects whether the
PHY's default is RGMII mode (pins 2-3) or GMII mode (pins 1-2). Table 1-4 defines the
default configuration of the Ethernet PHY, which can be modified through software.
Table 1-5 identifies the FPGA pin assignments for building new FPGA files.
Table 1-4: Default Ethernet PHY Configuration
Configuration Pin Board Connection Bit 2 Bit 1 Bit 0
CONFIG0 Vcc 2.5 V PHYADR[2] = 1 PHYADR[1] = 1 PHYADR[0] = 1
CONFIG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0
CONFIG2 Vcc 2.5 V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1
CONFIG3 Vcc 2.5 V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1
CONFIG4 Vcc 2.5 V or
LED_DUPLEX
HCWCFG_MODE
[2] = 0 or 1
HCWCFG_MODE
[1] = 1
HCWCFG_MODE
[0] = 1
CONFIG5 Vcc 2.5 V DIS_FC = 1 DIS_SLEEP = 1 HCWCFG_MODE
[3] = 1
CONFIG6 LED_RX SEL_BDT = 0 INT_POL = 1 50/75 ohm = 0
(50 ohm termination)
Table 1-5: Ethernet Interface Pin Assignments
FPGA Pin Description FPGA Pin Description
AB13 PHY_COL AA14 PHY_RX_CLK
AC10 PHY_CRS AC13 PHY_RX_ER
AC6 PHY_INT AE17 PHY_TXCTL_TXEN
AE4 PHY_MDC W13 PHY_TXC_GTXCLK
AD6 PHY_MDIO V12 PHY_TXD_0
AE9 PHY_RESET_N AB9 PHY_TXD_1
AC17 PHY_RXCTL_RXDV W12 PHY_TXD_2
AF17 PHY_RXD_0 AC9 PHY_TXD_3
AD9 PHY_RXD_1 AA12 PHY_TXD_4
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20 www.xilinx.com Spartan-3A DSP 3400A Edition User Guide
UG498 (v2.2) November 17, 2008
Chapter 1: Introduction
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9. Ethernet Port
10Base-T, 100Base-TX, and 1000Base-T (Gigabit) Ethernet port. Connected to the
Ethernet PHY (“8. Ethernet PHY”).
10. Flash Memory
Intel StrataFlash embedded memory JS28F256P30B95; provides the development
board with 32-MB flash memory. This memory provides non-volatile storage for data,
software, or bitstreams. The device is 16-bits wide. This flash memory can also be used
to program the FPGA. To use the Flash and ZBT memories, the memory enable pin
must be set in the FPGA. Table 1-6 identifies the pin assignment.
Note: The FMC module 1 cannot be used when using ZBT or flash memory. Make sure
that the FMC adjustable power supply no. 1 is configured for 3.3V to use the ZBT or
flash memory. See FMC expansion connector for information about how to configure
the adjustable power supply. The Flash memory shares the same address/data bus as
the ZBT synchronous SRAM (“12. ZBT Synchronous SRAM”).
11. PS/2 Connectors
The Spartan-3A DSP 3400A Edition board is equipped with two PS/2 connectors, one
each for a keyboard and mouse. Bi-directional level shifting transistors allow the 1.8-V
I/O to interface with the 5-V I/O of the PS/2 connectors, which are powered directly
from the 5-V power source of the development board. Connector J17 is used to connect
a mouse, and connector J14 is used to connect a keyboard. Table 1-7 identifies the pin
assignments.
AD12 PHY_RXD_2 AF9 PHY_TXD_5
AD16 PHY_RXD_3 AE8 PHY_TXD_6
AD10 PHY_RXD_4 AF8 PHY_TXD_7
AC22 PHY_RXD_5 Y14 PHY_TX_CLK
AF22 PHY_RXD_6 V13 PHY_TX_ER
AF15 PHY_RXD_7
Table 1-6: Memory Enable Pin Assignment
FPGA Pin Signal Description
R9 MEM_EN_B 0: memory is accessible
1: memory is not accessible
Table 1-5: Ethernet Interface Pin Assignments (Cont’d)
FPGA Pin Description FPGA Pin Description
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