Xilinx Virtex-6 FPGA User manual

Virtex-6LibrariesGuidefor
HDLDesigns
UG623(v14.5)arch20,2013

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Chapter1
Introduction
ThisHDLguideispartoftheISE®documentationcollection.Aseparateversionofthis
guideisavailableifyouprefertoworkwithschematics.
Thisguidecontainsthefollowing:
•Introduction.
•Descriptionsofeachavailablemacro.
•Alistofdesignelementssupportedinthisarchitecture,organizedbyfunctional
categories.
•Descriptionsofeachavailableprimitive.
AboutDesignElements
ThisversionoftheLibrariesGuidedescribesthevaliddesignelementsforVirtex®-6
devices,andincludesexamplesofinstantiationcodeforeachelement.Instantiation
templatesarealsosuppliedinaseparateZIPle,whichyoucanndinyourinstallation
directoryunderISE/doc/usenglish/isehelp.
Designelementsaredividedintothreemaincategories:
•Macros-TheseelementsareintheUniMacrolibraryintheXilinxtool,andareused
toinstantiateprimitivesthatarecomplextoinstantiatebyjustusingtheprimitives.
Thesynthesistoolswillautomaticallyexpandtheunimacrostotheirunderlying
primitives.
•Primitives-XilinxcomponentsthatarenativetotheFPGAyouaretargeting.Ifyou
instantiateaprimitiveinyourdesign,afterthetranslationprocess(ngdbuild)you
willendupwiththeexactsamecomponentinthebackend.Forexample,ifyou
instantiatetheVirtex®-5elementknownasISERDES_NODELAYasauserprimitive,
afteryouruntranslate(ngdbuild)youwillendupwithanISERDES_NODELAY
inthebackendaswell.IfyouwereusingISERDESinaVirtex-5device,thenthis
willautomaticallyretargettoanISERDES_NODELAYforVirtex-5inthebackend.
Hence,thisconceptofa“primitive”differsfromotherusesofthatterminthis
technology.
COREGeneratormaintainssoftwarelibrarieswithhundredsoffunctionaldesign
elements(UniMacrosandprimitives)fordifferentdevicearchitectures.Newfunctional
elementsareassembledwitheachreleaseofdevelopmentsystemsoftware.Inaddition
toacomprehensiveUniedLibrarycontainingalldesignelements,thisguideisonein
aseriesofarchitecture-speciclibraries.
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Chapter1:Introduction
DesignEntryethods
Foreachdesignelementinthisguide,Xilinxevaluatesfouroptionsforusingthedesign
element,andrecommendswhatwebelieveisthebestsolutionforyou.Thefouroptions
are:
•Instantiation-Thiscomponentcanbeinstantiateddirectlyintothedesign.This
methodisusefulifyouwanttocontroltheexactplacementoftheindividualblocks.
•Inference-Thiscomponentcanbeinferredbymostsupportedsynthesistools.You
shouldusethismethodifyouwanttohavecompleteexibilityandportabilityofthe
codetomultiplearchitectures.Inferencealsogivesthetoolstheabilitytooptimize
forperformance,area,orpower,asspeciedbytheusertothesynthesistool.
•Coregen&Wizards-ThiscomponentcanbeusedthroughCOREGeneratoror
otherWizards.Youshouldusethismethodifyouwanttobuildlargeblocksofany
FPGAprimitivethatcannotbeinferred.Whenusingthisow,youwillhaveto
re-generateyourcoresforeacharchitecturethatyouaretargeting.
•MacroSupport-ThiscomponenthasaUniMacrothatcanbeused.These
componentsareintheUniMacrolibraryintheXilinxtool,andareusedtoinstantiate
primitivesthataretoocomplextoinstantiatebyjustusingtheprimitives.The
synthesistoolswillautomaticallyexpandUniMacrostotheirunderlyingprimitives.
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Chapter2
AboutUnimacros
ThissectiondescribestheunimacrosthatcanbeusedwithVirtex®-6devices.The
unimacrosareorganizedalphabetically.
Thefollowinginformationisprovidedforeachunimacro,whereapplicable:
•Nameofelement
•Briefdescription
•Schematicsymbol
•Logictable(ifany)
•Portdescriptions
•DesignEntryMethod
•Availableattributes
•Exampleinstantiationcode
•Formoreinformation
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Chapter2:AboutUnimacros
BRA_SDP_ACRO
Macro:SimpleDualPortAM
Introduction
FPGAdevicescontainseveralblockRAMmemoriesthatcanbeconguredasgeneral-purpose36Kbor18Kb
RAM/ROMmemories.TheseblockRAMmemoriesofferfastandexiblestorageoflargeamountsofon-chip
data.Bothreadandwriteoperationsarefullysynchronoustothesuppliedclock(s)ofthecomponent.However,
readandwriteportscanoperatefullyindependentlyandasynchronouslytoeachother,accessingthesame
memoryarray .Byte-enablewriteoperationsarepossible,andanoptionaloutputregistercanbeusedtoreduce
theclock-to-outtimesoftheRAM.
NoteThiselement,mustbeconguredsothatreadandwriteportshavethesamewidth.
PortDescription
NameDirectionWidth(Bits)Function
OutputPorts
DOOutputSeeCongurationTableDataoutputbusaddressedbyRDADDR.
InputPorts
DIInputSeeCongurationTableDatainputbusaddressedbyWRADDR.
WRADDR,
RDADDR
InputSeeCongurationTableWrite/Readaddressinputbuses.
WEInputSeeCongurationTableByte-WideWriteenable.
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Chapter2:AboutUnimacros
NameDirectionWidth(Bits)Function
WREN,
RDEN
Input1Write/Readenable
SSRInput1Outputregisterssynchronousreset.
REGCEInput1Outputregisterclockenableinput(validonly
whenDO_REG=1)
WRCLK,
RDCLK
Input1Write/Readclockinput.
ConfigurationTable
DATA_WIDTHBRA_SIZEADDRWE
72-3736Kb98
36Kb10 36-19
18Kb9
4
36Kb11 18-10
18Kb10
2
36Kb12 9-5
18Kb11
1
36Kb13 4-3
18Kb12
1
36Kb14 2
18Kb13
1
36Kb15 1
18Kb14
1
DesignEntryethod
Thisunimacrocanbeinstantiatedonly.Itisaparameterizableversionoftheprimitive.ConsulttheConguration
Tableabovetocorrectlycongureittomeetyourdesignneeds.
InstantiationYes
InferenceNo
COREGenerator™andwizardsNo
MacrosupportRecommended
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Chapter2:AboutUnimacros
AvailableAttributes
AttributeDataTypeAllowedValuesDefaultDescription
BRAM_SIZEString"36Kb","18Kb""18Kb"ConguresRAMas"36Kb"or"18Kb"
memory.
DO_REGInteger0,10Avalueof1enablestotheoutput
registerstotheRAMenablingquicker
clock-to-outfromtheRAMatthe
expenseofanaddedclockcycleof
readlatency .Avalueof0allowsa
readinoneclockcyclebutwillhave
slowerclocktoouttiming.
INITHexadecimalAny72-BitValueAllzerosSpeciestheinitialvalueonthe
outputafterconguration.
READ_WIDTH,
WRITE_WIDTH
Integer1-7236SpeciesthesizeoftheDIandDO
buses.
Thefollowingcombinationsare
allowed:
•READ_WIDTH=
WRITE_WIDTH
•Ifasymmetric,READ_WIDTH
andWRITE_WIDTHmustbein
theratioof2,ormustbevalues
allowedbytheunisim(1,2,4,8,
9,16,18,32,36,64,72)
INIT_FILEStringStringrepresenting
lenameand
location
NoneNameofthelecontaininginitial
values.
SIM_COLLISION_
CHECK
String"ALL",
"WARNING_
ONLY",
"GENERATE_X_
ONLY",
"NONE"
"ALL"Allowsmodicationofthesimulation
behaviorifamemorycollisionoccurs.
Theoutputisaffectedasfollows:
•"ALL"-Warningproduced
andaffectedoutputs/memory
locationgounknown(X).
•"WARNING_ONLY"-Warning
producedandaffected
outputs/memoryretainlast
value.
•"GENERATE_X_ONLY"-No
warning.However,affected
outputs/memorygounknown
(X).
•"NONE"-Nowarningand
affectedoutputs/memoryretain
lastvalue.
NoteSettingthistoavalueother
than"ALL"canallowproblemsin
thedesigngounnoticedduring
simulation.Careshouldbetaken
whenchangingthevalueofthis
attribute.PleaseseetheSynthesis
andSimulationDesignGuideformore
information.
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Chapter2:AboutUnimacros
AttributeDataTypeAllowedValuesDefaultDescription
SIM_MODEString"SAFE","FAST"."SAFE"Thisisasimulationonlyattribute.It
willdirectthesimulationmodelto
runinperformance-orientedmode
whensetto"FAST."Pleaseseethe
SynthesisandSimulationDesignGuide
formoreinformation.
SRVALHexadecimalAny72-BitValueAllzeroesSpeciestheoutputvalueofonthe
DOportupontheassertionofthe
synchronousreset(RST)signal.
INIT_00to
INIT_7F
HexadecimalAny256-BitValueAllzeroesAllowsspecicationoftheinitial
contentsofthe16Kbor32Kbdata
memoryarray .
INITP_00to
INITP_0F
HexadecimalAny256-BitValueAllzeroesAllowsspecicationoftheinitial
contentsofthe2Kbor4Kbparity
datamemoryarray.
VHDLInstantiationTemplate
Unlesstheyalreadyexist,copythefollowingtwostatementsandpastethembeforetheentitydeclaration.
LibraryUNISIM;
useUNISIM.vcomponents.all;
--BRAM_SDP_MARO:SimpleDualPortRAM
--Virtex-6
--XilinxHDLLibrariesGuide,version14.5
--Note-ThisUnimacromodelassumestheportdirectionstobe"downto".
--Simulationofthismodelwith"to"intheportdirectionscouldleadtoerroneousresults.
-----------------------------------------------------------------------
--READ_WIDTH|BRAM_SIZE|READDepth|RDADDRWidth|--
--WRITE_WIDTH||WRITEDepth|WRADDRWidth|WEWidth--
--============|===========|=============|==============|============--
--37-72|"36Kb"|512|9-bit|8-bit--
--19-36|"36Kb"|1024|10-bit|4-bit--
--19-36|"18Kb"|512|9-bit|4-bit--
--10-18|"36Kb"|2048|11-bit|2-bit--
--10-18|"18Kb"|1024|10-bit|2-bit--
--5-9|"36Kb"|4096|12-bit|1-bit--
--5-9|"18Kb"|2048|11-bit|1-bit--
--3-4|"36Kb"|8192|13-bit|1-bit--
--3-4|"18Kb"|4096|12-bit|1-bit--
--2|"36Kb"|16384|14-bit|1-bit--
--2|"18Kb"|8192|13-bit|1-bit--
--1|"36Kb"|32768|15-bit|1-bit--
--1|"18Kb"|16384|14-bit|1-bit--
-----------------------------------------------------------------------
BRAM_SDP_MARO_inst:BRAM_SDP_MARO
genericmap(
BRAM_SIZE=>"18Kb",--TargetBRAM,"18Kb"or"36Kb"
DEVIE=>"VIRTEX6",--Targetdevice:"VIRTEX5","VIRTEX6","SPARTAN6"
WRITE_WIDTH=>0,--Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")
READ_WIDTH=>0,--Validvaluesare1-72(37-72onlyvalidwhenBRAM_SIZE="36Kb")
DO_REG=>0,--Optionaloutputregister(0or1)
INIT_FILE=>"NONE",
SIM_OLLISION_HEK=>"ALL",--ollisioncheckenable"ALL","WARNING_ONLY",
--"GENERATE_X_ONLY"or"NONE"
SRVAL=>X"000000000000000000",--Set/Resetvalueforportoutput
INIT=>X"000000000000000000",--Initialvaluesonoutputport
--ThefollowingINIT_xxdeclarationsspecifytheinitialcontentsoftheRAM
INIT_00=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01=>X"0000000000000000000000000000000000000000000000000000000000000000",
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Chapter2:AboutUnimacros
INIT_02=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F=>X"0000000000000000000000000000000000000000000000000000000000000000",
--ThenextsetofINIT_xxarevalidwhenconfiguredas36Kb
INIT_40=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47=>X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48=>X"0000000000000000000000000000000000000000000000000000000000000000",
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