Xilinx EK-U1-VCU128-G-J User manual

VCU128 Evaluaon Board
User Guide
UG1302 (v1.1) April 21, 2021

Table of Contents
Revision History...............................................................................................................4
Chapter 1: Introduction.............................................................................................. 5
Overview.......................................................................................................................................5
Additional Resources.................................................................................................................. 5
Block Diagram..............................................................................................................................6
Board Features............................................................................................................................ 6
Board Specifications....................................................................................................................8
Chapter 2: Board Setup and Configuration......................................................9
Standard ESD Measures............................................................................................................. 9
Board Component Location.....................................................................................................10
Default Switch and Jumper Settings....................................................................................... 13
Installing the Board in a PC Chassis........................................................................................14
FPGA Configuration...................................................................................................................16
Chapter 3: Board Component Descriptions................................................... 18
Overview.....................................................................................................................................18
Component Descriptions......................................................................................................... 18
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 93
Overview.....................................................................................................................................93
Appendix B: Xilinx Constraints File.................................................................... 94
Overview.....................................................................................................................................94
Appendix C: Regulatory and Compliance Information........................... 95
Overview.....................................................................................................................................95
CE Directives.............................................................................................................................. 95
CE Standards..............................................................................................................................95
Compliance Markings............................................................................................................... 96
Appendix D: Additional Resources and Legal Notices.............................97
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Xilinx Resources.........................................................................................................................97
Documentation Navigator and Design Hubs.........................................................................97
References..................................................................................................................................98
Please Read: Important Legal Notices................................................................................. 100
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Revision History
The following table shows the revision history for this document.
Section Revision Summary
04/21/2021 Version 1.1
Board Power System Revised the Renesas smart power stage module part
number in the power system block diagram.
12/21/2018 Version 1.0
Initial release. N/A
Revision History
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Chapter 1
Introduction
Overview
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which uses
stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the
package substrate. The VCU128 evaluaon board for the Xilinx® Virtex® UltraScale+™ FPGA
provides a hardware environment for developing and evaluang designs targeng the
UltraScale+ XCVU37P-2FSVH2892E device. The VCU128 evaluaon board is equipped with
many of the common board-level features needed for design development as listed here:
• DDR4, RLD-3, and QDR-IV component memory
• Ganged small form-factor pluggable (QSFP28) connectors
• Sixteen-lane PCI Express® interface
• Ethernet PHY
• General purpose I/O
• UART interface
Addional features can be supported using modules compable with the VITA-57.4 (FMCP
HSPC) connector on the VCU128 board.
Additional Resources
See Appendix D: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VCU128 evaluaon board.
Chapter 1: Introduction
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Block Diagram
A block diagram of the VCU128 evaluaon board is shown in the following gure.
Figure 1: Evaluation Board Block Diagram
233
not used
232
not used
231
not used
230
not used
229
not used
228
not used
227
226
225
224
235
not used
234
not used
70 71 72 75 74 73 135
133
not used
134
132
131
129
130
not used
128
127
126
125
124
NC
0HBM_43_PWR HBM_43_PWR
69
0
XCVU37P-FSVH2892
68 HBM_83
Not
used
67 64 HBM_43
Not
used
65 66
36-bit QDR-IV SDRAM
(shown at banks 68, 69)
36-bit DQB-port
FMCP HSPC
LA[00:33]
72-bit RLD-3 (2x32Mx36)
MT44K32M36RB-107E
Not used
Not used
QSFP1 TX/RX[1:4]
QSFP1_SI570_CLOCK
QSFP2 TX/RX[1:4]
QSFP2_SI570_CLOCK
SI5328_CLOCK1
QSFP3 TX/RX[1:4]
QSFP3_SI570_CLOCK
SI5328_CLOCK2
QSFP4 TX/RX[1:4]
QSFP4_SI570_CLOCK
SMA_REFCLK_INPUT
FMCP_HSPC_DP[20:23]
FMCP_HSPC_GBTCLK5
FMCP_HSPC_DP[16:19]
FMCP_HSPC_GBTCLK4
FMCP_HSPC_DP[12:15]
FMCP_HSPC_GBTCLK3
FMCP_HSPC_DP[8:11]
FMCP_HSPC_GBTCLK2
FMCP_HSPC_DP[4:7]
FMCP_HSPC_GBTCLK1
FMCP_HSPC_DP[0:3]
FMCP_HSPC_GBTCLK0
72-bit DDR4 Comp. Memory
(4.5X512MX16)
MT40A512M16LY-075E
GPIO 1.8V
ENET
LED[0:7]
PL_I2C0 BUS
UART0, UART1
QSFP1, QSFP4 CTRL
SMA_CLK OUT(P/N)
SYSCTLR_UCA1 (TX/RX)
36-bit DQA-port + common
36-bit QDR-IV SDRAM 4Mx36 Dual-Port
CY7C4142KV13_106FCXC
36-bit DQB-port
Bank 70
PCIE_EP_TX/RX[4:7]
PCIE_EP_TX/RX[0:3]
PCIE_CLK2
PCIE_EP_TX/RX[8:11]
PCIE_CLK1
PCIE_EP_TX/RX[12:15]
INIT LED
DONE LED
PROG_B PB
1.5V BATT.
QSPI 2Gb
System Controller
XC7Z010CLG225
GPIO
X21647-112818
Board Features
The VCU128 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• Virtex® UltraScale+™ XCVU37P-2FSVH2892E device
• Zynq®-7000 SoC XC7Z010 based system controller
• 4.5 GB DDR4 72-bit component memory interface (4.5 x [512 Mb x 16])
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• 144 Mb 36-bit dual-port QDR-IV component memory interface (1 x [4M x 36])
• 288 MB 72-bit RLD3 component memory interface (2 x [1.125 Gb x 36])
• 2 Gb Quad SPI ash conguraon memory
• QSFPF28 - Sixteen (16) GTY transceivers are allocated for a 1x4 QSFP cage
• USB JTAG interface (FTDI FT4232HL with a micro-AB USB connector)
• Clock sources:
○SMA I/F clocks:
- FPGA bank 67 SMA clock P/N
○QSFP clocks:
- Four Si570 I2C programmable clock oscillators (156.25 MHz default)
- QSFP clock recovery Si5328 input to GTY132 and GTY134
- QSFP external SMA di. clock input to GTY131
○Memory I/F clocks:
- Three SiT9120A xed 100 MHz LVDS clock oscillators
○PCIe® I/F clock:
- Fixed 100 MHz HCSL clock from PCI Express® edge input to 1-to-2 clock buer wired
to GTY225 and GTY227
○System controller clock:
- SiT8008A 33.33 MHz single-ended clock oscillator
• 96 GTY transceivers (24 Quads)
○FMCP HSPC connector (twenty-four GTY transceivers)
○4x28 Gb/s QSFP+ connectors (eight GTY transceivers)
○PCIe 16-lane edge connector (sixteen GTY transceivers)
○Not used (forty-eight GTY transceivers)
• PCI Express® Endpoint connecvity
○Gen1 (x1, x2, x4, x8, x16)
○Gen2 (x1, x2, x4, x8, x16)
○Gen3 (x1, x2, x4, x8, x16)
○Dual Gen4 (x1, x2, x4, x8)
• Ethernet PHY SGMII interface with RJ-45 connector
• Dual USB-to-UART bridge with micro-B USB connector (shared FTDI FT4232HL)
Chapter 1: Introduction
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• I2C bus
• Status LEDs
• User I/O (1 x push-buon switch, 8 x LED)
• VITA 57.4 FMC+ HSPC connector (DP[0:23], LA[0:33])
• Power management with I2C voltage monitoring through Intersil power controllers and GUI
•Conguraon opons:
○Quad SPI ash memory
○USB JTAG I/F (FTDI FT4232HL)
○Plaorm cable USB II interface 2x7 2 mm keyed connector
Board Specifications
Dimensions
Height: 7.53 inch (19.14 cm)
Length: 9.50 inch (24.13 cm)
Thickness (±5%): 0.061 inch (0.1549 cm)
Note: A 3D model of this board is not available.
IMPORTANT! The VCU128 board height exceeds the standard 4.376-inch (11.15 cm) height of a
PCI Express® card.
Environmental
Temperature
Operang: 0°C to +45°C, Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 VDC
Chapter 1: Introduction
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Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in
total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
•Aach a wrist strap to an unpainted metal surface of your hardware to prevent electrostac
discharge from damaging your hardware.
• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for
stac control. It does not increase or decrease your risk of receiving electric shock when you
are using or working on electrical equipment.
• If you do not have a wrist strap, before you remove the product from ESD packaging and
installing or replacing hardware, touch an unpainted metal surface of the system for a
minimum of ve seconds.
• Do not remove the device from the anstac bag unl you are ready to install the device in
the system.
• With the device sll in its anstac bag, touch it to the metal frame of the system.
• Grasp cards and boards by the edges. Avoid touching the components and gold connectors on
the adapter.
• If you need to lay the device down while it is out of the anstac bag, lay it on the anstac
bag. Before you pick it up again, touch the anstac bag and the metal frame of the system at
the same me.
• Handle the devices carefully to prevent permanent damage.
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Board Component Location
The following gure shows the VCU128 board component locaons. Each numbered component
shown in the gure is keyed to the table in Board Component Descripons.
IMPORTANT! The board component locaons gure is for visual reference only and might not reect the
current revision of the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be a
reference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic VCU128 version of interest for such details.
Figure 2: Evaluation Board Component Locations
33
27 38
24
32
40
39
30
8
6
29
25
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
24
31
26 36
35
22
23
22
28
44
10
34 34
9
12
21 7
18
16
15
19
17
14
13
37
11
5
2
1
3
20 20
X22144-121718
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Board Component Descriptions
The following table idenes the components, references the respecve schemac page
numbers, and links to a detailed funconal descripon of the components and board features in
Chapter 3: Board Component Descripons.
Table 1: Board Component Descriptions
Callout Feature [U#] = Bottom Notes
Schematic
Page
Number
1Virtex UltraScale+ XCVU37P-2FSVH2892E
Device (with fan-sink on soldered FPGA)
XCVU37P-2FSVH2892E
Cofan 30-4811
2 GTY transceivers, Right-side Quads (twelve
quads)
Embedded within FPGA U1 14-15
3 GTY transceivers, Left-side Quads (twelve
quads)
Embedded within FPGA U1 16-17
4DDR4 Component Memory, 72-bit DDR4
component memory I/F, (U17-U19), [U73,
U74]
5 x Micron MT40A256M16GE-075E 24-26
5RLD3 Component Memory, RLD3 72-bit
component memory I/F (U37, U39)
2 x Micron MT44K32M36RB-107E 29-30
6QDR4 Component Memory (U40) Cypress CY7C4142KV13-106FCXC 27
7Quad SPI Flash Memory (U46) Micron MT25QU02GCBB8E12-0SIT 3
8System Controller, Zynq®-7000 SoC (U42) XC7Z010CLG225 48-50
9 System Controller Quad SPI Flash Memory
[U89]
Micron MT25QU02GCBB8E12-0SIT 49
10 DDR4 Component Memory I/F clock, fixed
100 MHz LVDS [U76]
SiTime SIT9120AI-2D3-33E100.0000 32
11 RLD3 Component Memory I/F clock, fixed
100 MHz LVDS (U45)
SiTime SIT9120AI-2D3-33E100.0000 32
12 QDR4 Component Memory I/F clock, fixed
100 MHz LVDS [U96]
SiTime SIT9120AI-2D3-33E100.0000 32
13 Programmable QSFP1 Clock I2C, LVDS
[U95]
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
40
14 Programmable QSFP2 Clock I2C, LVDS
[U90]
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
40
15 Programmable QSFP3 Clock I2C, LVDS
[U82]
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
40
16 Programmable QSFP4 Clock I2C, LVDS
[U80]
Silicon Labs SI570BAB0000544DG
(default 156.250 MHz)
40
17 QSFP Jitter Attenuated Clock, [U87] Silicon Labs SI5328B-C-GMR 40
18 User QSFP SMA Clock pair J24(P)/J26(N)
input to XCVU37P U1 GTY131
MGTREFCLK1P/N
Rosenberger 32K10K-400L5 12
19 Four 28 Gb/s zQSFP+ Module Connectors,
QSFP1-4 (J42), (J39), (J35), (J32) + 1x4
ganged cage
4 x TE 1551920-2 connectors with TE 2170745-2
cage with heatsink
38, 39
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Table 1: Board Component Descriptions (cont'd)
Callout Feature [U#] = Bottom Notes
Schematic
Page
Number
20 PCI Express Endpoint Connectivity,
PCI Express® 16-lane connector (P1)
16-lane card edge connector 41
21 PCI Express Endpoint Connectivity 100
MHz REFCLK 1-to-2 clock buffer,
differential-to-LVDS [U94]
ICS ICS85411AMLF 14
22 10/100/1000 Mb/s Tri-speed Ethernet PHY
with RJ45, SGMII mode only, [U62], (P2)
TI DP83867ISRGZ with Wurth 7499111221A RJ45
(with magnetics)
37
23 Ethernet PHY Status LEDs, LEDs are
integrated into P2 bezel
Wurth 7499111221A RJ45 integrated status LEDs 37
24 USB JTAG Interface, USB bridge (U8) with
mini-B USB connector (J2) and 2x7 2 mm
prog. cable connector (J4)
FTDI FT4232HL bridge
Hirose ZX62D-AB-5P8 connector
Molex 87832-1420
34
25 I2C Bus, Topology, and Switches I2C0 bus
topology: I2C bus MUX [U55], 16-bit
expansion port [U65]
TI PCA9544ARGYR
TI TCA6416APWR
35
26 I2C Bus, Topology, and Switches I2C0 bus
topology: 2 x I2C bus MUX [U53, U54]
2 x TI TCA9548APWR 36
28 User GPIO LEDs (DS2-DS9), active-High Lumex SML-LX0603GW-TR 47
29 User GPIO pushbutton, CPU reset (SW4),
active-High
E-Switch TL3301EF100QG 47
30 Switches, program_B pushbutton, (SW2),
active-Low
E-Switch TL3301EF100QG 3
31 FMCP Connector J18, (J18) Samtec ASP_184329_01 42-46
32 Board Power System Power Input
Connector, (J16)
2x6 Molex-39-30-1060 52
33 Board Power System power input switch,
on/off slide switch (SW5)
C&K 1201M2S3AQE2 52
34 Board Power System, power management
system (top and bottom)
Intersil power system 54-65
35 Monitoring Voltage and Current, PMBus
2x3 R.A. male pin header (J1)
Amphenol 68021-406HLF 54
36 Configuration Options, FPGA U1
configuration mode DIP switch, (SW1)
4-pole CTS 218-4LPSTRF 3
37 PCI Express Endpoint Connectivity, lane
width select header, (J46)
2x4 0.1-inch male header Sullins PBC36DAAN 41
38 Jumpers, FPGA POR_OVERRIDE select
header, (J14)
1x3 0.1-inch male header Sullins PBC36SAAN 3
39 Jumpers, FPGA VCCINT select header, (J25) 1x3 0.1-inch male header Sullins PBC36SAAN 54
40 Jumpers, SYS CTLR RE-PROG header, (J43) 1x2 0.1-inch male header Sullins PBC36SAAN 50
The VCU128 board schemacs are available for download from the VCU128 Evaluaon Kit
website.
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Default Switch and Jumper Settings
Switches
Default switch sengs are listed in the following table. The switch locaons are shown in Figure
2. The following table also references the respecve schemac page numbers.
Table 2: Default Switch Settings
Switch Function Default Comments Figure 2
Callout
Schematic
Page
SW5 On/Off SPST slide switch OFF Board shipped with power switch off 33 52
SW1 4-pole configuration1
Default = SPI
SW1[1:4] =
0001
Position 1 = System Controller Enable
SW1[2:4] = FPGA U1 mode M[2:0] = 001
36 3
SW2 FPGA_PROG_B P.B. NA U1 XCVU37P PROG_B (active low) 30 3
SW3 SYSCTLR_POR_B P.B. NA U42 XC7Z010 POR_B (active low) Near
29
50
SW4 CPU_RESET P.B. NA U1 XCVU37P USER P.B. (active high) 29 47
Notes:
1. DIP switch sections are active-High (connected net is pulled High when DIP switch is closed = 1).
Jumpers
Default jumper sengs are listed in the following table. Jumper header locaons are shown in
Figure 2. The following table also references the respecve schemac page numbers.
Table 3: Default Jumper Settings
Jumper Function Default Comments Figure 2
Callout
Schematic
Page
J14 Power on reset (POR)
override
2-3 U1 POR_OVERRIDE pin
BG15 to GND
38 3
J25 VCCINT select 1-2 1-2: 0.85V; 2-3: 0.72V139 54
J46 PCIe® lane size select 7-8 16-lane configuration 37 41
J43 SYSCTLR RE-PROG Off U42 XCZU7010 MIO5 pin
A9
40 50
Notes:
1. VCCINT select header J25 should always have a jumper block installed.
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Installing the Board in a PC Chassis
The VCU128 board 12V power input circuitry allows 12V to be applied through one of two
connectors, J16 (typically used with the stand-alone VCU128 power adapter) or JP1, as shown in
the following gure.
Figure 3: 12V Power Entry
X22058-121318
Installaon of the VCU128 board inside a computer chassis is required when developing or
tesng PCI Express® funconality. When the VCU128 board is used inside a computer chassis
(i.e., plugged in to a PCIe slot), power is provided by choosing one of two mutually exclusive ATX
power supply cables as described in this secon (use one cable or the other).
• The ATX power supply 4-pin (1x4) peripheral connector, which requires using the ATX
adapter cable (see the following gure) to connect to J16 on the VCU128 board. The Xilinx
part number for this cable is 2600304. See ATX Power Supply Adapter Cable.
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Figure 4: ATX Power Supply Adapter Cable
To ATX 4-Pin Peripheral
Power Connector
To J16 on VCU128 Board
X21955-121918
• The ATX supply 8-pin (2x4) PCIe power connector, which plugs into JP1 on the VCU128
board.
Steps to Install Board
To install the board in a PC chassis:
1. On the VCU128 board, remove the ve screws retaining the ve rubber feet and standos,
and the PCIe bracket. Reinstall the PCIe® bracket using two of the previously removed
screws.
2. Power down the host computer and remove the power cord from the PC.
3. Open the PC chassis following the instrucons provided with the PC.
4. The VCU128 board has a large cooling fan that requires two adjacent PCIe slots. Ensure the
slot adjacent to the front of the board is free of obstrucons.
5. Remove the PCIe expansion slot cover (at the back of the chassis) which aligns with the
VCU128 PCIe bracket, by removing the screws on the top and boom of the cover.
6. Plug the VCU128 board into the appropriate open slot.
7. Install the top mounng bracket screw into the PC expansion cover retainer bracket to secure
the VCU128 board in its slot.
8. If using the ATX supply 4-pin (1x4) peripheral connector, connect power to the VCU128
board using the ATX power supply adapter cable as shown in the previous gure.
a. Plug the 6-pin 2 x 3 Molex connector end of the adapter cable into J16 on the VCU128
board.
b. Plug the 4-pin 1 x 4 peripheral power connector from the ATX power supply into the 4-
pin adapter connector end of the cable.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into J16 on the VCU128
evaluaon board. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-
pin connector into J16 damages the VCU128 evaluaon board and voids the board warranty.
c. Slide the VCU128 board power switch SW5 to the ON posion. The PC can now be
powered on.
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9. If using the ATX supply 8-pin (2x4) PCIe power connector, plug the connector into VCU128
board JP1. The PC can now be powered on.
FPGA Configuration
The VCU128 board supports two of the ve UltraScale+™ FPGA conguraon modes:
• Quad SPI ash memory (2 Gb)
• JTAG using:
○USB JTAG conguraon port (U8 FT4232HL + USB J2 micro-AB)
○Xilinx Plaorm Cable USB II, 2 mm, keyed at cable header (J4)
Each conguraon interface corresponds to one or more conguraon modes and bus widths, as
listed in the following table. The mode switches M2, M1, and M0 are on SW1 posions 2, 3, and
4, respecvely. The FPGA default mode seng M[2:0] = 001 selects the master SPI
conguraon mode.
Table 4: Configuration Modes
Configuration Mode SW1 DIP Switch
Settings M[2:0] Bus Width CCLK Direction
Master SPI 1x1, x2, x4 Output
JTAG 101 x1 NA
For complete details on conguring the FPGA, see UltraScale Architecture Conguraon User Guide
(UG570). The following gure shows the conguraon mode DIP switch SW1 JTAG switch
posions.
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Figure 5: SW1 JTAG Mode Settings
1 2 3 4
SCE M2 M1 M0
OFF Position = 0
ON Position = 1
SW1
X21648-121918
JTAG
The Vivado®, Xilinx SDK, or third-party tools can establish a JTAG connecon to the XCVU37P
FPGA through the FTDI FT4232 USB-to-JTAG/USB UART device (U8) connected to the micro-
USB connector (J2). Alternavely, a JTAG cable can be connected to the keyed at cable header
(J4). JTAG iniated conguraon takes priority over the conguraon method selected through
the FPGA mode pins M[2:0], wired to SW1 posions [2:4].
Quad SPI
To boot from the dual Quad SPI non-volale conguraon memory, follow these steps.
1. Store a valid XCVU37P FPGA boot image in the 2 Gbit Quad SPI ash device (U46)
connected to the FPGA bank 0 Quad SPI interface. See the VCU128 Restoring Flash Tutorial
(XTP533) for informaon on programming the QSPI.
2. Set the boot mode pins SW1 M[2:0] as indicated in the conguraon modes table in FPGA
Conguraon for master SPI.
3. Power-cycle the VCU128 board. Mode SW1 is callout 36 in Figure 2.
See the VCU128 Soware Install and Board Setup Tutorial (XTP535) for more informaon.
See System Controller for an overview of query and control of select programmable board
features such as clocks, FMCP funconality, and power systems. See the VCU128 System
Controller Tutorial (XTP534) for more informaon.
Chapter 2: Board Setup and Configuration
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Chapter 3
Board Component Descriptions
Overview
This chapter provides a detailed funconal descripon of the board’s components and features.
Table 1 idenes the components, references the respecve schemac page numbers, and links
to the corresponding detailed funconal descripon in this chapter. Component locaons are
shown in Figure 2.
Component Descriptions
Virtex UltraScale+ XCVU37P-2FSVH2892E Device
[Figure 2, callout 1]
The VCU128 board incorporates the VU37P high bandwidth memory (HBM) FPGA, which
ulizes stacked silicon interconnect (SSI) technology to add HBM die next to the FPGA die on the
package substrate. The VCU128 board is populated with the Virtex® UltraScale+™
XCVU37P-2FSVH2892E device. For more informaon on Virtex UltraScale+ FPGAs, see Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
Encryption Key Battery Backup Circuit
The XCVU37P device U1 implements bitstream encrypon key technology. The VCU128 board
provides the encrypon key backup baery circuit shown in the following gure.
Chapter 3: Board Component Descriptions
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VCU128 Board User Guide 18
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Figure 6: Encryption Key Backup Circuit
X21956-112918
The Seiko TS621E rechargeable 1.5V lithium buon-type baery B1 is soldered to the board
with the posive output connected to the XCVU37P device U1 VBATT pin BD13. The baery
supply current IBATT specicaon is 150 nA maximum when the board power is o. B1 is
charged from the VCC1V8_BUS 1.8V rail through a series diode with a typical forward voltage
drop of 0.38V and 4.7 KΩ current limit resistor. The nominal charging voltage is 1.42V.
I/O Voltage Rails
There are 12 I/O banks and 2 high-bandwidth memory (HBM) banks available on the XCVU37P
device. The VCU128 board does not use the HBM banks. The voltages applied to the FPGA I/O
banks on the VCU128 board are listed in the following table.
Table 5: I/O Bank Voltage Rails
FPGA (U1) Bank Power Supply Rail Net Name Voltage
Bank 0 VCC1V8 1.8V
HP bank 64 DDR4_VDDQ_1V2 1.2V
HP bank 65 DDR4_VDDQ_1V2 1.2V
HP bank 66 DDR4_VDDQ_1V2 1.2V
HP bank 67 VCC1V8 1.8V
HP bank 68 QDR4_VDDQ_1V2 1.2V
HP bank 69 QDR4_VDDQ_1V2 1.2V
HP bank 70 QDR4_VDDQ_1V2 1.2V
HP bank 71 VADJ 1.8V
Chapter 3: Board Component Descriptions
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VCU128 Board User Guide 19
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Table 5: I/O Bank Voltage Rails (cont'd)
FPGA (U1) Bank Power Supply Rail Net Name Voltage
HP bank 72 VADJ 1.8V
HP bank 73 RLD3_VDDQ_1V2 1.2V
HP bank 74 RLD3_VDDQ_1V2 1.2V
HP bank 75 RLD3_VDDQ_1V2 1.2V
HBM_43 (not used) VCCHBM/VCCAUX_HBM 1.2V/1.8V
HBM_83 (not used) VCCHBM/VCCAUX_HBM 1.2V/1.8V
DDR4 Component Memory
[Figure 2, callout 4]
The 4.5 GB DDR4 component memory system is comprised of ve 512 Mb x 16 DDR4 SDRAM
devices implemented in clam-shell fashion located at U17-U19 (top) and U73-U74 (boom). Half
of the U19 16-bits are used (4.5 x 16-bits = 72-bit wide interface).
• Manufacturer: Micron
• Part Number: MT40A512M16LY-075E
•Descripon:
○8 Gb (512 Mb x 16)
○1.2V 96-ball TFBGA
○DDR4-2666
The VCU128 XCVU37P FPGA DDR4 interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteriscs (DS923).
The 72-bit wide DDR4 memory system is connected to XCVU37P U1 HP banks 64, 65 and 66.
The DDR4 0.6V VTT terminaon voltage (net DDR4_VTERM_0V6) is sourced from the TI
TPS51200DR linear regulator U71. The DDR4 memory interface bank VREF pins are not
connected, which, coupled with an XDC set_property INTERNAL VREF constraint, invoke the
INTERNAL VREF mode. The connecons between the 72-bit interface DDR4 component
memories and XCVU37P banks 64, 65, and 66 are listed in the following table.
Chapter 3: Board Component Descriptions
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