Xilinx SP305 Spartan-3 User manual

UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide
www.xilinx.com
SP305 Spartan-3
Development Platform
User Guide
UG216 (v1.1) March 3, 2006

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SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006
www.xilinx.com
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UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide
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Revision History
SP305 Spartan-3 Development Platform User Guide
UG216 (v1.1) March 3, 2006
The following table shows the revision history for this document..
Version Revision
11/23/05 1.0 Initial Xilinx release.
3/3/06 1.1 In USB Controller with Host and Peripheral Ports (25) section, added note indicating
non-support for 2nd USB feature.

SP305 Spartan-3 Development Platform User Guide UG216 (v1.1) March 3, 2006
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UG216 (v1.1) March 3, 2006 SP305 Spartan-3 Development Platform User Guide
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Table of Contents
About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SP305 Spartan-3 Development Platform User Guide
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Spartan-3 FPGA (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Adapter and Input Power Switch/Jack (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power Indicator LED (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
On-board Power Supplies (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Oscillator Sockets (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DIP Switches (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
User LEDs (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
User Push Buttons (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
User Push Button LEDs (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU Reset Button (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Program Switch (11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
JTAG Configuration Port (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration Address and Mode DIP Switches (13) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
FPGA HSWAP_EN (14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Platform Flash Memory (15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Platform Flash Configuration Select (16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Platform Flash Enable and Reset Control (17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Done and INIT LED (18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Error LEDs (Active High) (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RS-232 Serial Port 1 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RS-232 Serial Port 2 (21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI (22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Character x 2-Line LCD (23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ROTARY ENCODER (24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
USB Controller with Host and Peripheral Ports (25) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10/100 SMSC Ethernet MAC/PHY (26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10/100 Intel Ethernet PHY (27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
A/D Converter (AD7928) (28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stereo AC97 Audio Codec (29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VGA Output (30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Differential Clock Input And Output With SMA Connectors (31) . . . . . . . . . . . . . . . . 22
Expansion Headers (32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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PS/2 Mouse and Keyboard Ports (33). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ChipScope (34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CAN Controller (MCP2515 and MPC2551) (35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DDR SDRAM (36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ZBT Synchronous SRAM (37). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Linear Flash Memory Chips (38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Expansion JTAG Jumper (39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Bank 3 Voltage selection (40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IIC Bus with 4Kb EEPROM (41). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
IFF (42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Default Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Guide Contents
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About This Guide
The Xilinx Development Platform allows designers to investigate and experiment with
features of the Spartan™-3 family of Xilinx FPGAs. This document describes features and
operation of the SP305 Development Platform.
Guide Contents
This manual contains the following chapter:
•“SP305 Spartan-3 Development Platform User Guide.”
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature/index/htm.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold Literal commands that you
enter in a syntactical statement ngdbuild design_name
Helvetica bold
Commands that you select
from a menu File →Open
Keyboard shortcuts Ctrl+C

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Chapter : About This Guide R
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Italic font
Variables in a syntax
statement for which you must
supply values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
Square brackets [ ]
An optional entry or
parameter. However, in bus
specifications, such as
bus[7:0], they are required.
ngdbuild [ option_name]
design_name
Braces { } A list of items from which you
must choose one or more lowpwr ={on|off}
Vertical bar | Separates items in a list of
choices lowpwr ={on|off}
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . . Repetitive material that has
been omitted
allow block block_name
loc1 loc2 ... locn;
Convention Meaning or Use Example
Blue text
Cross-reference link to a
location in the current
document
Red text Cross-reference link to a
location in another document
See Figure 2-5 in the Virtex-II
Handbook.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.

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Introduction
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SP305 Spartan-3 Development Platform
User Guide
Introduction
The MicroBlaze™ development kit allows designers to investigate and experiment with
features of the Spartan™-3 family of FPGAs. This document describes features and
operation of the SP305 Development Platform.
Features
•Spartan-3 FPGA (XC3S1500-FG676-10)
•64MB DDR SDRAM, 32-bit interface running up to 266 MHz data rate
•One differential clock input pair and differential clock output pair with SMA
connectors
•One 100 MHz clock oscillator (socketed) plus one extra open 3.3V clock oscillator
socket
•General purpose DIP switches, LEDs, and push buttons
•Rotary Encoder with a push button shaft
•Expansion header with 32 single-ended I/O, 16 LVDS capable differential pairs,
14 spare I/O’s, power, JTAG chain expansion capability, and IIC bus expansion
•Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, and
microphone-in (mono) jacks
•Two RS-232 serial port (one stand alone and one attached to the USB Chipset)
•16-character x 2-line LCD display
•4Kb IIC EEPROM
•VGA output with 50 MHz / 24-bit video DAC
•PS/2 mouse and keyboard connectors
•ZBT synchronous SRAM (9Mb) on 32-bit data bus with four parity bits
•Intel StrataFlash (or compatible) linear flash memory chips (8MB)
•10/100 Ethernet Mac-PHY transceiver
•10/100 Ethernet PHY transceiver
•USB interface chip (Cypress CY7C67300) with host and peripheral ports
•CAN and SPI interface ports
•IFF one wire encryption device
•Xilinx XCF32P Platform Flash configuration storage device
•JTAG configuration port for use with Parallel Cable III or Parallel Cable IV cable

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•Onboard power supplies for all necessary voltages
•5V @ 3A AC adapter
•Power indicator LED
Package Contents
If the user purchased part number HW-SP305-US (EU, UK)
•SP305 Board
•5 Volt Power Supply
•Evaluation version of the Xilinx ISE and EDK development tools (60 day evaluation)
If the user purchased part number DO-SP305-DVLP-US (UE,UK)
•SP305 Board
•5 Volt Power Supply
•Full version of the Xilinx ISE and EDK development tools (1 year time-based license)
•USB Download and Debug Cable
•RS232 Null Modem Cable
•RJ45 Ethernet Cable
•Xilinx Embedded Development Kit Reference CD
Additional Information
Please visit the SP305 web site at http://www.xilinx.com/sp305 for more information
about the SP305 Development Platform including:
•Current version of this user guide in PDF format
•Example design files for demonstration of Spartan-3 features and technology
•Demonstration hardware and software configuration files for the Platform Flash
configuration storage device, and linear flash memory chips
•MicroBlaze EDK reference design files
•Full schematics in PDF format and ViewDraw schematic format
•PC board layout in Pads PCB format
•Gerber files in *.pho and *.pdf for the PC board (There are many free or shareware
Gerber file viewers available on the internet for viewing and printing these files)
•Additional documentation, errata, frequently asked questions, and the latest news
For information about the Spartan-3 family of FPGA devices, including product highlights,
data sheets, user guides, and application notes, visit the Spartan-3 web site at
http://www.xilinx.com/spartan3.
Additional information is available from the data sheets and application notes supplied by
the component manufacturers.

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Introduction
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Block Diagram
Figure 2-1 shows a block diagram of the board.
Figure 2-1: Spartan-3 SP-305 Development Platform Block Diagram
Rotary
Encoder
GPIO
(Button/LED/
DIP Switch
100 MHz XTAL
+ User
SMA
(Differential In/
Out Clocks)
Dual PS/2
IFF
Chipscope
High Speed
Debug
Sync
RAM
USB
Controller
Spartan-3
FPGA
I/O Expansion
Header IIC EEPROM
5V Brick 3A
Platform
Flash
Flash
Flash
SEL MAP
SLV SERIAL
JTAG
MSTR SERIAL
16 x 32
Character LCD
Can
Controller
SPI
AC97
Audio CODEC
Line Out/Headphone
Video
Mic In/Line in
RS-232 XCVR
VGA
Host
Peripheral
Peripheral
Serial
10/100/1000
Enet Phy
10/100
Enet Phy
DDR
SDRAM
DDR
SDRAM
32
16
RJ-45
PC
RJ-45
User IIC
Bus
JTAG JTAG
32
5V to USB and PS/2
TPS54310
3A SWIFT
TPS54310
6A SWIFT
TPS54310
3A SWIFT
TPS54310
150mA LDO
12 V
5V
To FPGA Core
1.8 V
To PROM
TPS51100
3A DDR LDO
1.25 V
To VTT
3.3V
To FPGA I/O Digital Supply
2.5 V to DDR SDRAM
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Detailed Description
The SP305 Development Platform is shown in Figure 2-2 (front) and Figure 2-3 (back). The
features/components on the board are identified by numbered yellow balloons. These
features/components are then detailed or described in respectively numbered sections in
the subsequent sections of this document.
Figure 2-2: SP305 Development Platform (front view)
14
14
30
30
32
32
23
23
26
26
19
19
18
18
22
22
34
34
37
37
10
10
11
11
12
12
13
13
17
17
15
15
16
16
36
36
24
24
29
29
28
28
27
27
20
20
21
21
25
25
33
33
5
1
9
8
67
35b
35b
35a
35a
35e
35e
35f
35f
2
4
3
31
31
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Detailed Description
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Spartan-3 FPGA (1)
A Xilinx XC3S1500-FG676-10 FPGA is installed on the development platform (the board).
The FPGA is identified as component (1) in the heading above. The other
features/components are numbered accordingly in the subsequent sections.
Configuration
The board supports configuration in all modes: JTAG, Master Serial, Slave Serial, Master
SelectMAP, and Slave SelectMAP modes. See the “Configuration Options,” page 11 section
for more information.
Figure 2-3: SP305 Development Platform (back view)
2
30
30
21
21
39
39
40
40
33
33
36
36
33
33
41
41
29
29
20
20
26
26
25
25
24
24
12
12
25
25
42
42
5
4
35d
35d
35c
35c
38
38
37
37
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I/O Voltage Rails
The FPGA has 7 banks. The I/O voltage applied to each bank is summarized in Table 2-1.
FPGA Bank I/O Voltage Rail
3.3V
2.5V
2.5V
User selectable as 2.5V or 3.3V using jumper J29
3.3V
3.3V
3.3V
2.5V
AC Adapter and Input Power Switch/Jack (2)
The SP-305 board ships with a 15W (5V @ 3A) AC adapter. The power connector is a 2.1mm
x 5.5mm barrel type plug (center positive). For applications requiring additional power,
such as the use of expansion cards drawing significant power, a larger AC adapter may be
required. If a different AC adapter is used, its load regulation should be less than 10% or
better than +/- 10%. The power switch turns the board on and off by controlling the supply
of 5V to the board.
Power Indicator LED (3)
The PWR Good LED lights when the 1.2V, 2.5V, and 3.3V power supplies are all at their
nominal operating conditions. If the PWR Good LED is off, blinking, or glowing lightly, a
fault condition, such as a short or overload condition, may exist.
On-board Power Supplies (4)
Power supply circuitry on the board generates 1.2V, 1.25V, 1.8V, 2.5V, and 3.3V voltages to
power the components on the board. The 1.2V, 2.5V, and 3.3V supplies are driven by
switching power regulators. When these three switching regulators report they are
running at their nominal voltages, the PWR Good LED is turned on.
The diagram in Figure 2-4 shows the power supply architecture and maximum current
handling on each supply. Note that the typical operating currents are significantly below
Table 2-1: I/O Voltage Rail of FPGA Banks
0
1
2
3
4
5
6
7

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Detailed Description
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the maximum capable. The SP-305 board is normally shipped with a 15W power supply
which should be sufficient for most applications.
Oscillator Sockets (5)
On the back side, the SP305 Development Platform has two crystal oscillator sockets, each
wired for standard LVTTL-type oscillators. (Note: A 100 MHz oscillator is pre-installed in
the X1 SYSCLK socket.) These connect to the FPGA clock pins as shown in Table 2-2. The
oscillator sockets accept half-sized oscillators and are powered by the 3.3V supply.
Label Clock Name FPGA Pin
SYSCLK
USERCLK
DIP Switches (6)
There are eight general purpose (active-high) DIP switches connected to the user I/O pins
of the FPGA. See Table 2-3 for a summary of these connections.
SW1 FPGA Pin SW1 FPGA Pin
Figure 2-4: Power Supply Diagram
TPS54310
3A SWIFT
TPS54310
6A SWIFT
TPS51100
3A DDR LDO
TPS73118
150mA LDO
TPS54310
3A SWIFT
5V Brick
3A
1.25V
to VTT
1.2V
5V
5V to USB and PS/2
2.5V to DDR SDRAM
to FPGA Core
3.3V
to FPGA I/O. Digital Supply
1.8V
to PROM UG216_04_101105
Table 2-2: Oscillator Socket Connections
X1 AD13
X6 AE14
Table 2-3: DIP Switches Connections (SW1)
1 AE8 5 AB9
2AF8 6 AC9
3Y9 7 AD9
4AA9 8 AE9

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User LEDs (7)
There are 4 green LEDs are general purpose LEDs arranged in a row. The LEDs are active
high LEDs directly controllable by the FPGA:
Table 2-4 summarizes the LED definitions and connections
Reference
Designator Label/Definition Color FPGA Pin
GPIO LED 0
GPIO LED 1
GPIO LED 2
GPIO LED 3
.
User Push Buttons (8)
There are five active-high user push buttons available for general purpose usage and are
arranged in a North-East-South-West-Center orientation (only the West one is cited in
Figure 2-2, page 6). The user push button connections are summarized in Table 2-5.
Reference
Designator Label/Definition FPGA Pin
GPIO Switch North
GPIO Switch South
GPIO Switch East
GPIO Switch West
GPIO Switch Center
User Push Button LEDs (9)
There are 5 green LEDs positioned next to the North-East-South-West-Center oriented
push buttons (only the Center one is called out in Figure 2-2, page 6). The LEDs are active
high and are directly controllable by the FPGA:
Table 2-6 summarizes the LED definitions and connections.
Table 2-4: User LED Connections
DS15 Green J3
DS4 Green J4
DS5 Green D22
DS6 Green E22
Table 2-5: User Push Button Connections
SW3 H6
SW4 F3
SW5 G6
SW7 G4
SW6 F1
Table 2-6: User LED Connections
Reference
Designator Label/Definition Color FPGA Pin
DS14 LED North Green K6
DS3 LED South Green G5
DS11 LED East Green F4

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CPU Reset Button (10)
The CPU reset button is an active low push button intended to be used as a system or user
reset button. This button is wired to an FPGA I/O pin so it can also be used as a general
purpose button (see Table 2-7).
Reference
Designator Label/Definition FPGA Pin
FPGA CPU RESET
Program Switch (11)
When pressed, this switch grounds the Program pin of the FPGA. This clears the FPGA.
JTAG Configuration Port (12)
The JTAG configuration port for the board (J20) allows for device programming and FPGA
debug. The JTAG port supports the Xilinx Parallel Cable III or Parallel Cable IV products.
Third-party configuration products may also be available. The JTAG chain may also be
extended to an expansion board by setting jumper J26 accordingly. See the “Configuration
Options,” page 11 section for more information.
Configuration Options
The FPGA on the SP-305 Development Platform can be configured through JTAG by 2
devices:
•Parallel Cable IV cable (JTAG)
•Platform Flash memory
The following section provides an overview of the possible ways the board can be
configured.
DS13 LED West Green F2
DS12 LED Center Green H7
Table 2-6: User LED Connections (Continued)
Reference
Designator Label/Definition Color FPGA Pin
Table 2-7: CPU Reset Connections
SW10 G2

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The FPGA and Platform Flash memory can be configured through the JTAG port. The
JTAG chain of the board is illustrated in Figure 2-5.
The chain starts at the PC4 connector and goes through the Platform Flash memory, the
FPGA, and an optional extension of the chain to the expansion card. Jumper J26 determines
if the JTAG chain should be extended to the expansion card.
The JTAG chain can be used to program the FPGA and access the FPGA for hardware and
software debug. The JTAG chain is also used to program the Platform Flash memory.
The PC4 JTAG connection to the JTAG chain allows a host PC to download bitstreams to
the FPGA using the iMPACT software tool. PC4 also allows debug tools such as the
ChipScope™ Pro Analyzer or a software debugger to access the FPGA.
Configuration Address and Mode DIP Switches (13)
This 3-position DIP switch controls the configuration address and FPGA configuration
mode.
The three switches choose one of eight possible configuration addresses. It provides the
The Platform Flash memory supports up to four different images.
The three rightmost DIP switches set the FPGA configuration mode pins M2, M1, and M0
as shown in Table 2-8.
M2 M1 M0 Mode
Master Serial
Slave Serial
Master Parallel (SelectMAP)
Slave Parallel (SelectMAP)
JTAG
FPGA HSWAP_EN (14)
The default for the Spartan3 FPGA is to have an internal weak pull-up enabled on the
HSWAP_EN FPGA pin. The jumper J37 is used to control if a weak pull-up is present on
the user I/O during configuration. When there is no jumper on J37, a weak pull-up is
applied to the HSWAP_EN pin. The effect will be to disable internal pull-ups on User I/O
during configuration. If a jumper is placed on J37, the HSWAP_EN pin will be grounded.
Figure 2-5: JTAG Chain
PC4
TDI TDO TDI TDO
PlatFlash FPGA
TDI
TDO
Expansion
ug216_05_101105
Table 2-8: Configuration Mode DIP Switch Settings
000
111
011
110
101

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This will cause the Spartan-3 FPGA to attach a weak pull-up to all the User I/O during
configuration.
Platform Flash Memory (15)
The Platform Flash memory can also be used to program the FPGA. The Platform Flash
memory can hold up to four configuration images which are selectable by setting the
jumpers on J25 and J31. By default, with out having any jumpers set, the Platform Flash is
pointing to the first block of the configuration address space.
The board is wired up so the Platform Flash memory can download bitstreams in Master
Serial, Slave Serial, Master SelectMAP (parallel), or Slave SelectMAP (parallel) modes.
Using the iMPACT tool to program the Platform Flash memory, the user has the option to
select which of the four modes to use for programming the FPGA. The configuration mode
DIP switches on the board must be set to match the programming method being used by
the Platform Flash memory.
When set correctly, the Platform Flash memory will program the FPGA upon power-up or
whenever the Prog button is pressed.
Platform Flash Configuration Select (16)
The Platform Flash memory can hold up to four configuration images which are selectable
by setting the jumpers on J25 and J31. By default, without having any jumpers set, the
Platform Flash is pointing to the first block of the configuration address space.
Platform Flash Enable and Reset Control (17)
When using the Platform Flash memory to configure the FPGA, the configuration selector
jumper (J38) must be set to the FPGA_DONE (J38 1-2) or GND (J38 2-3). When set to
FPGA_DONE, the FPGA Done signal will enable the Platform Flash during configuration
and disable it when the Done pin goes high. This will also reset the Platform Flash Address
counter. If it is set to GND, then the Platform Flash will be left in an enabled state, pointing
to the next address after the current configuration data. This will allow the Platform Flash
data space to be used for data storage other than configuration data, where additional
memory will be available to be use as data after the FPGA has configured.
Done and INIT LED (18)
The INIT LED lights upon power-up to indicate that the FPGA has successfully powered
up and completed its internal power-on process.
The DONE LED indicates the status of the DONE pin on the FPGA. It should be lighted
when the FPGA is successfully configured.
Error LEDs (Active High) (19)
There are 2 red LEDs are intended to be used for signaling error conditions such as bus
errors, but can be used for any other purpose. They are active high LEDs directly
controllable by the FPGA:

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Table 2-9 summarizes the Error LED definitions and connections
Reference
Designator Label/Definition Color FPGA Pin
Error 1
Error 2
.
RS-232 Serial Port 1 (20)
The SP-305 board contains two male DB-9 RS-232 serial port to enable the FPGA to
communicate with serial data devices. Because the serial port #1 is wired as a host (DCE)
device, a null modem cable is normally required to connect the board to the serial port on
a PC. The serial port is designed to operate up to 115200 Bd. An interface chip is used to
shift the voltage level between FPGA and RS-232 signals.
Label FPGA Pin Description
UART_SOUT AA11 DB9- P3
UART_SIN Y11 DB9- P3
Note: Because the FPGA is only connected to the TX and RX data pins on the serial port, other RS-
232 signals, including hardware flow control signals, are not utilized. Flow control should be disabled
when communicating with a PC.
RS-232 Serial Port 2 (21)
A secondary serial interface is available on the USB chip. By using header J32 and J33 the
TX and RX can be selected between the USB debug port on the USB controller chip or the
Second FPGA UART port. The USB debug port is selected by moving the jumper on J32
and J33 to the Pin 1,2 setting. The second FPGA UART RX and TX are selected by moving
the jumper on J32 and J33 to the Pin 2,3 setting.
Because the serial port is wired as a host (DCE) device, a null modem cable is normally
required to connect the board to the serial port on a PC. The serial port is designed to
operate up to 115200 Bd. An interface chip is used to shift the voltage level between FPGA
and RS-232 signals.
Label FPGA Pin Description
UART1_SOUT AC8 DB9- P1 -- J32 bottom (2,3)
UART1_SIN AB8 DB9- P1-- J33 bottom (2,3)
Note: Because the FPGA is only connected to the TX and RX data pins on the serial port, other RS-
232 signals, including hardware flow control signals, are not utilized. Flow control should be disabled
when communicating with a PC.
Table 2-9: User and Error LED Connections
DS205 Red AB11
DS206 Red F12
Table 2-10: RS232 FPGA Pin Connections
Table 2-11: RS232 FPGA Pin Connections