Xilinx VCK190 Series User manual

VCK190 Evaluaon Board
User Guide
UG1366 (v1.0) January 7, 2021

Revision History
The following table shows the revision history for this document.
Section Revision Summary
01/07/2021 Version 1.0
Initial release. N/A
Revision History
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 2
Send Feedback

Table of Contents
Revision History...............................................................................................................2
Chapter 1: Introduction.............................................................................................. 5
Overview.......................................................................................................................................5
Navigating Content by Design Process.................................................................................... 6
Additional Resources.................................................................................................................. 7
Block Diagram..............................................................................................................................8
Board Features............................................................................................................................ 9
Board Specifications................................................................................................................. 12
Chapter 2: Board Setup and Configuration....................................................13
Standard ESD Measures........................................................................................................... 13
Board Component Location.....................................................................................................13
Default Jumper and Switch Settings....................................................................................... 17
Versal ACAP Configuration.......................................................................................................21
Chapter 3: Board Component Descriptions................................................... 23
Overview.....................................................................................................................................23
Component Descriptions......................................................................................................... 23
Appendix A: VITA 57.4 FMCP Connector Pinouts......................................... 69
Overview.....................................................................................................................................69
Appendix B: Xilinx Design Constraints............................................................. 70
Overview.....................................................................................................................................70
Appendix C: Pmod FMC..............................................................................................71
Pin Mapping Pmod to FMC...................................................................................................... 72
Appendix D: Regulatory and Compliance Information...........................74
CE Information...........................................................................................................................74
Compliance Markings............................................................................................................... 75
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 3
Send Feedback

Appendix E: Additional Resources and Legal Notices..............................76
Xilinx Resources.........................................................................................................................76
Documentation Navigator and Design Hubs.........................................................................76
References..................................................................................................................................77
Please Read: Important Legal Notices................................................................................... 78
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 4
Send Feedback

Chapter 1
Introduction
Overview
The VCK190 evaluaon board features the Xilinx® Versal™ ACAP XCVC1902 device. The
VCK190 board enables the demonstraon, evaluaon, and development of the applicaons
listed here, as well as other customer applicaons.
• Storage acceleraon
• Data center network acceleraon
• Passive opcal network
•Automove
• Aerospace and defense
• Industrial, scienc, and medical
• Test and measurement
• Embedded vision
• Machine learning
• Audio video broadcast
• Wired and wireless
The VCK190 evaluaon board is equipped with many of the common board-level features
needed for design development, including:
• SFP28 and QSFP28 opcal transceiver support
• LPDDR4 component and DDR4 UDIMM memory
• HDMI
• USB
• PMOD connectors
• CAN and Ethernet networking interfaces
• Two FMC+ expansion ports
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 5
Send Feedback

• PCIe® (up to Gen4x8)
Models of VCK190 Boards
The following table lists the models for the VCK190 evaluaon board. See the VCK190
Evaluaon Board product page for details.
The following table lists the models for the VCK190 evaluaon board. See the VCK190
Evaluaon Board product page for details.
Table 1: Models of VCK190 Evaluation Boards
Kit Description
EK-VCK190-G-ED Xilinx Versal ACAP VCK190 evaluation kit, encryption disabled, no secure boot
support
EK-VCK190-G-ED-J Xilinx Versal ACAP VCK190 evaluation kit, Japan specific
Versal ACAP Kit Numbering
The Versal ACAP kit numbering is illustrated in the following gure.
Figure 1: Kit Numbering
EK - VC
Kit
Type
Options
EK – Evaluation Kit
CK – Characterization Kit
K 190 - G - J
ROHS
Indicator
Regional
Identifier
Silicon indicator
K = kit
Ensures there is no
confusion with silicon P/Ns
Family and series
(e.g., Versal ACAP
and Core)
Examples
VCK190
VMK 180
Options
J – Japan
ED – All other customers
OEM – OEM kit
Product Number
-
Options
G – ROHS
Compliant
ED
X23340-121520
Navigating Content by Design Process
Xilinx® documentaon is organized around a set of standard design processes to help you nd
relevant content for your current development task. This document covers the following design
processes:
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 6
Send Feedback

•Board System Design: Designing a PCB through schemacs and board layout. Also involves
power, thermal, and signal integrity consideraons. For more informaon, see Versal ACAP
Design Process Documentaon Board System Design.
Additional Resources
See Appendix E: Addional Resources and Legal Noces for references to documents, les, and
resources relevant to the VCK190 evaluaon board.
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 7
Send Feedback

Block Diagram
The VCK190 block diagram is shown in the following gure.
Figure 2: Block Diagram
GTY0
GTY1
GTY2
GTY3
GTY
Bank 106
GTY0
GTY1
GTY2
GTY3
GTY
Bank 105
GTY0
GTY1
GTY2
GTY3
GTY
Bank 104
GTY0
GTY1
GTY2
GTY3
GTY
Bank 103
CPM
PMC_MI0[0:25] Bank 500
PMC_MI0[26:51] Bank 501
LP_MI0[0:25] Bank 502
XPIO
Triplet 1
XPIO
Triplet 2
XPIO
Triplet 3
XPIO
Triplet 4
GTY0
GTY1
GTY2
GTY3
GTY
Bank 206
GTY0
GTY1
GTY2
GTY3
GTY
Bank 205
GTY0
GTY1
GTY2
GTY3
GTY
Bank 204
GTY0
GTY1
GTY2
GTY3
GTY
Bank 203
GTY0
GTY1
GTY2
GTY3
GTY
Bank 202
GTY0
GTY1
GTY2
GTY3
GTY
Bank 201
GTY0
GTY1
GTY2
GTY3
GTY
Bank 200
MRMAC
MRMAC
MRMAC
MRMAC
HDMI
HSDP
2x zSFP
Lane 4
Lane 5
Lane 6
Lane 7
PCIe
GEN4
x8 Lane 0
Lane 1
Lane 2
Lane 3
MIO
HDIO
SysC, GPIO
1.8V
HDIO
HDMI, PCIe
3.3V
Versal VC1902
VSVA2197
700 701 702 703 704 705 706 707 708 709 710 711
DDR4 72-bit
UDIMM
LPDDR4
2x (1x32)
LPDDR4
2x (1x32)
FMC+_01 FMC+_02
zQSFP
4
4
4
4
4
4
4
12
12
X23196-121620
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 8
Send Feedback

Board Features
The VCK190 evaluaon board features are listed here. Detailed informaon for each feature is
provided in Chapter 3: Board Component Descripons.
• XCVC1902, VSVA2197 package
• Form factor: extended height PCIe®, double-slot (heatsink clearance)
• Onboard conguraon from:
○USB-to-JTAG bridge
○JTAG pod 2 mm 2x7 at cable connector
○microSD card (PS MIO I/F)
○microSD card (System Controller I/F)
• External boot module (EBM) conguraon opon
○X-EBM-01 dual quad SPI (QSPI)
• Clocks
○ACAP Bank 406 HDMI_REC_CLK_OUT 148.50 MHz
○ACAP Bank 503 RTC Xtal 32.768 kHz
○ACAP Bank 503 Si570 REF_CLK 33.3333 MHz
○ACAP Bank 700 Si570 DDR4_CLK (DIMM) 200 MHz
○ACAP Bank 705 Si570 DDR4_CLK2 (LPDDR4) 200 MHz
○ACAP Bank 711 Si570 DDR4_CLK1 (LPDDR4) 200 MHz
○ACAP Bank GTY103/4 (REFCLK0) PCIe_CLK0/1 100 MHz
○ACAP Bank GTY105 (REFCLK0) Si570 zSFP_SI570_CLK 156.250 MHz
○ACAP Bank GTY105 (REFCLK1) Si570 HSDP_SI570_CLK 156.250 MHz
○ACAP Bank GTY200 (REFCLK0) 8A34001_CLK1_IN 100 MHz
○IEEE-1588 eCPRI 8A34001 clocks (various)
• DDR4 8 GB 72-bit UDIMM
○XPIO triplet 1 (banks 700, 701, 702)
• Two LPDDR4 interfaces (2x32-bit 4 GB components each)
○XPIO triplets 2 (banks 703, 704, 705) and 4 (banks 709, 710, 711)
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 9
Send Feedback

• PL FMCP HSCP (FMC+) connecvity
○XPIO triplet 3 (banks 706, 707, 708)
○FMCP1 HSCP full LA[00:33] bus
○FMCP2 HSCP full LA[00:33] bus
• PL GPIO connecons
○PL UART1 to FTDI
○PL GPIO DIP switch (4-posion)
○PL GPIO pushbuons (two)
○PL GPIO LEDs (four)
○PL GPIO DC conguraon header
○PL SYSCTLR_GPIO[0:5]
• 44 PL GTY transceivers (11 quads)
○PCIe 8-lane edge connector (8, banks GTY103, GTY104)
○HSDP USB3.1 TYPE C (1, bank GTY105)
○zSFP28 (2, bank GTY105)
○HDMI (3, bank GTY106)
○HDMI TX only, RX not used (1, bank GTY106)
○zQSFP28 (4, bank GTY200)
○FMCP1 HSCP DP (12, banks GTY201-GTY203)
○FMCP2 HSCP DP (12, banks GTY204-GTY206)
○Not used (1, bank GTY105)
• PCI Express endpoint connecvity
○Gen1 8-lane (x8)
○Gen2 8-lane (x8)
○Gen3 8-lane (x8)
○Gen4 8-lane (x8)
• PS PMC MIO connecvity
○PS MIO[0:12]: boot conguraon header
- DC QSPI support
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 10
Send Feedback

○PS MIO[13:25]: USB2.0
○PS MIO[26:36, 50:51]: SD1 I/F
○PS MIO[37]: ZU4_TRIGGER
○PS MIO[38:39]: PCIe_WAKE_B, PCIe_PERST_B
○PS MIO[40:41]: CAN1
○PS MIO[42:43]: UART0 to FTDI
○PS MIO[44:47]: I2C1, I2C0
○PS MIO[48:49], PS LPD MIO[0:25]: dual GEM0/1 RGMII Ethernet with stacked RJ-45
• Security: PSBATT buon baery backup
• SYSMON header
•Operaonal switches (power on/o, PROG_B, boot mode DIP switch)
•Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System Controller (XCZU4EG)
The VCK190 provides a rapid prototyping plaorm using the XCVC1902-2VSVA2197 device.
See the Versal Architecture and Product Data Sheet: Overview (DS950) for a feature set overview,
descripon, and ordering informaon.
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 11
Send Feedback

Board Specifications
Dimensions (Extended Height PCIe Form-Factor)
Height: 7.477 inches (18.992 cm)
Length: 9.50 inches (24.13 cm) (¾ PCIe length)
Thickness: 66.87 mil ±10% (1.698 mm ±10%)
Note: Reserve two adjacent PCIe slots to accommodate fan-sink height.
Note: A 3D model of this board is not available.
See the VCK190 evaluaon board website for the XDC lisng and board schemacs.
Environmental
Temperature
Operang: 0°C to +45°C
Storage: -25°C to +60°C
Humidity
10% to 90% non-condensing
Operating Voltage
+12 VDC
Chapter 1: Introduction
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 12
Send Feedback

Chapter 2
Board Setup and Configuration
Standard ESD Measures
CAUTION! ESD can damage electronic components when they are improperly handled, and can result in
total or intermient failures. Always follow ESD-prevenon procedures when removing and replacing
components.
To prevent ESD damage:
•Aach a wrist strap to an unpainted metal surface of your hardware to prevent electrostac
discharge from damaging your hardware.
• When you are using a wrist strap, follow all electrical safety procedures. A wrist strap is for
stac control. It does not increase or decrease your risk of receiving electric shock when you
are using or working on electrical equipment.
• If you do not have a wrist strap, before you remove the product from ESD packaging and
installing or replacing hardware, touch an unpainted metal surface of the system for a
minimum of ve seconds.
• Do not remove the device from the anstac bag unl you are ready to install the device in
the system.
• With the device sll in its anstac bag, touch it to the metal frame of the system.
• Grasp cards and boards by the edges. Avoid touching the components and gold connectors on
the adapter.
• If you need to lay the device down while it is out of the anstac bag, lay it on the anstac
bag. Before you pick it up again, touch the anstac bag and the metal frame of the system at
the same me.
• Handle the devices carefully to prevent permanent damage.
Board Component Location
The following gure shows the VCK190 board component locaons. Each numbered component
shown in the gure is keyed to the table in Board Component Descripons.
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 13
Send Feedback

IMPORTANT! The following gure is for visual reference only and might not reect the current revision of
the board.
IMPORTANT! There could be mulple revisions of this board. The specic details concerning the
dierences between revisions are not captured in this document. This document is not intended to be a
reference design guide and the informaon herein should not be used as such. Always refer to the
schemac, layout, and XDC les of the specic VCK190 version of interest for such details.
Figure 3: Evaluation Board Component Locations
00 Round callout references a component
on the front side of the board
Square callout references a component
on the back side of the board
00
1
40
37
36
39
2
41 22
42
33
34 26
23
11
15
13
8 47
14
50
12
52 43
4
10
48 3
9
7
49
55
54
18
20 21
19
18 53
19
28
38
11
45
44
27
27
16 17
16
17 32
30
31
25
35
5
29
6
24
51
46
X24958-121420
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 14
Send Feedback

Board Component Descriptions
The following table idenes the components and references the respecve schemac
(038-05005-01) page numbers.
CAUTION! Do NOT plug a PC ATX power supply 6-pin connector into the VCK190 board power
connector J16. The ATX 6-pin connector has a dierent pinout than J16. Connecng an ATX 6-pin
connector into J16 damages the VCK190 board and voids the board warranty.
Table 2: Board Component Locations
Callout Ref. Des. Feature Notes Schematic
Page
1 U1 Versal™ ACAP
XCVC1902-2VSVA2197
The heatsink is not shown in
Figure 31
2 J45 DDR4 288-pin DIMM SOCKET/
DDR4 DIMM
FCI 10124677-000100ILF/Micron
MTA9ADF1G72AZ-3G2E1 43
3 U25,U26 LPDDR4 16 GBIT comp. memory
(B710/B711 IF) Micron MT53D512M32D2DS-046 27,28
4 U150,U151 LPDDR4 16 GBIT comp. memory
(B709/B710 IF) Micron MT53D512M32D2DS-046 29, 30
5 J212 Fast-boot module daughter card
connector
Samtec SEAF-30-05.0-L-08-1-A-K-
TR 31
6 SW1 ACAP MODE 4-pole DIP switch,
active-High C&K SDA04H1SBD 12
7 J36 ACAP JTAG 2 mm 2x7 flat-cable
connector Molex 87832-1420 24
8 U20,J207 USB-UART bridge, USB Type-C
connector (USB2.0)
FTDI FT4232HL-REEL, Amphenol
12401598E4#2A 25, 99
9 U99,J308 USB ULPI transceiver, USB 2.0
type A connector
SMSC USB3320C-EZK, WURTH
629104190121 24
10 U104,J302 Versal ACAP SD 3.0 level-
translator circuit, SD card socket
Nexperia IP4856CX25/CZ, ALPS
SCHA4B0419 76
11 U33,U35,U214 I2C bus switches TI TCA9548APWR 44, 45
12 U233 I2C bus expander TI TCA6416APWR 55
13 J287 zSFP/zSFP+ (1x2 stacked)
connector Tyco 2198318-6 45
14 J288 zQSFPConnector TE 1551920-2 47
15 P3 PCIe EndPoint 8-lane edge
connector NA - PCB layout feature 46
16 U198,J307B(UPR) GEM0 SGMII Ethernet PHY,
0x01, RJ45 w/mag
TI DP83867ISRGZ, TE-AMP
2301997-7 dual port 77
17 U134,J307A(LWR) GEM1 SGMII Ethernet PHY,
0x02, RJ45 w/mag
TI DP83867ISRGZ, TE-AMP
2301997-7 dual port 78
18 U43,P2A(UPR) HDMI XMT, TMDS to HDMI level
shifter retimer, 0x22, 0xBC
TI SN65DP159RGZ, TE 1888811-1
dual port 50
19 U55,P2B(LWR) HDMI RCV TMDS retimer, 0x0B,
0xB8
TI TMDS181IRGZT, TE 1888811-1
dual port 51
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 15
Send Feedback

Table 2: Board Component Locations (cont'd)
Callout Ref. Des. Feature Notes Schematic
Page
20 J51 FMCP1 Samtec ASP-184329-01 32-36
21 J53 FMCP2 Samtec ASP-184329-01 37-41
22 DS3-DS6,SW6 User LEDs and 4-pole DIP
switch, active-High
Lumex SML-LX0603GW (green),
C&K SDA04H1SBD 53
23 SW4,SW5 User pushbutton, active-High E-switch TL3301EP100QG 53
24 U216,J309 SPDIF IF driver and RCA jack TI SN74AVC1T45, CUI RCJ-021 79
25 U110,J5 CAN BUS transceiver, 2x4 CAN
header
Nexperia TJA1057GT/3J, SULLINS
PBC04DAAN 80
26 J11 SYSMON 2X6 vertical male pin
header SULLINS PBC06DAAN 12
27 Various Power management system
(top, [bottom]) Infineon regulators 47-60
28 J325 PMBus 3-pin header SULLINS PBC03SAAN 26
29 DS9-DS17,DS19-DS32 Power good LEDs Lumex SML-LX0603GW-TR,
green 83
30 SW13 Power On/Off slide switch C&K 1201M2S3AQE2 46
31 J16 Power connector, 2x3, for AC-DC
power adapter MOLEX 39-30-1060 (mini-fit) 46
32 JP1 Power connector, 2x4, for ATX
PCIe power Astron 6652208-T0003T-H-A 46
33 U64 Fan controller Maxim MAX6643LBBAEE++ 54
34 J233 Fan header (keyed 4-pin) Molex 22-11-2032 54
35
U10,SW2 Power-on reset (POR) with
pushbutton
TI TPS389001DSER, E-switch
TL3301EP100QG 15
U110,J326 Alternate POR source driver and
2x4 select header
TI SN74LVC07A, SULLINS
PBC04DAAN 15
SW15 GEM0 Ethernet PHY reset
pushbutton, active-Low E-switch TL3301EP100QG 77
SW7 GEM1 Ethernet PHY reset
pushbutton, active-Low E-switch TL3301EP100QG 78
36 U2 DDR4 DIMM CLK, 200 MHz, 3.3V
LVDS, 0x60 Silicon Labs SI570BAB000299DG 4
37 U3 LPDDR4 CLK2, 200 MHz, 3.3V
LVDS, 0x60 Silicon Labs SI570BAB000299DG 5
38 U4 LPDDR4 CLK1, 200 MHz, 3.3V
LVDS, 0x60 Silicon Labs SI570BAB000299DG 7
39 U5 HSDP CLK, 156.25 MHz, 3.3V
LVDS, 0x5D Silicon Labs SI570BAB000544DG 8
40 U32 ACAP U1 REF CLK, 33.33 MHz,
1.8V CMOS, 0x5D Silicon Labs SI570JAC000900DG 43
41 U39 PCIe 1:2 buffer, 100 MHz, 3.3V
LVDS IDT 85411AMLF 49
42 U62 HDMI jitter atten., 148.50 MHz,
3.3V LVDS, 0x6C IDT 8T49N241-994NLGI 52
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 16
Send Feedback

Table 2: Board Component Locations (cont'd)
Callout Ref. Des. Feature Notes Schematic
Page
43 U142 SYSCTLR clocks 33.33 MHz & 125
MHz I2C 0x6A
Silicon Labs Si5332FD10259-
GM1 101
44 U192 zSFP CLK, 156.25 MHz, 3.3V
LVDS, 0x5D Silicon Labs SI570BAB000544DG 8
45 U205 IEEE-1588 eCPRI input CLK, 100
MHz, 3.3V LVDS, 0x5F Silicon Labs SI570BAC002038DG 48
46 U219 IEEE-1588 eCPRI CLK, various,
3.3V, 0x58 IDT 8A34001E-000AJG8 104
47 J328-J331 IEEE-1588 eCPRI 8A34001 CLK in
and out SMA pairs Rosenberger 32K10K-400L5 104
48 U125 XCZU4EG System Controller TI MSP430F5342 85-91
49 SW11 System Controller MODE 4-pole
DIP switch, active-High C&K SDA04H1SBD 89
50 J202 System Controller JTAG 2 mm 2
x 7 flat-cable connector Molex 87832-1420 89
51 J206 System Controller SD card
socket ALPS SCHA4B0419 96
52 U132 System Controller LPDDR4 16
GBIT comp. memory Micron MT53D512M32D2DS-046 97
53 U131,J204 System Controller SGMII
Ethernet, RJ45 w/magnetics
Marvell 88E1512-A0-NNP2C000,
Halo HFJ11-1G01E-L12RL 95
54 SW16 System Controller pushbutton
switch, active-High E-switch TL3301EP100QG 88
55 U129,SW12 System Controller POR with
pushbutton
TI TPS389001DSER, E-switch
TL3301EP100QG 88
Notes:
1. The VCK190 evaluation board includes a Cofan USA 30-6156-06 heatsink with a thermal resistance of 0.27°C/W.
Default Jumper and Switch Settings
The following gure shows the VCK190 board jumper header and switch locaons. Each
numbered component shown in the gure is keyed to the applicable table in this secon. Both
tables reference the respecve schemac page numbers.
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 17
Send Feedback

Figure 4: Board Jumper Header and Switch Locations
7
5
8
9
3
14
6
16
11
4
12
2
13
15
1
10
X23150-121420
Jumpers
The following table lists the default jumper sengs.
Table 3: Default Jumper Settings
Callout
Number Ref. Des. Function Default Schematic Page
1 J12
SYSMON VREFP
1-2 12
1-2: 1.024V VREFP connected to ACAP
2-3: VREFP connected to GND
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 18
Send Feedback

Table 3: Default Jumper Settings (cont'd)
Callout
Number Ref. Des. Function Default Schematic Page
2 J26
POR_B sense select
1-2 15
1-2: VCCO_503
2-3: VCCAUX_PMC
3 J32
SFP1_TX_DISABLE select
ON 45
ON: enable always
OFF: disable/allows ACAP U1 control
4 J34
ACAP U1 bank VCC_FUSE select
2-3 17
1-2: VCC1V8
2-3: GND
5 J35
SFP0_TX_DISABLE select
ON 17ON: enable always
OFF: disable/allows ACAP U1 control
6 J37
JTAG MUX U14/U15 OE_B
2-3 24
1-2: UTIL_3V3 disable
2-3: GND enable
7 J60
PCIe lane size select
5-6 46
1-2: x1
3-4: x4
5-6: x8
8 J203
SYSCTLR_POR_B enable
ON 89ON: enable
OFF: disable
9 J205
System Controller M88E1512 EPHY U131 configuration
7-8 95
1:2: GND (5'b00000)
3:4: SYSCTLR_ETH_LED0
5:6: SYSCTLR_ETH_LED0
7:8: SYS_VCC1V8 (5'b00001)
10 J234
ACAP cooling fan control
2-3 54
1-2: MAX6643 U64 control is enabled
2-3: always on
8 J300
ULPI USB3320 U99 USB conn. J308 shield select
1-2 421-2: J308 shield directly to GND
2-3: J308 shield capacitor C2762 to GND
8 J301
IP4856 U104 VERSAL_SD1_REF voltage select
1-2 761-2: UTIL_3V3
2-3: GND
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 19
Send Feedback

Table 3: Default Jumper Settings (cont'd)
Callout
Number Ref. Des. Function Default Schematic Page
11 J306
Si53340 clock MUX U206 input select
OFF 48
ON: CLK1 8a34001_Q2
OFF: U205 USER_SI570_1(100 MHz default)
12 J326
POR_B source select (OR’d with POR_B)
1-2
3-4
7-8
15
None: U10 TPS389001 POR only
1-2: U125 SYSCTLR_POR_B
3-4: J36 PC4_POR_B
5-6: J212(B) DC_PS_POR_B_OUT
7-8: U20 FTDI_POR_B
Switches
The following table lists the default switch sengs.
Table 4: Default Switch Settings
Callout
Number Ref. Des. Function Default Schematic Page
13 SW1 ACAP U1 mode 4-pole DIP switch 0000 14
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW1[4:1] = Mode[3:0]
JTAG = ON,ON,ON,ON = 0000
QSPI32 = ON,ON,OFF,ON = 0010
SD = OFF,OFF,OFF,ON = 1110
Reserved for Xilinx® = OFF,OFF,OFF,OFF = 1111
14 SW3
JTAG MUX select 2-pole DIP switch
01 24
Switch OFF = 1 = High; ON = 0 = Low
SW3[1:2] = MUX[S0:S1]
SYSCTLR U125 BANK 44 = ON,ON = 00
FTDI BRIDGE U20 = ON,OFF = 01
15 SW6
ACAP U1 BANK 306 GPIO 4-Pole DIP switch
0000 53
SW6[4:1] = GPIO_DIP_SW[0:3]
Switch OFF = 0 = Low; ON = 1 = High
16 SW11
ZU4 SYSCTLR U125 Mode 4-Pole DIP switch
0000 89
Switch OFF = 1 = High; ON = 0 = Low
Mode = SW11[4:1] = Mode[3:0]
JTAG = ON,ON,ON,ON = 0000
QSPI32 = ON,ON,OFF,ON = 0010
SD = OFF,OFF,OFF,ON = 1110
Chapter 2: Board Setup and Configuration
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 20
Send Feedback