Xilinx SmartLynq Plus User manual

SmartLynq+ Module User
Guide
UG1514 (v1.0) March 8, 2021

Revision History
The following table shows the revision history for this document.
Section Revision Summary
03/08/2021 Version 1.0
Initial release. N/A
Revision History
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Overview......................................................................................................5
Features........................................................................................................................................5
Description................................................................................................................................... 5
Chapter 2: Connectors................................................................................................. 8
Host Side.......................................................................................................................................8
Target Side................................................................................................................................... 9
Front View.................................................................................................................................. 10
Chapter 3: Installing the SmartLynq+ Module.............................................11
Chapter 4: USB 3.0 Host Connection.................................................................. 12
Minimum Host System Requirements....................................................................................12
Default USB 3.0 IP Setting........................................................................................................ 12
Windows USB 3.0 Driver Setup................................................................................................13
Linux USB 3.0 Setup.................................................................................................................. 16
Changing the USB 3.0 IP Setting............................................................................................. 18
Chapter 5: Ethernet Connection...........................................................................19
Changing the Ethernet IP Settings..........................................................................................19
Chapter 6: SmartLynq+ Module Display.......................................................... 20
Chapter 7: JTAG Target Interface......................................................................... 21
Chapter 8: GPIO Target Interface........................................................................ 25
Chapter 9: HSDP Target Interface....................................................................... 28
Chapter 10: Parallel Debug Interface................................................................35
Appendix A: Regulatory and Compliance Information........................... 38
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Appendix B: Additional Resources and Legal Notices............................. 39
Xilinx Resources.........................................................................................................................39
Documentation Navigator and Design Hubs.........................................................................39
References..................................................................................................................................39
Please Read: Important Legal Notices................................................................................... 40
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Chapter 1
Overview
The Xilinx® SmartLynq+ Module is a high-speed debug and trace module, primarily targeng the
Versal™ adapve compute acceleraon plaorm (ACAP). It drascally improves conguraon and
trace speed. For trace capture, the SmartLynq+ module is capable of speeds up to 10 Gb/s by
means of its high-speed debug port (HSDP), which is 100 mes faster than standard JTAG. Faster
iteraons and repeve downloads increase development producvity and reduce the design
cycle.
Features
The SmartLynq+ Module provides the following features:
• Super-fast download speed, maximize development producvity for faster iteraons
• High-speed trace with enhanced visibility, up to 14 GB of trace memory for execuon history
• Full visibility for heterogeneous architectures, in-depth debug for Hard IP and Engines in
Versal ACAP
• Cohesive and me-related debug of all subsystems
• Flexible and smart debug plaorm with features such as smart ltering and a soware-
programmable built-in debugger
• Sharable debug plaorm with unied view for remote, mul-user environment
Note: The SmartLynq+ Module is not supported by Xilinx ISE® tools.
Description
The SmartLynq+ Module oers high-bandwidth connecvity to allow heterogenous system
debug and trace of Versal ACAP-based applicaons. It provides all of the desired connecons for
programming, debug and trace. JTAG can be a direct connecon with PC4 connector,
MICTOR-38 connector, or via USB-C when used along with HSDP.
Chapter 1: Overview
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The contents of the SmartLynq+ Module kit are shown in the following gure.
Figure 1: SmartLynq+ Module Kit Contents
Physical Description
The SmartLynq+ module circuitry is housed in a plasc enclosure with an OLED display, as shown
in the following gure. The enclosure and heat sink assembly aenuates internally generated
emissions and protects against suscepbility to radiated emissions.
Chapter 1: Overview
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Figure 2: SmartLynq+ Module
CAUTION! The SmartLynq+ module is designed to operate in the temperature range of 10°C to 26°C
(50°F to 80°F). Operang outside of this range might cause malfuncon or permanent damage to the
device.
Chapter 1: Overview
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Chapter 2
Connectors
Connectors on the SmartLynq+ Module are located as follows.
Host Side
The DC power, USB 3.0, and Ethernet connectors are located on the le side of the SmartLynq+
Module, as shown in the following gure.
Figure 3: Host-Side Connections
Chapter 2: Connectors
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Power to the SmartLynq+ Module is supplied by a 12V / 2A DC module connected to the Power
connector. Note that when the DC module is connected to the power connector, the SmartLynq+
Module turns on. The Ethernet connector is always acve when the cable is powered. When an
ethernet cable is connected to the SmartLynq+ module, the cable inializes the ethernet port and
a host can communicate with it by using the IP address shown on the display screen. The USB
3.0 is an alternate host interface that can be used for host communicaon. The USB 3.0 interface
is also acve upon power up and inializes on connecon to an acve USB connecon.
Target Side
The GPIO, JTAG, HSDP, and MICTOR connectors are on the right side of the SmartLynq+
Module, as shown in the following gure.
Figure 4: Target-Side Connections
For standard HSDP communicaon use the HSDP connector. Typically, this is the only
connecon required to a target board such as the Versal ACAP VCK190 evaluaon board. For
target boards without the HSDP connector use the 14 pin JTAG connector using a ribbon cable
or ying leads. The GPIO cable provides addional low-speed signals for controlling the target or
other instruments used alongside the board under test.
Chapter 2: Connectors
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Front View
The reset pin, mode selector switch, and micro-SD card slot are located on the front of the
SmartLynq+ Module, as shown in the following gure.
Figure 5: Front View Connections
The SmartLynq+ Module MODE switch seng determines the source from which the module
boots. When the mode is set towards MICRO SD, the module boots using the SD card image.
When the MODE switch is set away from MICRO SD, the module boots from the EMMC image.
Note that you must have wrien an image to the eMMC for the system to boot properly.
Chapter 2: Connectors
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