Xilinx SmartLynq Plus User manual

SmartLynq+ Module User
Guide
UG1514 (v1.0) March 8, 2021

Revision History
The following table shows the revision history for this document.
Section Revision Summary
03/08/2021 Version 1.0
Initial release. N/A
Revision History
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Table of Contents
Revision History...............................................................................................................2
Chapter 1: Overview......................................................................................................5
Features........................................................................................................................................5
Description................................................................................................................................... 5
Chapter 2: Connectors................................................................................................. 8
Host Side.......................................................................................................................................8
Target Side................................................................................................................................... 9
Front View.................................................................................................................................. 10
Chapter 3: Installing the SmartLynq+ Module.............................................11
Chapter 4: USB 3.0 Host Connection.................................................................. 12
Minimum Host System Requirements....................................................................................12
Default USB 3.0 IP Setting........................................................................................................ 12
Windows USB 3.0 Driver Setup................................................................................................13
Linux USB 3.0 Setup.................................................................................................................. 16
Changing the USB 3.0 IP Setting............................................................................................. 18
Chapter 5: Ethernet Connection...........................................................................19
Changing the Ethernet IP Settings..........................................................................................19
Chapter 6: SmartLynq+ Module Display.......................................................... 20
Chapter 7: JTAG Target Interface......................................................................... 21
Chapter 8: GPIO Target Interface........................................................................ 25
Chapter 9: HSDP Target Interface....................................................................... 28
Chapter 10: Parallel Debug Interface................................................................35
Appendix A: Regulatory and Compliance Information........................... 38
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Appendix B: Additional Resources and Legal Notices............................. 39
Xilinx Resources.........................................................................................................................39
Documentation Navigator and Design Hubs.........................................................................39
References..................................................................................................................................39
Please Read: Important Legal Notices................................................................................... 40
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Chapter 1
Overview
The Xilinx® SmartLynq+ Module is a high-speed debug and trace module, primarily targeng the
Versal™ adapve compute acceleraon plaorm (ACAP). It drascally improves conguraon and
trace speed. For trace capture, the SmartLynq+ module is capable of speeds up to 10 Gb/s by
means of its high-speed debug port (HSDP), which is 100 mes faster than standard JTAG. Faster
iteraons and repeve downloads increase development producvity and reduce the design
cycle.
Features
The SmartLynq+ Module provides the following features:
• Super-fast download speed, maximize development producvity for faster iteraons
• High-speed trace with enhanced visibility, up to 14 GB of trace memory for execuon history
• Full visibility for heterogeneous architectures, in-depth debug for Hard IP and Engines in
Versal ACAP
• Cohesive and me-related debug of all subsystems
• Flexible and smart debug plaorm with features such as smart ltering and a soware-
programmable built-in debugger
• Sharable debug plaorm with unied view for remote, mul-user environment
Note: The SmartLynq+ Module is not supported by Xilinx ISE® tools.
Description
The SmartLynq+ Module oers high-bandwidth connecvity to allow heterogenous system
debug and trace of Versal ACAP-based applicaons. It provides all of the desired connecons for
programming, debug and trace. JTAG can be a direct connecon with PC4 connector,
MICTOR-38 connector, or via USB-C when used along with HSDP.
Chapter 1: Overview
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The contents of the SmartLynq+ Module kit are shown in the following gure.
Figure 1: SmartLynq+ Module Kit Contents
Physical Description
The SmartLynq+ module circuitry is housed in a plasc enclosure with an OLED display, as shown
in the following gure. The enclosure and heat sink assembly aenuates internally generated
emissions and protects against suscepbility to radiated emissions.
Chapter 1: Overview
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Figure 2: SmartLynq+ Module
CAUTION! The SmartLynq+ module is designed to operate in the temperature range of 10°C to 26°C
(50°F to 80°F). Operang outside of this range might cause malfuncon or permanent damage to the
device.
Chapter 1: Overview
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Chapter 2
Connectors
Connectors on the SmartLynq+ Module are located as follows.
Host Side
The DC power, USB 3.0, and Ethernet connectors are located on the le side of the SmartLynq+
Module, as shown in the following gure.
Figure 3: Host-Side Connections
Chapter 2: Connectors
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Power to the SmartLynq+ Module is supplied by a 12V / 2A DC module connected to the Power
connector. Note that when the DC module is connected to the power connector, the SmartLynq+
Module turns on. The Ethernet connector is always acve when the cable is powered. When an
ethernet cable is connected to the SmartLynq+ module, the cable inializes the ethernet port and
a host can communicate with it by using the IP address shown on the display screen. The USB
3.0 is an alternate host interface that can be used for host communicaon. The USB 3.0 interface
is also acve upon power up and inializes on connecon to an acve USB connecon.
Target Side
The GPIO, JTAG, HSDP, and MICTOR connectors are on the right side of the SmartLynq+
Module, as shown in the following gure.
Figure 4: Target-Side Connections
For standard HSDP communicaon use the HSDP connector. Typically, this is the only
connecon required to a target board such as the Versal ACAP VCK190 evaluaon board. For
target boards without the HSDP connector use the 14 pin JTAG connector using a ribbon cable
or ying leads. The GPIO cable provides addional low-speed signals for controlling the target or
other instruments used alongside the board under test.
Chapter 2: Connectors
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Front View
The reset pin, mode selector switch, and micro-SD card slot are located on the front of the
SmartLynq+ Module, as shown in the following gure.
Figure 5: Front View Connections
The SmartLynq+ Module MODE switch seng determines the source from which the module
boots. When the mode is set towards MICRO SD, the module boots using the SD card image.
When the MODE switch is set away from MICRO SD, the module boots from the EMMC image.
Note that you must have wrien an image to the eMMC for the system to boot properly.
Chapter 2: Connectors
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Chapter 3
Installing the SmartLynq+ Module
Prior to using the SmartLynq+ Module you need to download the latest SD card image and the
SmartLynq+ applicaon soware. Go to the SmartLynq+ Module wiki page to access the
download links and installaon instrucons:
Chapter 3: Installing the SmartLynq+ Module
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Chapter 4
USB 3.0 Host Connection
The SmartLynq+ Module can be accessed by a host system using the USB 3.0 connecon. When
accessing the module through the USB 3.0 interface, the host establishes a network interface
used by applicaons such as Vivado® Design Suite to communicate with the module. Vivado
Design Suite version 2020.2 or later is required to support the SmartLynq+ Module for USB3.0
and HSDP.
Note: The SmartLynq+ Module is not powered by the USB 3.0 interface and must have the power cable
plugged in and supplying power prior to use.
Minimum Host System Requirements
These are the supported operang systems on x86 and x86-64 processor architectures:
•Microso Windows Professional/Enterprise 10.0 1809 Update; 10.0 1903 Update; 10.0 1909
Update; 10.0 2004 Update
• Red Hat Enterprise Workstaon/Server 7.4 - 7.8, and 8.2 (64-bit), English/Japanese
• CentOS 7.4 - 7.8, and 8.2 (64-bit), English/Japanese
• Ubuntu Linux 16.04.5 LTS;16.04.6 LTS; 18.04.1 LTS; 18.04.2 LTS, 18.04.3 LTS; 18.04.4 LTS;
and 20.04 LTS (64-bit), English/Japanese
Default USB 3.0 IP Setting
The default factory image seng for the SmartLynq+ Module USB 3.0 interface is 10.0.0.2.
Ensure that 10.0.0.2 IP on the host machine can be used to form a local network for the
SmartLynq+ Module. If necessary, you can change this seng but you sll need to have the host
inially access 10.0.0.2 to be able to change the USB 3.0 IP factory seng.
Chapter 4: USB 3.0 Host Connection
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Windows USB 3.0 Driver Setup
The Windows 10 included RNDIS driver needs to be associated with the SmartLynq+ Module.
These are the steps to associate the cable to the driver. You might need to repeat these steps if
you connect the SmartLynq+ Module to a dierent port on the Windows PC.
1. Connect the SmartLynq+ Module to a Windows PC using the USB-B cable.
2. Open Device Manager. You should see a device named RNDIS.
3. Right-click the RNDIS device and click Update Driver.
4. A new window pops up. Click Browse my computer for driver soware.
.
Chapter 4: USB 3.0 Host Connection
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5. Click Let me pick from a list of available drivers of my computer.
6. Select Network adapters from the list and click Next.
7. Select Microso from the Manufacturer list and select USB RNDIS Adapter from the Model list.
Click Next.
Chapter 4: USB 3.0 Host Connection
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8. You will now see an Update Driver Warning. Click Yes to proceed.
9. You should now see the driver successfully installed.
10. Open the Windows network connecons panel.
11. You should see a device with the descripon USB RNDIS Adapter.
12. Right-click this adapter and click Properes.
13. Select Internet Protocol Version 4 (TCP/IPv4) from the list and click Properes.
Chapter 4: USB 3.0 Host Connection
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14. A new window pops up. Congure the network interface as follows and click OK.
15. You should now be able to access the SmartLynq+ Module at 10.0.0.2
Linux USB 3.0 Setup
Run the ifconfig command to congure the network interface on the IP address Linux
assigned to the SmartLynq+ Module. Linux assigns the IP address as 10.0.0.2. Run ifconfig to
view the currently acve network interfaces on this system. For example:
eth0 Link encap:Ethernet HWaddr D7:45:89:22:88:97
inet addr:172.19.3.148 Bcast:172.19.3.255 Mask:255.255.252.0 UP
BROADCAST
RUNNING MULTICAST MTU:1500 Metric:1
RX packets:2278375690 errors:0 dropped:307 overruns:0 frame:0 TX
packets:2305014867 errors:0 dropped:22 overruns:0 carrier:0 collisions:0
txqueuelen:1000
RX bytes:1026403610964 (955.9 GiB) TX bytes:1048839754879 (976.8
GiB)
Interrupt:17
lo Link encap:Local Loopback
Chapter 4: USB 3.0 Host Connection
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inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:41586323 errors:0 dropped:0 overruns:0 frame:0 TX
packets:41586323
errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:0
RX bytes:107897957583 (100.4 GiB) TX bytes:107897957583 (100.4 GiB)
If none of the interface names have an internet address that is part of the protocol address family
that covers the assigned SmartLynq+ Module address, use ifconfig to congure a new
interface.
In the preceding example, the Linux system has two interfaces dened: eth0 and lo. Neither
interface has an internet address format of 10.0.x.x that includes the address 10.0.0.2 assigned
to SmartLynq+ Module. Set up the interface by running ifconfig with the following arguments:
sudo ifconfig eth1 10.0.0.1 netmask 255.255.0.0
Running ifconfig again shows the new interface:
eth0 Link encap:Ethernet HWaddr D7:45:89:22:88:97
inet addr:172.19.3.148 Bcast:172.19.3.255 Mask:255.255.252.0 UP
BROADCAST
RUNNING MULTICAST MTU:1500 Metric:1
RX packets:2278375690 errors:0 dropped:307 overruns:0 frame:0 TX
packets:2305014867 errors:0 dropped:22 overruns:0 carrier:0 collisions:0
txqueuelen:1000
RX bytes:1026403610964 (955.9 GiB) TX bytes:1048839754879 (976.8
GiB)
Interrupt:17
eth1 Link encap:Ethernet HWaddr 00:5D:03:00:00:01
inet addr:10.0.0.1 Bcast:10.0.255.255 Mask:255.255.0.0 UP BROADCAST
RUNNING MULTICAST MTU:1500 Metric:1
RX packets:10 errors:0 dropped:0 overruns:0 frame:0 TX
packets:2 errors:0 dropped:0 overruns:0 carrier:0 collisions:0
txqueuelen:1000
RX bytes:2396 (2.3 KiB) TX bytes:345 (345.0 b)
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:16436 Metric:1
RX packets:41586323 errors:0 dropped:0 overruns:0 frame:0 TX
packets:41586323
errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:107897957583 (100.4 GiB) TX bytes:107897957583 (100.4 GiB
Chapter 4: USB 3.0 Host Connection
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Changing the USB 3.0 IP Setting
To change the default USB 3.0 IP address seng on the SmartLynq+ Module you rst need to set
up the host to communicate using the 10.0.0.2 IP default address. To change the IP address,
connect the host to the module using ssh on the host machine and passing in the IP address
10.0.0.2. When prompted for a user name and password, enter in the default user name xilinx
with the password xilinx.
Aer logging into the SmartLynq+ Module, run the following command to edit the USB network
sengs:
sudoedit /etc/systemd/network/20-usb-gadget.network
This command brings up a linux nano editor where you can adjust the sengs as needed. The
following are the default sengs:
[Match]
Name=usb0
[Network]
Address=10.0.0.2/24
Gateway=10.0.0.1
Reset the SmartLynq+ Module to update the USB interface.
Chapter 4: USB 3.0 Host Connection
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Chapter 5
Ethernet Connection
By default, the SmartLynq+ Module's Ethernet connecon is congured to use DHCP to obtain
the cable’s IP address. When you connect the cable to a network with a DHCP server, the
module obtains an IP address and shows the value on the display. This value can be used to
connect to the module. If you need to reserve a MAC address for the module you can inspect the
label on the boom of the module for the unique MAC address value.
Changing the Ethernet IP Settings
To change the default factory Ethernet IP sengs you need to rst ssh to the SmartLynq+
Module. You can use the USB 3.0 interface to make the Ethernet changes. When prompted for a
user name and password, enter in the default user name xilinx with the password xilinx.
Aer logging into the SmartLynq+ Module, run the following command to edit the usb network
sengs:
sudoedit /etc/systemd/network/20-eth0.network
This command brings up a Linux nano editor where you can adjust the sengs as needed. The
following are the default sengs:
[Match]
Name=eth0
[Network]
DHCP=ipv4
#Address=10.101.0.101/24
#Gateway=10.101.0.1
To set a stac address, remove the # on Address and Gateway lines and set them as needed
while adding a # at the beginning of the DHCP line. Aer the edits are complete, save the le.
To update the Ethernet interface, reset the SmartLynq+ Module or run the following command:
sudo systemctl restart systemd-networkd
Chapter 5: Ethernet Connection
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Chapter 6
SmartLynq+ Module Display
The SmartLynq+ Module display provides general informaon about the module and allows some
tasks to be performed. The following SL+ menu is the default menu displayed at power up when
no connecons are acve:
The SL+ tab displays the IP address when a connecon is acve:
Use the up and down arrow keys to select dierent tabs. These keys transion from the SL+
(SmartLynq+) tab to the STAT (status) tab and to the INFO (informaon) tab. The drop-down
menu in the STAT tab allows drilling down into various sub menus by pressing the select buon
on the STAT tab. The INFO tab shows soware build informaon.
Chapter 6: SmartLynq+ Module Display
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