
CDR1000
PIN
NO.
NAME I/O FUNCTION
PIN
NO.
NAME I/O FUNCTION
1DI I Input data 23 OW20N I Output format setting*1
2 DI I 24 OW20N I
3 BCKI I Input side bit clock 25 IISN I IIS output mode select
4 BCKI I 26 IISN I H: normal L: IILS
5 LRCI I Input side word clock 27 STATE O
Output which shows internal operation
6 ICLK I Input side system clock input 28 TST1N I Diza ON/OFF select
7 ICKSL I Input side system clock select 29 TST2N I Test
8 IFM1 I Input format setting 30 RSTN I Reset
9 IFM1 I 31 RSTN I
10 IFM2 I 32 VSS - Ground
11 IFM2 I 33 VSS -
12 VDD - Power supply 34 SLAVE I
Mode select of BCKO and LRCO
13 VDD - 35 SLAVE I H: input L: output
14 DMUTE I Mute 36 THRUN I Slue mode setting of DOUT
15 DMUTE I 37 THRUN I
16 MCOM I 17 to 20 pin control select 38 OCKSL I
Output side system clock select
17 MDT/FSI1 I
MCDM H: data input
L: de-emphasis clock select
39 OCLK I
Output side system clock input
18 MCK/FSI2 I
MCDM H: Bit clock of data input
L: de-emphasis clock select
40 LRCO I/O
Output side word clock input/output
19
MLEN/DEEM
I
MCDM H: data word latch clock
41 BCKO I/O
Output side Bit clock input/output
20
MLEN/DEEM
I
L: de-emphasis on/off control
42 BCKO I/O
21 OW18N I Output format setting*1 43 DOUT O Data Out
22 OW18N I 44 DOUT O
*1 IISN: H
Output format OW20N OW18N
16 bit H H
18 bit H L
Stuffs back
LH
20 bit
Stuffs ahead
LL
IISN: L
Output format OW20N OW18N
16 bit H H
18 bit H L
LH
20 bit
IIS MODE
Stuffs ahead
LL
IMF1 IMF2 Word length Data sequence Data position
L L 16 Bit MBS first Stuffs back
L H 20 Bit MSB first Stuffs back
H L 20 Bit MSB first Stuffs ahead
H H 20 Bit LSB first Stuffs back
SM5844AF (XW097A00) Sample Converter
PIN NO.
NAME I/O FUNCTION
PIN NO.
NAME I/O FUNCTION
1 TIOCA3 I/O 41 A18/P52 O Address bus
2 TIOCB3 I/O 42 A19/P53 O
3 TIOCA4 I/O Input capture/output compare 43 P60//WAIT I Wait
4 TIOCB4 I/O 44 MD0 I Mode control
5 TOCXA4 I/O 45 MD1 I
6 TOCXB4 I/O 46 φOSystem clock
7 MD2 I Mode control 47 /STBY I Standby
8 /ADTRG/TP15/PB7
AD conversion external trigger input
48 /RES I Reset
9 TXD0/P90 O Transmit data 49 NMI Non-maskable interrupt
10 RXD0/P92 I Receive data 50 VSS Ground
11 /IRQ4/SCK0/P94 I Interrupt request 51 EXTAL I Crystal oscillator
12 VSS - Ground 52 XTAL I
13 D0/P30 I/O 53 VCC Power supply
14 D1/P31 I/O 54 P63/AS O Address strobe
15 D2/P32 I/O 55 P64/RD O Read
16 D3/P33 I/O Data bus 56 P65/WR O Write
17 D4/P34 I/O 57 /RESO/FWE I/O
Reset output/write enable signal
18 D5/P35 I/O 58 AVSS - Ground
19 D6/P36 I/O 59 P70/AN0 I
20 D7/P37 I/O 60 P71/AN1 I
21 VCC - Power supply 61 P72/AN2 I
22 A0/P10 O 62 P73/AN3 I Analog input
23 A1/P11 O 63 P74/AN4 I
24 A2/P12 O 64 P75/AN5 I
25 A3/P13 O Address bus 65 P76/AN6 I
26 A4/P14 O 66 P77/AN7 I
27 A5/P15 O 67 AVCC - Power supply
28 A6/P16 O 68 P80//IRQ0 I Interrupt request
29 A7/P17 O 69 P81//IRQ1 I
30 VSS - Ground 70 P91/TXD1 O Transmit data
31 A8/P20 O 71 P93/RXD1 I Receive data
32 A9/P21 O 72 P95/SCK1/IRQ5 I Interrupt request
33 A10/P22 O 73 PA0/TP0/TCLKA I
34 A11/P23 O 74 PA1/TP1/TCLKB I Clock input
35 A12/P24 O Address bus 75
PA2/TP2/TIOCA0/TCLKC
I
36 A13/P25 O 76
PA3/TP3/TIOCB0/TCLKD
I
37 A14/P26 O 77 A23 O
38 A15/P27 O 78 A22 O Address bus
39 A16/P50 O 79 A21 O
40 A17/P51 O 80 A20 O
HD64F3039F18 (XW700A00) CPU