Ziatech Corporation ZT 8954 Instructions for use
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SM
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Instra
ZT 8954
Low Profile
Floppy Disk Controller
Hardware User Manual
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2
CONTENTS
MANUAL ORGANIZATION.....................................................................................................................4
1. INTRODUCTION .................................................................................................................................5
PRODUCT DEFINITION .............................................................................................................5
FEATURES.................................................................................................................................5
FUNCTIONAL BLOCKS..............................................................................................................6
STD 32 BUS INTERFACE..............................................................................................6
INTERRUPTS.................................................................................................................7
FLOPPY DISK CONTROLLER .......................................................................................7
FLOPPY DISK DRIVE ....................................................................................................7
EXTERNAL FLOPPY INTERFACE.................................................................................7
2. GETTING STARTED...........................................................................................................................8
UNPACKING...............................................................................................................................8
SYSTEM REQUIREMENTS........................................................................................................8
CPU BOARDS SUPPORTING THE ZT 8954:...........................................................9
CPU BOARDS NOT SUPPORTING THE ZT 8954:...................................................9
PHYSICAL REQUIREMENTS.........................................................................................9
POWER REQUIREMENTS.............................................................................................9
ENVIRONMENTAL REQUIREMENTS..........................................................................10
INSTALLING THE ZT 8954.......................................................................................................10
INTERRUPT SELECTION ............................................................................................10
DMA MODE SELECTION.............................................................................................10
JUMPER REQUIREMENTS - DOS AND STD 32 STAR SYSTEMS..............................11
FRONTPLANE CONNECTORS................................................................................................11
STD 32 COMPLIANCE..............................................................................................................12
3. THEORY OF OPERATION................................................................................................................13
FREQUENTLY ASKED QUESTIONS........................................................................................13
WHY IS THE ZT 8954 IS INCOMPATIBLE WITH OLDER CPU BOARDS?...................13
WHAT FLOPPY DISK DRIVES ARE SUPPORTED BY THE ZT 8954?.........................13
HOW DO I USE FRONTPLANE DMA?.........................................................................13
HOW DO I REMOTE MOUNT A FLOPPY DISK DRIVE?..............................................13
STD BUS COMPATIBILITY.......................................................................................................14
STD BUS INTERFACE..............................................................................................................14
DATA TRANSFERS......................................................................................................14
MEMORY.....................................................................................................................14
I/O................................................................................................................................14
FLOPPY DISK CONTROLLER REGISTERS................................................................15
INTERRUPTS...........................................................................................................................16
ZIATECH STD 32 STAR SYSTEM USE....................................................................................16
STAR SYSTEM FLOPPY RULE ...................................................................................16
4. FDC DESCRIPTION (82078).............................................................................................................17
PERPENDICULAR RECORDING MODE..................................................................................18
STATUS, DATA, AND CONTROL REGISTERS........................................................................18
STATUS REGISTER A (SRA).......................................................................................19
STATUS REGISTER B (SRB).......................................................................................19
TAPE DRIVE REGISTER (TDR)...................................................................................21
DATARATE SELECT REGISTER (DSR) ......................................................................22
MAIN STATUS REGISTER (MSR)................................................................................24
DATA (FIFO) ................................................................................................................25
DIGITAL INPUT REGISTER (DIR)................................................................................26
RESET......................................................................................................................................27
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Contents
3
RESET PIN ..................................................................................................................27
DOR RESET VS. DSR RESET.....................................................................................27
DMA TRANSFERS....................................................................................................................28
COMMAND SET/DESCRIPTIONS............................................................................................28
ADDITIONAL INFORMATION...................................................................................................28
A. JUMPER CONFIGURATIONS ..........................................................................................................29
JUMPER OPTIONS ..................................................................................................................29
JUMPER DESCRIPTIONS........................................................................................................31
W1-2 (DMA MODE SELECTION) .................................................................................31
W3-11 (FLOPPY INTERFACE).....................................................................................32
W12-18 (INTERRUPT SELECTION).............................................................................32
B. SPECIFICATIONS............................................................................................................................33
ELECTRICAL AND ENVIRONMENTAL.....................................................................................33
ABSOLUTE MAXIMUM RATINGS................................................................................33
STORAGE TEMPERATURE ..................................................................................33
OPERATING TEMPERATURE...............................................................................33
DC OPERATING CHARACTERISTICS.........................................................................33
SUPPLY CURRENT, VCC......................................................................................34
NON-CONDENSING RELATIVE HUMIDITY...........................................................34
STD BUS LOADING CHARACTERISTICS ...................................................................34
MECHANICAL...........................................................................................................................37
CARD DIMENSIONS AND WEIGHT.............................................................................37
CONNECTORS............................................................................................................38
STD 32 P/E CONNECTOR.....................................................................................39
J1 (DMA PORT) .....................................................................................................41
J2, J3 (FLOPPY INTERFACE)................................................................................42
J4, J6 (SLIMLINE FLOPPY DISK DRIVE)...............................................................43
J5 (POWER CABLE)..............................................................................................43
CABLES.......................................................................................................................44
C. CUSTOMER SUPPORT....................................................................................................................46
TECHNICAL/SALES ASSISTANCE...........................................................................................46
RELIABILITY.............................................................................................................................46
RETURNING FOR SERVICE....................................................................................................46
ZIATECH WARRANTY..............................................................................................................47
TRADEMARKS.........................................................................................................................47
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4
MANUAL ORGANIZATION
This manual describes the operation and use of the ZT 8954 Low Profile Floppy Disk
Controller. The following outline summarizes the focus of each section in this manual.
Chapter 1, "Introduction," offers an overview of the ZT 8954. It includes a product
definition, a list of product features, a functional block diagram, and a brief description of
each block. This chapter is most useful to those who wish to compare the features of
the ZT 8954 against the needs of a specific application.
Chapter 2, "Getting Started," summarizes the information you need to get your
ZT 8954 operational. This includes system requirements and installation instructions.
Chapter 3, "Theory of Operation," presents an operational view of the ZT 8954's
hardware. Each of the board's functions is described in detail, and some common
concerns are addressed.
Chapter 4, "FDC Description (82078)," defines the 82078 Floppy Disk Controller
(FDC) and describes its functions and capabilities in detail.
Appendix A, "Jumper Configurations," describes all of the ZT 8954 jumpers in detail,
specifies factory default settings, and provides the information you need to tailor your
board to a specific application.
Appendix B, "Specifications," contains the electrical, mechanical, and environmental
specifications.
Appendix C, "Customer Support," offers technical support information, the Ziatech
warranty, and instructions for returning the ZT 8954 if service is necessary.
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5
1. INTRODUCTION
This chapter provides a brief introduction to the ZT 8954 Low Profile Floppy Disk
Controller. It includes a product definition, a list of product features, a functional block
diagram, and a description of each function. You will find unpacking information and
installation instructions in Chapter 2, "Getting Started."
PRODUCT DEFINITION
The ZT 8954 is a Low Profile Floppy Disk Controller for the STD 32 bus structure.
Support is provided for 5¼" and 3½" floppy drives, as well as floppy controller-
compatible tape drive units.
The ZT 8954 is available with an integrated 3½" slimline drive (occupying just one
STD 32 card slot), as a remote mount option with no drive loaded, and with a mounting
bracket to extend the drive out for use in card cages with front bezels (for example, the
ZT 250).
Mechanically, the ZT 8954 is compatible with both the STD and the STD 32 bus
specifications. The ZT 8954 supports 5 and 8 MHz bus operation.
FEATURES
•STD 32 bus compatible
•360K, 720K, 1.2 Mbyte, and 1.44 Mbyte floppy disk drive support
•IBM-PC®/AT®/MCA®/EISA®compatible register set
•3½", 5¼" floppy disk drive support
•Integrated 3½" slimline floppy disk drive (1 slot usage) (ZT 8954-D1)
•Remote mounting option (20") (ZT 8954-D0)
•Tape drive support
•Bracket mounting option for ZT 250/300 card cages (ZT 8954-D1M)
•STD-80 backplane option (ZT 8954-D3)
•Burned in at 55º C and tested to guarantee reliability
•STD 32 compliance:
•I/O Slave: SA8-I, IXL, IXP, SDMA8, SDMABP, EDMAA, EDMAB
•Five-year warranty
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1. Introduction
6
FUNCTIONAL BLOCKS
The "Functional Block Diagram" below illustrates the board's major functional blocks. A
description of the board's features and functional blocks can be found in the following
topics.
ZT 8954
Floppy
Disk
Controller
®
Integrated
Floppy Disk Drive
(5.25", 3.5", or 3.5" Slimline)
Bus Interface
Interrupts
External
Floppy
Interface
Functional Block Diagram
STD 32 Bus Interface
STD bus interface logic decodes the I/O address for cycles destined for the floppy disk
controller. Control of the backplane data bus buffer is also performed in this logic for
both programmed I/O cycles and DMA cycles.
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1. Introduction
7
Interrupts
The Floppy Disk Controller (FDC) communicates status to the host processor via an
interrupt. This interrupt is routed through a group of jumpers to select the appropriate
backplane interrupt to drive. Standard bussed interrupts are supported, as well as the
slot-specific interrupt for STD 32 backplanes. By default, the floppy disk controller drives
INTRQ2* on the backplane, which is normally connected on the host CPU to IR6.
Floppy Disk Controller
The Floppy Disk Controller used on the ZT 8954 supports all DOS-compatible floppy
disk drives through either a 0.1" 34-pin header or a 1-millimeter 26-pin connector. Data
rates of 250 Kbytes, 300 Kbytes, 500 Kbytes, and 1 Mbytes per second are supported
through program control. Perpendicular recording mode is supported for 2.88 Mbyte
floppy disk drives. An on-board 16-byte FIFO provides increased bus-latency tolerance.
The FDC is fully compatible with the IBM-AT, IBM-PS/2®, and EISA architectures. The
FDC supports up to two disk drives directly.
Floppy Disk Drive
The ZT 8954 supports a variety of floppy disk drives. Two types of connectors are
provided for interfacing to the different styles of floppy drives. A 34-pin 0.1" header
interfaces to older style 5¼" and 3½" drives. For newer 3½" slimline drives, a 26-pin
1 mm FPC connector is provided.
External Floppy Interface
The ZT 8954 supports remote mounted floppy drives through an onboard 34-pin 0.1"
header.
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8
2. GETTING STARTED
This chapter discusses features of the ZT 8954 and summarizes the information you
need to get your ZT 8954 operational. Read this chapter and Chapter 3, "Theory of
Operation," before you use the board. Most users will not need to adjust any jumpers for
correct operation.
Many of the topics in "Getting Started" are discussed in greater detail in subsequent
chapters. You will find a number of cross references for topics containing further
information. Many of the details of the floppy disk controller can be found in the Intel
Peripherals Data Book
in the
82078-1
data sheet, also available as a separate Intel
publication 290468-002.
The ZT 8954 is supported by CPU boards that have on-board DMA controllers to
perform the floppy disk data transfer (for example, ZT 8902 Revision A, ZT 8903,
ZT 8904, and ZT 8905). The ZT 8954 is supported in Ziatech DOS and STD 32 STAR
SYSTEMs, starting with BIOS 4.01.
UNPACKING
Be sure to check the shipping carton for damage. If the shipping carton and contents
were damaged, notify the carrier and Ziatech for an insurance settlement. Retain the
original shipping carton and packing material for inspection by the carrier. Save the anti-
static bag for storing or returning the ZT 8954.
Do not return any product to Ziatech without a Return Material Authorization (RMA)
number. The procedure for obtaining an RMA number from Ziatech is explained in the
"Returning for Service" section of Appendix C, "Customer Support."
Caution: Like all equipment utilizing MOS devices, the ZT 8954 must
be protected from static discharge. Never remove any of the socketed
parts except at a static-free workstation. Use the anti-static bag shipped
with the ZT 8954 to handle the board.
SYSTEM REQUIREMENTS
The ZT 8954 is designed for use in STD and STD 32 bus environments. The ZT 8954 is
dependent upon the host CPU's performing DMA cycles to transfer data between the
floppy disk and the host's memory. It is important to note that not all CPU boards have
this capability. In particular, the ZT 8954 is designed for use with the ZT 8902
Revision A, ZT 8903, ZT 8904, and ZT 8905. Use the following lists to determine
whether your Ziatech CPU board supports the ZT 8954.
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2. Getting Started
9
CPU Boards supporting the ZT 8954:
Note: As CPU boards are designed, this list will change. Contact Ziatech for details on
boards not listed here.
•ZT 8902 Revision A
•ZT 8903
•ZT 8904
•ZT 8905
CPU Boards NOT supporting the ZT 8954:
Note: As CPU boards are designed, this list will change. Contact Ziatech for details on
boards not listed here.
•ZT 8801/88CT01
•ZT 8802/88CT02
•ZT 8808/8809/88CT09
•ZT 8816/8817
•ZT 8901/89CT01
•ZT 8902 Revision 0.X
•ZT 8910
•ZT 8911 Revision 0.X (although slot-specific DMA can be used)
Physical Requirements
The ZT 8954-D1 and ZT 8954-D0 require just one STD 32 card cage slot. The
maximum board height, including the floppy disk drive, is 0.5". Note that boards placed
to the left of the ZT 8954 should be chosen with care so that they do not exceed the
maximum height limit. Should this happen, select another board to install next to the
ZT 8954. Note that the top of the floppy disk drive is shielded to protect against shorting
adjacent boards.
The ZT 8954-D3 requires three STD card slots. Refer to the "Card Dimensions and
Weight" section of Appendix B, "Specifications," for exact dimensions of the ZT 8954.
Power Requirements
Power required by the ZT 8954 depends upon the type of drive loaded on the controller.
Consult Appendix B, "Specifications," for details. In general, the ZT 8954 and drives
shipped with it do not require +12 V. Only +5 V is required for the complete assembly.
Some older drives do use +12 V, and they can be powered through the ZT 8954 via the
J5 power connector.
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2. Getting Started
10
Environmental Requirements
Ziatech recommends vertical mounting for applications in which a fan is not used.
Horizontal mounting requires a minimum air flow of 30 cubic feet/minute passing over
the surface of the board.
INSTALLING THE ZT 8954
If the ZT 8954 is purchased as part of a system, then the system-specific jumpers will
already have been installed at the factory. In general, you should not need to change
the jumpers on the ZT 8954. The ZT 8954 is, by default, set up to drive INTRQ2* (P50)
on the STD 32 backplane, and will use Mode 2 DMA (BUSRQ*/BUSAK*, backplane
control signals) for DOS applications. The default jumper configuration for Ziatech CPU
boards also reflects this configuration.
If the ZT 8954 is purchased as a stand-alone control (for remote mounting of the floppy
drive), then you may need to change the floppy interface jumpers to meet the particular
requirements of the floppy disk drive you are using. In particular, older 5¼" drives have
an inverted DENSEL* signal when compared to the 3½" drives. Jumpers W6 and W7 let
you select the sense of this signal. By default, W7 is in; this selects the proper logic
level for DENSEL* for 3½" drives. Refer to the description of W7 in Appendix A,
"Jumper Configurations," for details.
Interrupt Selection
Jumpers W12-18 select the backplane pin to which the floppy disk controller interrupt
will be driven. By default, INTRQ2* (backplane pin P50) is used for floppy disk
subsystem interrupts. Other backplane interrupts, as well as STD 32 slot-specific
interrupts, can be selected if the default is not acceptable. The slot-specific interrupt is
configurable for either active low (IXL) or positive edge (IXP).
DMA Mode Selection
The ZT 8954 uses four different modes for floppy DMA transfers (Modes 0-3). The
primary mode of operation is Mode 2, which uses the BUSRQ*/BUSAK* signals for bus
arbitration and uses the backplane control signals (DMAIOW*, DMAIOR*, and T-C) for
the data transfer. Slot-specific DMA and frontplane DMA can also be selected
depending upon the capabilities of the host CPU board. Jumpers W1 and W2 select the
DMA Mode for the ZT 8954.
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2. Getting Started
11
Jumper Requirements - DOS and STD 32 STAR SYSTEMs
Installed:
W2,W4,W5,W7,W9, W10,W16
Not installed:
W1,W3,W6,W8,W11-15,W17,W18
This configuration selects DMA Mode 2, drives INTRQ2* with the floppy disk interrupt,
and sets up the floppy disk drive interface for 3½" drives.
Refer to Appendix A, "Jumper Configurations," for details.
FRONTPLANE CONNECTORS
As shown in the "Connector Locations" drawing, the ZT 8954 includes six frontplane
connectors to interface to application-specific devices. A brief description of each
connector is given below in the "Frontplane Connector Assignments" table. For more
information, see the "Connectors" topic in Appendix B.
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2. Getting Started
12
Frontplane Connector Assignments
Connector Function
J1 J1 provides Direct Memory Access (DMA) support for external
peripherals via channel 0 or 3 on the local 8237A DMA controller. The
floppy disk controller can use this connector to request service from the
DMA controller on the ZT 8954. This connector is not normally loaded
on the ZT 8954, as it resides under the integrated floppy drive.
J2, J3 J2 and J3 accommodate 0.1" 34-pin floppy interface drives. J3 is a
reverse image of J2 to allow interfacing to drives with minimal cable
twisting.
J4, J6 J4 and J6 are 1 mm FPC cable connectors for newer slimline floppy disk
drives. J4 is not loaded by default as it is underneath the integrated
floppy drive.
J5 J5 is for a power cable connection location for remote floppy disk drives.
STD 32 COMPLIANCE
STD 32 peripherals are required to meet certain compliance standards. This allows the
system integrator to match capabilities among different manufacturers' boards.
STD 32 peripherals are available from a variety of manufacturers.
The ZT 8954 has the following STD 32 compliance:
I/O Slave: SA8 - I, IXP, IXL, SDMA8, SDMABP, EDMAA, EDMAB
Definitions
SA8 Standard Architecture 8-bit transfers
I Can drive INTRQ*, INTRQ1*, INTRQ2*, and/or INTRQ3*
IXP Can drive IRQx with a positive active edge
IXL Can drive IRQx with an active low request
SDMA8 Supports frontplane 8-bit DMA transfers
SDMABP Supports Standard Architecture backplane DMA by BUSRQ*/BUSAK*
EDMAA Extended Architecture type A DMA transfers supported
EDMAB Extended Architecture type B DMA transfers supported
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13
3. THEORY OF OPERATION
This chapter presents an operational overview of the hardware operation of the
ZT 8954. Each of the board's functions is described in detail. Frequently asked
questions are addressed below.
FREQUENTLY ASKED QUESTIONS
Why is the ZT 8954 Incompatible With Older CPU Boards?
The ZT 8954 relies upon the host CPU to perform DMA transfers between the floppy
disk controller and the host CPU's memory. Only boards that can field requests from a
DMA slave (for example, ZT 8902) can be used with the ZT 8954. Many older CPU
boards do not have on-board DMA controllers or do not allow for off-board DMA slaves.
With STD 32, DMA capability was added by defining the backplane signals necessary
for data transfer completion under DMA. The ZT 8954 is not supported by the ZT 8801,
ZT 8802, ZT 8808, ZT 8809, ZT 8816, ZT 8817, ZT 8901, ZT 8902 Revision 0.X, or
ZT 8911 Revision 0.X.
What Floppy Disk Drives are Supported by the ZT 8954?
The ZT 8954 supports all floppy disk drives that are compatible with the IBM-PC family.
Data transfer rates of 250 Kbps through 2 Mbps are supported. In addition, the ZT 8954
supports tape drive units that are floppy interface compatible, such as the Colorado
Memory Systems "JUMBO" tape drives.
How Do I Use Frontplane DMA?
The ZT 8954 is capable of frontplane DMA, but only as a special option from Ziatech
(ZT 8954-D3). The connector location for frontplane DMA is located underneath the
integrated 3½" drive. In order to minimize slot usage by the floppy subsystem, this
connector is not loaded. Frontplane DMA is primarily used for floppy operation in STD-
80 card cages that have no backplane DMA capability. When the frontplane DMA
connector is loaded, the floppy disk drive must be raised; this causes the complete
ZT 8954/Floppy Disk Drive to occupy two card slots.
How Do I Remote Mount A Floppy Disk Drive?
Floppy Disk Drives can be remote mounted with a ZT 8954-D0 board and the addition
of two cables, ZT 90077 and ZT 90172. These cables allow for interfacing drives up to
20" away from the controller. These cables support 3½" and 5¼" drives with separate
power connectors and drives that use the older style .050" ribbon cable for floppy drive
control (34-pin 0.1" connectors). The micro-floppy 3½" drives that use FPC cable are
not supported by this mechanism. These drives can be interfaced with a 26-pin FPC
cable on 1 millimeter pitch at up to 0.5 meters or less. Parlex company (telephone
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3. Theory of Operation
14
[603] 893-0040) manufactures custom length cables for these drives for your
application. When interfacing to remote drives, minimize the amount of electrical noise
in the system to avoid corrupting the data transfer between the floppy disk drive and the
floppy disk controller.
STD BUS COMPATIBILITY
The ZT 8954 is fully compatible with both the STD-80 and STD 32 bus specifications.
STD 32 is a superset of STD-80. Both specifications are available through Ziatech.
STD BUS INTERFACE
The ZT 8954 interfaces the STD and STD 32 bus structure to IBM-PC platform floppy
disk controllers. Programmed I/O transfers are used to program the ZT 8954 for a floppy
disk sector read or write. DMA is used for the transfer of floppy disk data. DMA can be
done a byte at a time (which is the IBM PC method); or, with the on-board 16-byte
FIFO, the ZT 8954 can perform block DMA in order to improve bus-latency tolerance.
Under MS-DOS, floppy disk transfers also require the use of an interrupt, which is
nominally jumpered for INTRQ2* on the backplane. The ZT 8954 uses
BUSRQ*/BUSAK* and backplane DMA control signals, by default, for data transfers.
Data Transfers
The floppy disk controller supports both polled and DMA-driven data transfers. Standard
MS-DOS uses DMA, by default, for moving data back and forth between the host CPU's
memory and the floppy disk controller. The DMA transfer is driven by the DMA controller
on board the host CPU board. The ZT 8954 does not have a controller. The BIOS
software is responsible for managing the low-level hardware in DOS systems and in
STD 32 STAR SYSTEM™ multiprocessing applications. All transfers are 8 bits wide.
The normal DMA transfer mechanism is to use BUSRQ* to request a DMA cycle, qualify
DMAIOW* or DMAIOR* with BUSAK* to transfer data, and receive T-C as a terminal
count signal from the host CPU. This is referred to as Mode 2 DMA for the ZT 8954.
Slot-specific DMA, frontplane DMA, and a combination of frontplane and backplane
DMA can also be selected as other modes.
Memory
The ZT 8954 does not occupy or decode any of the STD bus memory address space.
I/O
The ZT 8954 decodes the I/O address range 3F0h-3F7h, with the exception of 3F6h.
Port 3F7h is shared with the hard disk interface (ZT 8952/8953); only one bit is driven
by the ZT 8954 when that port is read by the host CPU. The other seven bits are driven
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3. Theory of Operation
15
by the ZT 8952/8953. The ZT 8954 is not jumper selectable for any alternate I/O
address. The I/O map is shown below in the "I/O Map" figure.
†
3F7h is shared with the ZT 8952/53.
3F7h†
3F6h
3F5h
3F0h
Not Decoded
I/O Map
Floppy Disk Controller Registers
The Floppy Disk Controller (FDC) interface is composed of eight registers. The "Floppy
Disk Controller I/O Registers" table defines the I/O address for all of the FDC registers.
These registers are further described in Chapter 4, "FDC Description (82078)."
Floppy Disk Controller I/O Registers
I/O Port Address I/O Read Function I/O Write Function
3F0h Status Register A --
3F1h Status Register B Status Register B
3F2h Digital Output Register Digital Output Register
3F3h Tape Drive Register Tape Drive Register
3F4h Main Status Register Data Rate Select Register
3F5h Data Data
3F6h Reserved Reserved
3F7h Digital Input Register†Configuration Control Register
†Bit 7 only driven
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3. Theory of Operation
16
INTERRUPTS
The ZT 8954 can drive any of the bussed backplane interrupts, as well as the slot-
specific interrupt IRQx. By default, the ZT 8954 is jumpered for driving INTRQ2*
(backplane pin P50) for the floppy disk subsystem interrupt.
The "Interrupt Selections" illustration below indicates the possible interrupt selections.
†W16 is installed by default.
Floppy
Disk
Controller
IRQx
INTRQ*
INTRQ1*
INTRQ2*
INTRQ3*
INTRQ4*
(E47)
(P44)
(P37)
(P50)
(E67)
(P5)
126
W12
W13
W14
W15
W16
W17
W18
†
Interrupt Selections
ZIATECH STD 32 STAR SYSTEM USE
In multiprocessing operations, the floppy disk interface is shared between CPUs in the
backplane. Because different CPU boards are supported by different floppy disk
interfaces, the STD 32 STAR SYSTEM allows for different CPU board types. When a
system is composed of different CPU types, a simple rule is applied, as detailed in the
following topic, "STAR SYSTEM Floppy Rule".
STAR SYSTEM Floppy Rule
Always match the floppy disk controller to the Permanent Master type. For instance, if
the ZT 8902 Rev A is your Permanent Master, the ZT 8954 is required. The STAR BIOS
will manage transfers between Temporary Masters and the floppy disk through the
Permanent Master.
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17
4. FDC DESCRIPTION (82078)
The 82078 is a true single-chip floppy disk controller for IBM PC/AT and PS/2
architectures. The integrated analog data separator needs no external compensation,
yet allows for a wide motor speed variation with exceptionally low soft error rates. The
microprocessor interface has 100% hardware register compatibility for PC/ATs and
PS/2s. The 16-byte FIFO with programmable thresholds is extremely useful in multiple
master systems or systems with a large amount of bus latency.
The following "82078 Block Diagram" below shows a block diagram of the 82078 floppy
disk controller.
PRECOMP
SERIAL
INTERFACE
LOGIC
WRITE CLK
GENERATOR
FLOPPY
DISK
DRIVE
INTERFACE
LOGIC
HOST
INTER-
FACE
LOGIC
INTERNAL OSC.
DATA RATE
SELECTION
POWER
MANAGEMENT
LOGIC
INPUT
OUTPUT
WRDATA
WE
MEDID0:1
PD
X [1:2]
IDENT0
IDLE
INTERNAL BUS
SRA
SRB
DOR
TDR
MSR
DSR
FIFO
DIR
CCR DATA
SEPARATOR
MICRO-
CONTROLLER
DRVID0:1
DSKCHG
DRV2
WP
TRK0
INDX
DIR
STEP
HDSEL
DENSEL
DS [0:3]
ME [0:3]
IDENT1
VCCF
SEL3V#
RD#
WR#
A[0:2]
DACK#
DRQ
INT
TC
CS#
RESET
DB[0:7]
82078 Block Diagram
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4. FDC Description (82078)
18
PERPENDICULAR RECORDING MODE
An added capability of the 82078 is the ability to interface directly to perpendicular
recording floppy drives that use the Toshiba format. Perpendicular recording differs from
the traditional longitudinal method by orienting the magnetic bits vertically. This scheme
then packs in more data bits for the same area.
The 82078 with perpendicular recording drives can, at a minimum, read standard 3½"
floppies as well as read and write perpendicular media. Some manufacturers offer
drives that can read and write standard and perpendicular media in a perpendicular
media drive. A single command puts the 82078 into perpendicular mode. All other
commands operate as they normally do. The perpendicular mode requires the 1 Mbps
data rate of the 82078. At this data rate, the FIFO eases the host interface bottleneck
due to the speed of data transfer to or from the disk, if utilized.
STATUS, DATA, AND CONTROL REGISTERS
The following topics discuss the status, data, and control registers of the 82078 FDC.
The base address range is supplied via the CS* pin. For PC-compatible designs, this is
3F0h to 3F7h. The following "82078 Register Summary" table summarizes addressing
for the status, data, and control registers.
82078 Register Summary
A2 A1 A0 Register
000SRA - Status Register A
001SRB - Status Register B
010DOR - Digital Output Register
011TDR - Reserved (Tape Drive Register)
100MSR - Main Status Register
100DSR - Datarate Select Register
101FIFO - Data (FIFO)
1 1 0 Reserved (Not decoded)
111DIR - Digital Input Register (Read)
111CCR - Configuration Control Register (Write)
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4. FDC Description (82078)
19
Status Register A (SRA)
3F0h Default
This register is read-only and monitors the state of the interrupt pin and several disk
interface pins. This register is part of the PS/2 register set.
76543 210
INT
PENDING DRV2* STEP TRK0* HDSEL INDX* WP* DIR
Status Register A
The INT PENDING bit is used by software to monitor the state of the 82078
INTERRUPT pin. As a read-only register, no default value is associated with a reset
other than that some drive bits change with a reset. The INT PENDING, STEP, HDSEL,
and DIR bits are low after reset.
Status Register B (SRB)
3F1h Default
This register is read-only and monitors the state of several disk interface pins. This
register is part of the PS/2 register set.
76543 210
DRIVE
SEL0
1MOT
WE
WRDATA
TOGGLE RDDATA
TOGGLE
1EN1 MOT
EN0
Status Register B
As the only drive input, RDDATA TOGGLE's level always reflects the level as seen on
the cable.
The two TOGGLE bits do not read back the state of their respective pins directly.
Instead, the pins drive a flip-flop which produces a wider and more reliably read pulse.
Bits 6 and 7 are undefined and always return a 1.
After any reset, the activity on the TOGGLE pins is cleared. Drive select and motor
bits are cleared by the RESET pin and not by software resets.
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