ZoBoVison E50I Altera C5 User manual

Focus On FPGA/SOC Video IP
ZoBoVison H.265 Encoder FPGA IP
Altera CycloneV
Terasic(友晶) SocKit FPGA board
Live Demo
User Guide
www.zobovision.com
Shen Zhen, CHINA Document Data: Aug 2015
深圳市中博视清科技开发有限公司 Document Version: V3.0
ser[email protected]
[email protected]

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Release Information
Item Description
Version V3.01
Name zobo_Enc_Altera_C5_SocKit_Demo
Revision Data Aug 20th, 2015
FPGA IP Support E50I_Altera_C5
E51P_Altera_C5
Introducation
The document describes the method of ZoBoVision E50I_Altera_C5 and
E50P_Altera_C5 H.265/HEVC encoder demo on Terasic SocKit FPGA board (Altera
CycloneV Series).
To execute the demo, please boot the linux from microSD card in SocKit board and
copy the execution file “zoboenc” and the source YUV file to Linux directory. Use Quartus
Programmer to configure FPGA with .sof or .jic file. Then, launch the ARM program
“./zoboenc” to copy the source YUV frames to be loop encoded from microSD card to
FPGA DDR3 memory, once the source frames ready on FPGA DDR3, the FPGA program
start to encoding process and wirte output bitstream to microSD card. Also the original
encode frames or reconstructed frames which is the same as the decoder output will
present on VGA port.

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Limitation
There are some limitations for demo:
■The maximum number of source YUV frames to be loop encoded is limited
according to the encode frame size.
■Four different encode frame size supported for demo :
1920*1080/1280*720/832*480/704/576
■Five different quant parameter supported:
20/24/28/32/36
■The GOP size is limited to 100 when p_frame exist.
■The maximum file sizes of encoder output bitstream is limited to 128 Mbyte.
Demo File
You can download the demo support files package from our website:
www.zobovision.com
The demo files package including:
ZoBoVision_E50I_Altera_C5_Demo_SocKit.sof
ZoBoVision_E50I_Altera_C5_Demo_SocKit.jic
ZoBoVision_E51P_Altera_C5_Demo_SocKit.sof
ZoBoVision_E51P_Altera_C5_Demo_SocKit.jic
zoboenc_linux.rar
VLC_Media_Player.rar
SoCKit_Getting_Started_Guide.pdf
My_First_HPS.pdf

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1. Hardware Requirement
■ Altera cycloneV development board: Terasic SocKit .
■ Development board can be purchased from Terasic website:
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=China&CategoryNo=203&No=832
■ MicroSD: min 8GB
■ VGA monitor (min. 1440*900)
■ Ethernet Router and RJ45 Ethernet cable
■ PC or laptop with Microsoft Windows

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2. Software Requirement
■ Quartus II Programmer
■ Altera Soc EDS (Embedded Design Suite)
■ PuTTY
■ Virtual COM driver installed
■ A bootable SD card with Linux system
3. Execute the Demo
3.1 Development Board Setup
Please check the position of the switches and headers on the SocKit board Before
moving on:
■ J17~J19 BOOTSEL [2:0] = 101
■ SW6 MSEL[4:0] = 10010
■ SW4.1=0 and SW4.2=0

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Figure. SocKit board BOOTSEL and CLKSEL
Figure. SocKit board FPGA MSEL

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Figure. SocKit board JTAG_EN
3.2 Create SD Card Linux Image
■For details about creating a microSD Card Linux Image, please refer to the
document:
SoCKit_Getting_Started_Guide.pdf
■NOTE: MicroSD Card: 8GB min.
■NOTE: SocKit_SD.img (errors may occurs for other image)

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3.3 Setup UART Terminal
■For details about setup UART terminal, please refer to the document:
SoCKit_Getting_Started_Guide.pdf
■USB to UART drivers installed.
■PuTTY installed.
■Uart Baud Rate: 57600 ( the baud rate is related to the linux image version)
3.4 Copy EXE file to SD Linux
■For details about copying files to SD Linux directory, please refer to the document:
My_First_HPS.pdf
■In Altera SoC command shell, Copy the executable file “zoboenc” into the SD Linux
folder “/home/root”.
■NOTE: Before the file “zoboenc” can be executed, you need to change the file
permission by running the command “chmod 777 zoboenc” as shown below:

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3.5 Download SOF or JIC file into FPGA Board
■For details about downloading an .sof or .jic file into SocKit FPGA board , please refer
to the document:
SoCKit_Getting_Started_Guide.pdf
■ZoBoVision_E50I_Altera_C5_SocKit.sof and ZoBoVision_E50I_Altera_C5_SocKit.jic
is used for E50I_Altera_C5 FPGA IP Demo.
■ZoBoVision_E50P_Altera_C5_SocKit.sof and
ZoBoVision_E50P_Altera_C5_SocKit.jic is used for E50P_Altera_C5 FPGA IP Demo.
3.4 Copy YUV file to SD Linux
■For details about copying files to SD Linux directory, please refer to the document:
My_First_HPS.pdf
■In Altera SoC command shell, Copy the YUV file into the SD Linux folder
“/home/root”.
■Only standard YUV420 format file supported, such as the H.265/HEVC YUV test
sequence “BasketballDrill_832x480_50.yuv” and “BQMall_832x480_60.yuv”, etc.
■Only four kinds frame size supported for demo, as shown below:
1920 ×1080
1280 ×720
832 ×480
704 ×576

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■The YUV file under the SD Linux folder “/home/root” should be named according to
the frame size , as shown below:
yuv420_1920_1080.yuv / yuv420_1920_1080_oth.yuv
yuv420_1280_720.yuv / yuv420_1280_720_oth.yuv
yuv420_832_480.yuv / yuv420_832_480_oth.yuv
yuv420_704_576.yuv / yuv420_704_576_oth.yuv
For example, if encoder frame size is set to 1920×1080，and the switch ‘H_SW0’ on
the fpga board is set to ‘0’, the file ‘yuv420_1920_1080.yuv’ will be used as the source
of the encoder. if ‘H_SW0’ set to ‘1’, ‘yuv420_1920_1080_oth.yuv’ will be used.
■Maximum number of the frames to be encoded is limited according to the frame size ,
as shown below:
1920 × 1080: 70 frames
1280 × 720: 180 frames
832 × 480: 440 frames
704 × 576: 420 frames
The frames beyond the max number limitation in the YUV file will be discard, and the
valid frames will be loop encoded frame by frame.
3.5 Start Demo
■Insert the microSD Card with the pre-built linux image into fpga board, and the
YUV420 file to be encoded and the executable file “zoboenc” should have been copied
into the SD Linux folder “/home/root”.
■Connect the USB cable to the USB Blaster II connector (J2) on the SocKit board and
host PC ( if necessary).