4DSP FMC230 User manual

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FMC230
User Manual
4DSP, USA
www.4dsp.com/forum
This document is the property of 4DSP LLC. and may not be copied nor communicated to a
third party without the written permission of 4DSP LLC.
© 4DSP LLC 2015

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Revision History
Date
Description
Revision
2012-12-19
Release
1.0
2013-02-05
Corrected pin assignments in Appendix A
1.1
2013-03-22
Updated analog output range in Table 2 and added a
FMC700 requirement information for KC705
1.2
2013-08-15
Updated analog output bandwidth in Table 2. Added a
signal description in Appendix A.
1.3
2014-01-30
Removed incorrect reference to analog input gain and
over range in Chapter 2
1.4
2014-04-07
Revised some descriptions and fixed typos. Changed
external reference input characteristics.
1.5
2014-05-30
Corrected analog output power range in Table 2
1.6
2014-07-03
Added DACx_SYNC signals in Appendix A
1.7
2014-10-02
Updated external reference input characteristics
1.8
2015-02-27
Clarified external clock frequency range
1.9
2015-06-22
Updated analog output and external sample clock input
characteristics
1.10
2015-09-30
Updated Figure 4: Wideband balun output option, to
reflect board schematic, added section 4.4.1.
1.11

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Table of Contents
1Acronyms and related documents ................................................................................4
1.1 Acronyms...................................................................................................................4
1.2 Related Documents....................................................................................................4
2General description........................................................................................................5
3Installation ......................................................................................................................5
3.1 Requirements and handling instructions.....................................................................5
4Design .............................................................................................................................6
4.1 Physical specifications ...............................................................................................6
4.1.1 Board Dimensions...............................................................................................6
4.1.2 Front panel..........................................................................................................6
4.2 Electrical specifications..............................................................................................6
4.2.1 EEPROM ............................................................................................................6
4.2.1 FMC Connector...................................................................................................6
4.2.1 JTAG...................................................................................................................7
4.3 Main characteristics....................................................................................................7
4.4 Analog output channels..............................................................................................9
4.4.1 Analog output phase...........................................................................................9
4.5 External trigger input..................................................................................................9
4.6 External clock input....................................................................................................9
4.7 External reference input...........................................................................................10
4.8 External clock output................................................................................................10
4.9 Clock tree.................................................................................................................10
4.9.1 PLL design........................................................................................................11
4.10 Power supply........................................................................................................12
5Controlling the FMC230................................................................................................13
5.1 Architecture..............................................................................................................13
5.2 SPI Programming.....................................................................................................15
6Environment..................................................................................................................17
6.1 Temperature ............................................................................................................17
6.2 Monitoring................................................................................................................17
6.3 Cooling.....................................................................................................................18
6.3.1 Convection cooling............................................................................................18
6.3.2 Conduction cooling............................................................................................18
7Safety.............................................................................................................................18
8EMC ...............................................................................................................................18
9Ordering information....................................................................................................19
10 Warranty........................................................................................................................19
Appendix A LPC / HPC pin-out........................................................................................20
Appendix B CPLD Register map.....................................................................................23

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1 Acronyms and related documents
1.1 Acronyms
ADC
Analog-to-Digital Converter
DDR
Double Data Rate
DSP
Digital Signal Processing
EPROM
Erasable Programmable Read-Only Memory
FBGA
Fineline Ball Grid Array
FMC
FPGA Mezzanine Card
FPGA
Field Programmable Gate Array
JTAG
Join Test Action Group
LED
Light Emitting Diode
LVTTL
Low Voltage Transistor Logic level
LSB
Least Significant Bit(s)
LVDS
Low Voltage Differential Signaling
MGT
Multi-Gigabit Transceiver
MSB
Most Significant Bit(s)
PCB
Printed Circuit Board
PCI
Peripheral Component Interconnect
PCIe
PCI Express
PLL
Phase-Locked Loop
PMC
PCI Mezzanine Card
PSSR
Power Supply Rejection Ratio
QDR
Quadruple Data rate
SDRAM
Synchronous Dynamic Random Access memory
SRAM
Synchronous Random Access memory
TTL
Transistor Logic level
XMC
PCIe Mezzanine card
Table 1: Glossary
1.2 Related Documents
FPGA Mezzanine Card (FMC) standard ANSI/VITA 57.1-2010
Datasheet AD9129, Rev C, Analog Devices
Datasheet AD9517 Rev A, Analog Devices
Datasheet AD7291 Rev B, Analog Devices
FMC700 User Manual, 4DSP

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2 General description
The FMC230 is a two channel DAC FMC daughter card. The card provides two 14-bit up to
5.7 GSPS DAC channels which can be clocked by an internal clock source (optionally locked
to an external reference) or an externally supplied sample clock. There is one trigger input for
customized sampling control. The FMC daughter card is mechanically and electrically
compliant to FMC standard (ANSI/VITA 57.1). The FMC has a high-pin count connector, front
panel I/O, and can be used in a conduction-cooled environment.
The design is based on Analog Devices AD9129 single-channel 14-bit 5.7 GSPS DAC with
DDR LVDS inputs. The analog output signals are AC-coupled and connect to MMCX coax
connectors on the front panel.
The FMC allows flexible control of sampling frequency through serial communication busses.
Furthermore, the card is equipped with power supply and temperature monitoring, and it offers
several power-down modes to switch off unused functions or protect the card from
overheating.
Sample Clock
Trigger
FMC Connector
HPC 400 Pins
Clock Tree Status & Control
Clock
Clock Output
Monitoring
DAC A AD9129
single channel
14-bit, 5.7 GSPS Status & Control
DDR LVDS
AD9129
single channel
14-bit, 5.7 GSPS
DAC B Status & Control
DDR LVDS
Ref Clock
Figure 1: FMC230 block diagram
3 Installation
3.1 Requirements and handling instructions
Prevent electrostatic discharges by observing ESD precautions when handling the card.
Do not flex the card.
The FMC daughter card must be installed on a carrier card compliant to the FMC standard.
The FMC carrier card must support the high-pin count connector (400-pins) to support all
channels. A low-pin count connector is supported but may result in limited features.
The FMC carrier card may support a VADJ/VIO_B voltage of +1.2V to +3.3V.
The FMC700 is required in order to use the FMC230 on KC705.

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4 Design
4.1 Physical specifications
4.1.1 Board Dimensions
The FMC card complies with the FMC standard known as ANSI/VITA 57.1. The card is a
single-width, conduction-cooled mezzanine module (with region 1 and front panel I/O). There
may be a mechanical conflict with the front rib on a carrier card. The stacking height is 10mm,
and the PCB thickness is 1.6mm.
4.1.2 Front panel
There are six MMCX connectors available from the front panel. From top to bottom:
- Analog outputs B (D1) and A (D0)
- Trigger in (TR)
- Clock Input (CI)
- Reference Input (RI)
- Clock Output (CO)
A3
A2
A1
A0
D1
D0
TR
CI
RI
CO
Figure 2: Front panel layout
4.2 Electrical specifications
The DAC devices use DDR LVDS signals mapped to the regular FMC pins. Each channel has
two 14-bit wide DDR LVDS busses.
Control signals operate in LVCMOS mode. A VADJ range of 1.2V to 3.3V is supported. The
voltage on VIO_B pins will follow the voltage on VADJ.
The CLKx pins are required to be LVDS by the FMC standard. CLK2 and CLK3 are not used
for best compatibility with Xilinx development platforms. CLK0 is connected to a spare clock
output of the clock tree. CLK1 is connected to the external trigger.
4.2.1 EEPROM
The FMC card has a small serial EEPROM (M24C02) which is accessible from the carrier card
through the I2C bus. The EEPROM is powered by 3P3VAUX. The standby current is only
0.01µA when SCL and SDA are kept at 3P3VAUX level. These signals may also be left
floating since pull-up resistors are present on the FMC. The EEPROM is write-protected by
default.
4.2.1 FMC Connector

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FMC Top Connector
The top connector is the main connector to the FMC carrier board. The pin-out is defined in
the appendix. The connector is a HPC connector.
FMC Bottom Connector
The high-pin count connector enables FMC card stacking. The following connections are
available between the top and bottom FMC connector:
Unused gigabit data signals (DP[4..9]_M2C_P/N, DP[0..9]_C2M_P/N)
All gigabit reference clocks (GBTCLK[0..1]_M2C_P/N)
RES0
3P3VAUX, 3P3V, 12P0V, VADJ
JTAG (see section 4.2.1)
The bottom connector is not mounted by default.
4.2.1 JTAG
In a stacked environment, the TDI pin will be decoupled from the TDO pin by the
PRST_M2C_L signal coming from the bottom connector. TRST#, TCK, TMS, TDI, and TDO
are directly connected between top to bottom connector.
TDI TDO
TDI TDO PRSNT_M2C_L
PRSNT_M2C_L
Top connector (to FMC carrier)
Bottom connector (to stacked FMC)
3P3V
OE
TMS
TMS
TCK
TCK
TRST#
TRST#
CPLD
Figure 3: JTAG Connection
4.3 Main characteristics
Analog outputs
Number of channels
2
Channel resolution
14-bit
Output voltage range
1.12 Vpp (5 dBm)
Output impedance
50Ω (optimized output impedance for mixed-mode operation)

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Analogue output bandwidth
1.4GHz, please refer to AD9129 datasheet for details
External sampling clock input
Input Level
-10dBm < Clock In Level < 10dBm
0dBm typical (LVTTL level supported1)
Input impedance
50Ω
Input range
4.5 MHz to 2850 MHz 2
External reference clock input
Serial numbers FMC230-0000 to FMC230-0186
Input Level
LVTTL: 3.6 > VIH > 2.0V, -0.3 < VIL < 0.8V
Input impedance
50Ω(DC-coupled)
Input range
0MHz to 250MHz
Serial numbers FMC230-0187 and above
Input Level
LVTTL: 3.6 > VIH > 2.0V, -0.3 < VIL < 0.8V
Input is DC-coupled and self-biased to 1.5V, refer to 4.7
Input impedance
5KΩ
Input range
0MHz to 250MHz
External clock output
Output Level
800mVp-p into 50Ω typical
(LVCMOS output available as build option, contact 4DSP)
External Trigger input
Format
LVTLL/LVCMOS33
Logic ‘0’ max 0.8V / Logic ‘1’ min 2.0V
Frequency range
Up to 300 MHz
Internal sampling clock
Format
LVPECL
Frequency Range
DAC: up to 5300MHz (Software selectable, contact 4DSP for
frequencies higher frequencies up to 5700MHz)
Table 2 : FMC daughter card main characteristics
1
3.3V LVTTL into 50Ohm would result in 14dBm, a 1A Schottky diode in the clock input circuit protects
the clock input from overvoltage when driving the input with a LVTTL signal.
2
AD9517 device does support up to 2850MHz with a clock input level of 0dB and higher.

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4.4 Analog output channels
The DAC output circuit is constructed such that different build options are available. The
default configuration is a wideband balun ETC1-1-13 (MACOM; 4.5 to 3000MHz) as shown in
Figure 4. This configuration is the recommended output circuit for mixed-mode operation of the
DAC, for details refer to the AD9129 datasheet.. Please contact 4DSP for custom
configurations.
4.4.1 Analog output phase
While not intuitively obvious from the representative schematic below, the analog output
voltage tracks the data written to the DAC. The analog output signal at its maximum when the
DAC is set to full scale.
As shown in the schematic, the analog output connector X8 is directly connected to the DACs
IOUTN (labeled DAC1_IN) signal thru the balun T4, this results in the output voltage tracking
the voltage on the IOUTN pin.
From the perspective of the output connector and IOUTN, the analog output is formed by a
voltage divider consisting of the high side pulled up to +1.8V by R89 and L13, and the low side
pulled down to -1.5V by the DACs programmable current source.
When 0x0000 is written to the DAC, IOUTN will be sourcing its maximum current thru the
pullups resulting in a negative output voltage.
When the full scale value is written to the DAC, the current thru IOUTN and the pullups will be
at its minimum resulting in the maximum positive voltage on the output.
The complementary output signal IOUTP performs in a similar manner except that it is 180
degrees out of phase with the value written to the DAC, The IOUTP and IOUTN signals are
combined by the transformer action of the balun T4.
Figure 4: Wideband balun output option
4.5 External trigger input
An external trigger is available on the front panel (MMCX connector). The trigger signal
connects to a buffer (NB6N11S) before being sent to the carrier card. The buffer translates the
external LVTTL signal to LVDS and connects to the FMC connector. The trigger input is
terminated to ground with 4.7kΩ.
4.6 External clock input
There is one MMCX clock input on the front panel that can serve as sampling clock input.
Refer also to section 4.9 for more information about the clock tree.

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Note: When internal clock is enabled and there is no need for an external reference, it is
highly recommended to leave the clock input unconnected to prevent interference with
the internal clock.
4.7 External reference input
There is one MMCX reference input on the front panel that can serve as reference clock input.
Refer also to section 4.9 for more information about the clock tree.
Note: When internal clock is enabled and there is no need for an external reference, it is
highly recommended to terminate the reference input with 50Ωto ground, to prevent
interference with the internal clock.
The external reference input connects to the single ended, high-impedance, REF2 input of the
AD9517 clock generator. The input is DC-coupled to support reference frequencies below
20MHz. The AD9517 has got an internal self-bias voltage of 1.5V. The single ended input
characteristics of the clock generator specify VIL < 0.8V and VIH > 2.0V.
If the external reference source is DC-coupled, make sure that the VIL < 0.8V and VIH > 2.0V
levels are met. If the external reference source is AC-coupled, the clock generator uses its
self-bias to pull its reference input to the offset level of 1.5V. The required AC voltage swing
ranges from 1.4Vpk-pk to 2.2Vpk-pk.
4.8 External clock output
There is one MMCX clock input on the front panel that can serve as sampling/reference clock
output. Refer also to section 4.9 for more information about the clock tree.
4.9 Clock tree
The FMC offers a clock architecture that combines flexibility and high performance.
Components have been chosen to minimize jitter and phase noise and reduce degradation of
the data conversion performance. The user may choose to use an external sampling clock or
an internal sampling clock.
The clock tree has a PLL and clock distribution section. The PLL ensures locking of the
internal VCO clock to an external supplied reference. There is an onboard reference which is
used if no external reference is present. The onboard reference is a QuartzCom TX3-801
30.72MHz.