i-See IGEPv2 BOARD Quick user guide

ISEE
IGEPv2
BOARD
ISEE ( Integration Software & Electronics Engineering )
Address: C/Vallespir nº19 Planta 1 odulo 1
Post Code: 08224
City: Sant Cugat
Country: SPAIN
Phone: [phone]
[email protected]m
http://www.iseebcn.com
http://www.igep.es
IGEPv2 BOARD
Hardware Reference anual
(Revision 1.20 1/10/2010)

IGEPv2 BOARD HARDWARE USER ANUAL v1.20
ISEE 2007 SL. All rights reserved, IGEP® is a registered trademark from ISEE 2007 SL. The following is
provided for informational purposes only.
DOCU ENT FRO ISEE 2007 S.L. AN-PR-IGEP.0020-001.20.HW_RC 10/1/2010
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CONTENTS
1 COPYRIGHT NOTICE ................................................................................ 5
2 WARRANTY ............................................................................................. 5
3 ISEE IGEPv2 BOARD FEATURES ................................................................ 7
3.1 ISEE IGEPv2 BOARD GENERAL SPECIFICATIONS ................................... 9
3.2 SYSTE BLOCK DIAGRA ................................................................. 15
3.2.1 IGEPv2 Revision B board series block diagram ............................... 15
3.2.2 IGEPv2 Revision C board series block diagram ............................... 16
3.2.3 IGEPv2 Revision C board series improvements ............................... 17
3.3 GENERAL VIEW ................................................................................ 18
3.3.1 IGEPv2 Revision B board series view ............................................ 18
3.3.2 IGEPv2 Revision C board series view ............................................ 19
3.4 ECHANICAL SPECIFICATION ............................................................ 20
3.4.1 IGEPv2 Revision B board series mechanical ................................... 20
3.4.2 IGEPv2 Revision C board series mechanical ................................... 21
3.5 ELECTRICAL SPECIFICATIONS ........................................................... 22
4 WIFI/BLUETOOTH INTERFACE .................................................................. 24
4.1 BLOCK DIAGRA .............................................................................. 24
4.2 INTERFACES .................................................................................... 24
4.3 Power-on Reset Sequence for WLAN ................................................... 25
4.4 WLAN RESET/PDN PINS .................................................................... 26
4.5 BLUETOOTH RESET PINS ................................................................... 26
4.6 PC INTERFACE ............................................................................... 26
4.6.1 TPS65950 SIDE ......................................................................... 26
4.6.2 WIFI ODULE SIDE .................................................................... 27
5 CONNECTORS DESCRIPTION ................................................................... 28

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5.1 CONNECTOR J200: AIN 5.0VCC POWER ............................................ 29
5.2 CONNECTOR J400: JTAG DEBUG ........................................................ 29
5.3 CONNECTOR J940: POWER + RS485 .................................................. 31
5.4 CONNECTOR J960: SERIAL PORT DEBUG (+ EXTRA RS232) .................. 33
5.5 CONNECTOR J971: KEYBOARD ATRIX 4x4 ......................................... 37
5.6 TFT CONNECTORS: JA41-JA42 ........................................................... 39
5.6.1 CONNECTOR JA41 ...................................................................... 39
5.6.2 CONNECTOR JA42 ...................................................................... 43
5.6.3 CONNECTOR JA41-JA42 COUNTERPART ........................................ 44
5.7 CONNECTOR J990: GPIO ................................................................... 45
5.8 IGEPv2 ANTENNAS (INTERNAL/EXTERNAL - UD11, JD21, JD22) ............. 50
5.9 CONNECTOR JC20/JC21: ANALOG TO DIGITAL CONVERTER .................. 54
5.10 CONNECTOR JC30: CA ERA CONNECTOR ........................................ 56
5.11 S_VIDEO SIGNALS (TP400 and TP401) ............................................ 59
5.12 RTC BACKUP BATTERY ................................................................... 60
6 BOARD REFERENCE ................................................................................ 63
7 LIST OF FIGURES ................................................................................... 64
8 CHANGELOG .......................................................................................... 67

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VERSION CONTROL
VERSION DATE ORIGIN DESCRIPTION
1.00 19/03/2009 R&D Initial version
1.02 20/05/2009 R&D Board Configuration update.
1.10 24/0 /2009 R&D Update Hw Revision RB
1.11 21/09/2009 R&D Document Update
1.12 24/09/2009 R&D Document Update
1.13 23/10/2009 R&D Document Update
1.14 18/11/2009 R&D Document Update
1.15 9/03/2010 R&D Update Hw Revision RC
1.16 15/05/2010 R&D Document Update
1.1 6/0 /2010 R&D Document Update
1.18 9/0 /2010 R&D Document Update
1.19 31/08/10 R&D Document Update

IGEPv2 BOARD HARDWARE USER ANUAL v1.20
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provided for informational purposes only.
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1COPYRIGHT NOTICE
This document is copyrighted, 2009, by ISEE 2007 SL. All rights are reserved. ISEE
reserves the right to make improvements to the products described in this manual
at any time without notice. No part of this manual may be reproduced, copied,
translated or transmitted in any form or by any means without the prior written
permission of the original manufacturer. Information provided in this manual is
intended to be accurate and reliable. However, the original manufacturer assumes
no responsibility for its use, nor for any infringements upon the rights of third
parties which may result from its use.
2WARRANTY
Should this evaluation board/kit not meet the specifications indicated in the User’s
Guide, the board/kit may be returned within 30 days from the date of delivery for a
full refund.
THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY
SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES,
EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the
goods. Further, the user indemnifies ISEE 2007 SL from all claims arising from the
handling or use of the goods. Due to the open construction of the product, it is the
user’s responsibility to take any and all appropriate precautions with regard to
electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER
PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL,
INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
ISEE 2007 SL currently deals with a variety of customers for products, and
therefore our arrangement with the user is not exclusive. ISEE assumes no liability
for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read specifically, the Warnings and Restrictions notice in this manual prior to
handling the product. This notice contains important safety information about
temperatures and voltages. For additional information on IGEPV2 environmental
and/or safety programs, please contact with ISEE ([e-mail]).

IGEPv2 BOARD HARDWARE USER ANUAL v1.20
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provided for informational purposes only.
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No license is granted under any patent right or other intellectual property right of
ISEE covering or relating to any machine, process, or combination in which such
ISEE products or services might be or are used.
WARRANTY: IGEPV2 i warranted again t defect in material and
workman hip for a period of 1 year from purcha e. Thi warranty doe not
cover any problem occurring a a re ult of improper u e, modification ,
expo ure to water, exce ive voltage , abu e, or accident . All board will
be returned via tandard mail if an i ue i found. If no i ue i found or
expre return i needed, the cu tomer will pay all hipping co t .
ISEE IGEP platform web site: http://www.igep.es
ISEE IGEP wiki: http://labs.igep.es
ISEE shop: http://shop.igep.es or https://shop.igep.es
ISEE Software Repositories: http://git.igep.es

IGEPv2 BOARD HARDWARE USER ANUAL v1.20
ISEE 2007 SL. All rights reserved, IGEP® is a registered trademark from ISEE 2007 SL. The following is
provided for informational purposes only.
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3ISEE IGEPV2 BOARD FEATURES
De cription Characteri tic
Proce or O AP3530 (AR Cortex-A8)
Proce or Speed 720 hz
Memory SDRAM 512 Bytes LPDDR SDRA – 200 hz
Nand Fla h 512 bytes
DSP T S320D 64+
DSP Speed 430 hz
Video 3D Accelerator PowerVR SGX 530
Power Management TPS65950
Debug Console RS232 + JTAG Interface

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PCB ize 93 x 65 x 1.6 mm
Indicator 2 Bicolor USER LEDS
USB 2.0 LS/FS/HS OTG 1 ini AB USB socket connector (dual slave and host role)
USB 2.0 HS HOST 1 Type A USB socket connector (standard USB host)
Audio tereo in/out 3.5mm standard stereo audio jack
microSD microSD connector (SD and SDHC cards supported)
DVI video output DVI-D using HD I connector. (video and TS lines are
available in expansion connector also).
Power 5Vcc / 1A
3.5mm socket connector for wall plug or JST Connector
Expan ion connector Power 5V and 1.8V, UART, cBSP, cSPI, I2C, GPIO,
RS485 with transceiver, Keyboard.
Wifi IEEE 802.11b/g 2,4GHz
Bluetooth 2.0
Antenna WiFi/Bluetooth 1 shared internal antenna (integrated on PCB)
Ethernet 10/100 B BaseT (RJ45 connector with led link/activity)
Temperature Range Commercial ( 0 to 70 Cº) and Industrial range (-40 to
+80 Cº Degrees) are available (Contact ISEE ale )
WARNING: IGEPv2 BOARD CAN ONLY BE POWERED WITH 5V DC
POWER SUPPLY OR THE BOARD WILL BE DAMAGED!
The following sections provide more detail on each feature and components on the
IGEPv2 BOARD.

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3.1 ISEE IGEPV2 BOARD GENERAL SPECIFICATIONS
OMAP Proce or
The IGEPv2 BOARD uses the O AP3530 version ES3.1 and comes in a 0.4mm pitch
memory POP package on it.
POP (Package on Package) is a technique where the memory, NAND and SDRA ,
are mounted on top of the O AP3530. For this reason, when looking at the IGEPv2
BOARD, you will not find an actual part labeled O AP3530.
Figure 1 POP Package
Memory
The memory is mounted on top of the processor as mentioned. The key function of
the POP memory is to provide:
•4Gb NAND x 16 (512 B)
•4Gb LP-DDR SDRA x32 (512 B @ 200 Hz)
Power Management
The TPS65950 is used on the board to provide power to the IGEPv2 Board with the
exception of the 3.3V regulator which is used to provide power to the DVI-D
encoder and RS232 driver. In addition to the power it also provides:
•Stereo Audio Out
•Stereo Audio in
•Power on reset
•USB OTG PHY
•Status LED

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USB 2.0 LS/FS/HS OTG
On the board a single USB 2.0 OTG Port is
provided.
Figure 2 USB OTG connector
It is not possible to power the board with the OTG connector.
USB 2.0 HS HOST
On the board a single USB 2.0 HS HOST only one port is provided via a USB Type A
socket connector. Hardware provides power on/off switch control and up to 500mA
of current limit at 5V.
Figure 3 USB HOST connector
USB HOST Port supports only high speed devices (USB 2.0
HS devices). In order to support low speed devices (USB 1.0
LS devices) or full speed devices (USB 1.1 FS devices), external USB 2.0 HUB must
be used.
WIFI
IEEE802.11b/g compliant.
Chipset based on arvell 88W8686. The 88W8686 integrates a RF transceiver
operating at 2.4GHz, a physical layer, a media access controller, and an AR
processor into a single die.
BLUETOOTH
Bluetooth 2.0 compliant.
Class 2, 2.5 mW (4 dBm) ~10 meters
Version 2.0 + EDR 3 bit/s
ETHERNET
A RJ45 connector is provided for the Ethernet Auto- DIX Full Duplex 10/100 Base T
interface.
There is a EEPRO (U830) memory for AC configuration (Not populated).
NOTE: Contact ISEE sales for custom assembly boards.

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Figure 4 ETHERNET connector
This connectors comes with link and activity status led.
Stereo Audio Output Connector
A 3.5mm standard stereo output audio jack is provided to access the stereo output
of the onboard audio CODEC. The Audio CODEC is provided by the TPS65950.
Figure 5 Stereo Output connector location
Stereo Audio In connector
A 3.5mm standard stereo audio input jack is provided to access the stereo input of
the onboard audio CODEC.
Figure 6 Stereo Input connector location

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DVI-D Connector
The IGEPv2 BOARD can drive a LCD panel equipped with a DVI-D digital input. This
is the standard LCD panel interface of the O AP3530.
Figure 7 HDMI connector
DDC2B (Display Data Channel) or EDID (Enhanced Display ID) support over I2C is
provided in order to allow for the identification of the LCD monitor type and
settings.
The IGEPv2 BOARD does not support the full HD I interface and is used to provide
the DVI-D interface portion only. The user must use a HD I to DVI-D cable or
adapter to connect to a LCD monitor. A standard HD I cable can be used when
connecting to a monitor with and HD I connector.
LCD and touch creen header
A pair of 1.27mm pitch 2x10 headers are provided to have access to the LCD
signals and touchscreen control (IGEPv2 Revision B boards). On IGEPv2 Revision C
boards, JA41 connector is wider and enhanced with additional LCD bits depth. All
IGEPv2 boards (Revisions B and C) are mechanical, electrical and logical
compatible.
This allows for the creation of LCD boards to support different LCD panels.
microSD Connector
A microSD connector is provided for microSD cards form
factor.
The microSD memory card is the smallest memory card
available commercially, with the lowest price per capacity
and the highest capacity. At 15 mm × 11 mm × 1 mm
(about the size of a fingernail), it is about a quarter the size
of an SD card.

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The microSD connector supports SD and SDHC cards. SDHC (Secure Digital High
Capacity, SD 2.0) is an extension of the SD standard which increases card's storage
capacity up to 32GB. SDHC cards shares the same physical and electrical form
factor as older (SD 1.x) cards, allowing SDHC-devices to support both newer SDHC
cards and older SD-cards.
RS232
IGEPv2 Revision B boards provide only UART3 with RS232 levels on J960.
IGEPv2 Revision C boards provide both UART1 and UART3 with RS232 levels on
J960. [Contact ISEE sales for custom assembly boards for UART2 port]
RS485
The IGEPv2 board comes with 1 x RS485 on JST connector J940 (UART1). On
IGEPv2 Revision B are default populated. On IGEPv2 Revision C, RS485 are not
default populated. [Contact ISEE sales for custom assembly boards for RS485
feature].
ANALOG TO DIGITAL CONVERTER (A/D)
The IGEPv2 BOARD could come with one ADC (Analog to digital converter) device.
The analog signal inputs from U.FL HIROSE connector (located at the bottom) or
two 2,54mm pins header.
Several ADC devices can be populated. For example:
•ADC-SPI 3 Sps 3V3 (LTC2366)
•ADC-SPI 1 Sps 5VDC (ADC121S101)
Indicator
There are two bicolor LEDs on the Board that can be controlled by the user. In total
are like 4 individual leds and 16 color schemes
•Three leds are controlled via GPIO pins on the O AP3530 Processor
•One is programmed via the I2C interface on the TPS65950
Power Connector
Power will be supplied via the DC power jack (or via JST connector J940).
JTAG Connector
A 14 pin JTAG header is provided on the board to facilitate the SW development
and debugging of the board by using various JTAG emulators. The interface is at
1.8V on all signals. Only 1.8V C OS levels are supported. DO NOT expo e the
JTAG header to 3.3V.

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Expan ion Header
An option for a single 28 pin header is provided on the board to allow for the
connection of various expansion cards that could be developed by the users or
other sources. Due to multiplexing, different signals can be provided on each pin
providing more that 24 actual signal accesses.

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3.2 SYSTE BLOCK DIAGRA
3.2.1 IGEPV2 REVISION B BOARD SERIES BLOCK DIAGRA
Figure 8 IGEPv2 Revi ion B board erie block diagram
O AP3530
USB HOST
HS
microSD
INTERFACE
JTAG
INTERFACE
ETHERNET
INTERFACE
WIFI
INTERFACE
BLUETOOTH
INTERFACE
DVI
INTERFACE
USB-OTG
LS/FS/HS
TPS65950
STEREO-IN
STEREO-OUT
DVI digital
transmiter
ETHERNET
Controller
10/E100
WIFI-
BLUETOOTH
CO BO
Controller
RS485
INTERFACE
RS485
DRIVER
EXPANSION
INTERFACE
KEYBOARD

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3.2.2 IGEPV2 REVISION C BOARD SERIES BLOCK DIAGRA
Figure 9 IGEPv2 Revi ion C board erie block diagram
O AP3530
USB HOST
HS
microSD
INTERFACE
JTAG
INTERFACE
ETHERNET
INTERFACE
WIFI
INTERFACE
BLUETOOTH
INTERFACE
DVI
INTERFACE
USB-OTG
LS/FS/HS
TPS65950
STEREO-IN
STEREO-OUT
DVI digital
transmiter
ETHERNET
Controller
10/E100
WIFI-
BLUETOOTH
CO BO
Controller
RS485
INTERFACE
RS485
DRIVER
EXPANSION
INTERFACE
RS232
DRIVER
RS232
INTERFACE
CA ERA
INTERFACE
RTC
Backup
Battery
KEYBOARD

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3.2.3 IGEPV2 REVISION C BOARD SERIES I PROVE ENTS
ain goals of new IGEPv2 revision C series are:
•RTC Battery Backup for TPS65950 (Super Capacitor or Rechargeable
Battery)
•Updated TFT interface from 18bit to 24bit.
•New Camera Connector (full O AP interface on a new 28pin header
connector)
•Optional high speed 3 Bps ADC (Hirose U.FL connector or two pin header)
•Added second RS232 UART on J960 (Now 2 UARTs on J960, UART3+UART1)
•Changed JD22 from GSC urata connector to Hirose U.FL connector
•Added optional second external antenna (Hirose U.FL connector)
•New GPIO to physically reset BT module
•Added resistors for hardware UART selection
•Non-populated parts:
oJ400 JTAG connector
oJ990: GPIO expansion connector
oJ970: 4x4 keyboard connector
oJD22: External wifi antenna connector
oJA41 and JA42: TFT interface
oJC30: Camera interface
oUC20 3 Bps ADC + JC21 Hirose connector
Contact ISEE sales for custom assembly boards for fully previous IGEPv2
revision B compatible mechanical, electrical and logical) on IGEP0020-
RCx PCBs.

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3.3 GENERAL VIEW
3.3.1 IGEPV2 REVISION B BOARD SERIES VIEW
Figure 10 IGEPv2 revi ion B board top ide component
Figure 11 IGEPv2 revi ion B board bottom ide component

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3.3.2 IGEPV2 REVISION C BOARD SERIES VIEW
Figure 12 IGEPv2 revi ion C board top ide component
Figure 13 IGEPv2 revi ion C board bottom ide component

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3.4 ECHANICAL SPECIFICATION
3.4.1 IGEPV2 REVISION B BOARD SERIES ECHANICAL
Figure 14 IGEPv2-RB Top view mechanical pecification
Get echanical drawings on:
http://www.igep.es  User enu  Download  01-Products  IGEPv2 
HW_ echanical