Acorn Risc PC Product manual

Acorn Rise PC
Technical Reference Manual

Acorn Risc PC
Contents
About this manual
Safety
Part 1 - System description
Introduction
CPU and control
Memory system
Video and audio system
Peripheral control
Expansion and I/O system
Part 2 - Interface specifications
Introduction
Keyboard and mouse
Serial port
Parallel port
Video system
Audio system
OPEN Bus
DRAM SIMMs
VRAM
Floppy drive
,IDE -hard disc
Links, plugs and sockets
Part 3 - Parts lists
Rise PC main PCB assembly parts list
Rise PC
2W Backplane PCB assembly parts list
Rise PC
4W Backplane PCB assembly parts list
Rise PC 2MB HD final assembly parts list
Rise PC 5MB HD final assembly parts list
Rise PC 9MB HD final assembly parts list
Risc PC ARM610 PCB assembly parts list
Rise PC VRAM 1MB PCB assembly parts list
Rise PC VRAM 2MB PCB assembly parts list
Appendix A - Power On Self Test
Appendix 8 - Monitor adaptor cables
Appendix C - Engineering drawings
Appendix D - System chipset pinouts
Appendix E - Mechanical and electrical data
Technical Reference Manual
iv
iv
1-1
1-1
1-3
1-10
1-14
1-18
1-19
2-1
2-1
2-1
2-6
2-9
2-12
2-15
2-16
2-23
2-25
2-29
2-35
2-44
3-1
3-1
3-6
3-6
3-7
3-8
3-9
3-10
3-11
3-11
A-1
8-1
C-1
D-1
E-1
Contents
Issue 1, September 1994
,.
III

Acorn Risc PC Technical Reference Manual
Part 1 - System description
Introduction
The Acorn Risc PC family is built around the Advanced
Risc Machines (ARM) chipset, comprising the ARM
processor, the I/O and Memorycontroller (IOMD) and the
Video Controller (VIDC). All products feature 10MD and
VI DC 20 and offer the following features:
DMA Enhanced Bus Interface (DEBI) -where
capabilities include 32-bit data transfer and the
support
of up to two general purpose DMA channels
for transfer between I/O and memory
PC-AT compatible keyboard interface
Support for Video RAM (VRAM)
1-, 2-, 4-, 8-, 16- &32-bit pixel depths
Pixel rates in excess of 110 MHz
Support for up to 256
MB of DRAM via two DRAM
SIMM sockets
Interchangeable ARM CPU card
OPEN Bus connector for second bus master or
additional CPU.
Ablock diagram of the main system components is
shown in Figure 1.1 overleaf.
General
Initially, model variants feature either an ARM 610 or
ARM700 processor with the option for aFloating Point
Accelerator
({PA) to plug in alongside the ARM700. the
processor is resident on a small plug in card which fits in
to one of the two 'OPEN Bus' slots on the main PCB.
Variants are also likely to appear which feature
an Intel-
based processor resident
in the second OPEN Bus slot.
The number of expansion bus slots available is either
none, 2
or 4(with architectural support for up to 8). The
backplane PCBs are easily interchangeable
as they plug
into the 132-way edge connector
on the main PCB. A
network slot is provided so that adding networkcapability
does not detract from the numberof free expansion card
slots available. This new Acorn propriety interface is,
therefore, incompatible with the existing
A30xO and
A4000 network expansion cards.
Memory upgrading is provided for by the use of DRAM
Single In-line Memory Modules (SIMMs). Two sockets
are provided for this purpose and the machine uses
industry-standard modules chosen to meet the system
specifications. VRAM is provided on a plug-in daughter
card; this is an Acorn proprietary upgrade module and
plugs into the Dual In-line Memory Module (DIMM)
connector on the motherboard.
The Parallel, Serial, floppy disc and Integrated Drive
Electronics (IDE) hard disc sub-systems are handled by
an industry-standard PC clone Universal Peripheral
Controller device (Le. 'combo' IC). This provides PC-
standard control signals and allows each of these
interfaces to
be (broadly) compatible with the PC world.
Anew version of RISC OS 3is provided with these
machines
in two 1MB ROMS on the main PCB. This
version, 3.50, provides all the necessary software and
user interfaces
to make use of the hardware: for instance
anew screen mode selector to cater for the increased
number of screen modes available with VIDC 20. Some
other functional improvements over version 3.11 have
also been included. The reader is referred to the
RISC as 3UserGuide for the Rise PC and RISC as3
Programmer's Reference Manual,
Vol. 5(version 3.5
supplement) for further details.
System chipset: ARM, IOMD, vIDe and
peripheral controller
ARM
From the ARM 600 onwards, all ARM processors provide
afull 32-bit address bus and a32-bit program counter.
The
ARM 6xO and 7xO also have the ability to be
configured in a26-bit address space mode for either
instruction fetches ordataoperations. RISC OS 3version
3.5 operates
in 26-bit address space for instruction
fetches
and 32-bit address space for data access. The
ARM610 (and 700) also feature 4KB and 8KB caches
respectively and both use write-back buffers to improve
on chip memory performance. Both devices also feature
an on-board memory management unit (MMU) with a
4KB page size.
IOMD
From the ARM600 onwards, the Memory Management
Unit is integrated within the ARM CPU. This has allowed
memory control and refresh (previously provided by
MEMC),
10 control (previously provided by 10C) and PC
specific I/O signals to drive the
PC Combo device
(previously provided by lOEB) together with some new
functionality to
be implemented in one device: the I/O
Memory Device, or 10MD. Essentially, 10MD provides
the following:
•direct interface to ARM61 0
or ARM700
•
DRAM control for2SIMMs providing 4banks of DRAM
•VRAM control and interface
to VIDC20, including
generation of transfer cycles
•DMA Interface to CD-quality digital sound chip
•Video and sound DMA channels similar to that
provided by MEMC
•four general purpose 1/0 DMA channels
•.. 16-bit byte-steered bus, for on-board peripherals such
as the network and IDE interfaces
two general purpose counter /timers and system
interrupt control registers
•interrupt line allocation similar to previous machines
•
PC keyboard interface
•Quadrature mouse interface.
System description
Issue 1, September 1994
1-1

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Expansion Interfaces
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IDE
Hard disc
page 1-18
Peripheral Control
~ Uni-Direclional Buffer
page 1-3
CPU &Control
II !=. Parallel
Serial
Mouse buttons
IQuadrature Mouse
I IBM PS/2 COrJ1lalible Keyboard
~ Bi-Direclional Buffer
page 1-10
- - - - - - - - - -I _. _
~ Uni-Directional Latch
page 1-14
Video IAudio IRandom Access Memory
Key
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Acorn Risc PC
VIDe
VIDC20 provides higher resolutions and colour depths
than previously available on Acorn platforms.
It is used in
either 32 or 54-bit DRAM access mode to interface (via
10M
D) with either system DRAM or 1or 2MB of VRAM.
Although
VI DC20 provides its own VRAM modes, the use
of 64-bit mode allows better provision for future
performance improvements. Colourdepth
is 1, 2, 4, 8, 16
or 32 bits per pixel and using anovel Phase Lock Loop
(PLL) frequency synthesizer pixel rates are continuously
selectable between 8and 135 MHz. VIDC20 supports the
old style VIDC1A 8channel 8bits stereo sound, but also
has ahigh quality digital stereo 16-bit serial sound
interface which is compatible with the Philips 1
2S
standard.
Peripheral controller
The FDC37C665 Peripheral controller or 'Combo' device
is memory mapped in the system 10 space and connects
to the lower 8bits of the buffered data bus. This device
provides the Floppy disc, Parallel and Serial interfaces,
along with some of the IDE control signals, although in
the system block diagram, only the IDE datapath and the
IDE control signals provided by 10MD are shown.
Architecture
The block diagram in Figure 1.1 shows how the system is
built up. The ARM, second CPU, 10MD, ROMs, DRAM
and VRAM (DRAM port) are all connected to the
unlatched data bus. 10MD uses the unlatched processor
address bus to generate the row and column addresses
for the DRAM and VRAM,
or suitable control signals for
I/O accesses'or ROM enable. The CPU databus passes
through byte steering logicinternalto 10MO and emerges
as the 16-bit on-board peripheral data bus 80[15:0]. This
bus allows OMA data to be transferred to or from the I/O
system at arbitrary byte locations. The Motherboard
1/0
devices use 80[15:0], which, along with the upper 16 bits
of data latched by four'74ACT57
4s undercontrol of
10MD, provides the 32-bit word, half word
or byte wide'
data bus to and from the DEBI expansion interface.
Technical Reference Manual
CPU and control
ARM CPU &OPEN Bus
The ARM processor is fitted to adaughtercard which
connects to the system via one of the OPEN Bus
connectors (see OPEN
Buson page 2-16). The ARM 61 C
card contains the ARM, a60 MHz can oscillatortogether
with adivide by 2circuit based on a 74ACT74in order
to
ensure aclean symmetrical 30 MHz clock signal and a
74ACT08 AND gate.
Syst~m Clock generation
The masterclock source, clk64, is a64MHz signal which
is applied to 10MD ancfprovides all the system timing.
The DRAM timing generators use both edges of a32MHz
clock, which
is generated from the 64MHz by dividing by
two. The peripheral bus is clocked from the master clock
divided by 4(16MHz). The video RAM serial interface
uses 64MHz divided by 3to generate
sc which clocks the
VRAM serial ports at 21.33MHz using a
2:1 mark space
ratio. The VIDC20 pcJk signal must be the same
as sc
during video RAM datatransfer, but must be the same as
mclk during cursor DMA, VIDC20 programming (Nprog
activity), and sound DMA (if the VIDC20 sound system
is
being used).
In addition to clk64 there is a24M Hz clock source which
provides areference clock
to both VIDC20 and the
FOC37C665 device.
rOMO
Interrupt control logic and 10C timers
IOMD has anumberofinterrupt inputs which can be used
to generate irq and fiq interrupts.
In addition, there are
internal interrupts generated by the DMA channels, the
keyboard interface and the 10C timers 0and
1. Aset of
registers similar to those
in 10C allow the interrupt
sources to be controlled by the processor. Some IOC
r.egister bits are unused, and some pin polarities are
different to 10C. Refer to Figure 1.2for the register bit
allo.cations, and to Table
1.1 for the interrupt active
levels.
Table 1.1: Interrupt active polarities
Interrupt
Description
Npliq Podula fiq inpul. Levellriggered,
activalow
Npirq Podula Irq input. Levellriggered, aClive low
Nsintr Serial interrupt input. Level triggered. ac1ive low
Nscirq Level triggered, active low
<D
Nlintr Floppy inlerrupt requesl. Levellriggered, active low
Nindex 'Floppy disc index input. Falling edge Iriggered
lIyl;Jack Flyback Irom VIDe. rising edge Iriggered
Idrq Floppy drq inlerrupl. Levellriggered. active high
'pintr Prinler inlerrupt request. Rising edge triggered
System description
Issue 1, September 1994 1·3

Acorn Risc PC
Technical Reference Manual
Table 1.1: Interrupt active polarities
DMA
Description
Priority Channel
o(highest) Cursor and DRAM Video
,Sound chan. 0(VIDC sound
OUI and linear sound in)
2VRAM transfer
cyde
3Sound chan.:' (linear sound
OUI)
4DRAM and VRAM refresh
5
va DMA channels ('round robin belween channels 0 to 3)
6(lowest) ARM
Table 1.2: DMA channels priority
There are four general purpose 1/0 DMA channels, and
two sound channels.
In addition, there are two further
channels for video and cursor data. The DMA channels
have fixed priorities as shown below.
The state machine which controls bus activity has a
number
of points at Which arbitration for the bus takes
place. Arbitration always takes place while the processor
performs
an idle cycle'and before it starts amemory
access.
In addition, arbitration occurs during sequential
memory accesses
as follows:
DRAMNRAM -sequential bursts of
up to awords can
occur uninterrupted by DMA.
In the absence of DMA
requests these bursts can extend to 256 words.
•
ROM -uninterrupted burst accesses of up to 4words
can occur. If non-burst ROM is used, arbitration occurs
on every access.
•PROG -uninterrupted bursts of
up to 4words can
occurwhere the access
is to an 10MD internal register.
Where the access is to the VIDC control register,
arbitration occurs on every word.
1/0 - an 10ROIIOGT mechanism is used for
programmed 1/0 and (non-I/O) DMA can occur during
1/0 cycles.
I/O and sound DMA
The I/O and sound DMA channels have two sets of
pointers,
so that data transfers may be 'double buffered'
as
is the case with the MEMC1 asound DMA channel.
The DMA pointers consist of two pairs
(A and B) of 29-bit
current address registers, and 12 bit end pointers which
also have 2control bits
in them, The current and end
pointer addresses are inclusive addresses, and the end
address
is the address of the last transfer, which will
depend upon the transfer size. The current address
registers are divided into two fields. The lower 12 bits
form
an offset into a4K page. The upper 17 bits form a
static page number. The end register consists
of a12 bit
page offset
in the lower 12 bits of the register, and two
control bits in the most significant bits of the register.
Each channel also has an a.bit control register, and a
three bit status register. The control register is readable
and writable, and the status register
is read only. Five of
the control register bits (Inc[ 4:0)) control the amount by
which the current pointer is incremented after each
transfer. Another bit (D) controls the direction of transfer,
Control (RIW)
StetUI (Rj
Requeat (R)
Mllk(RIW)
Cleer(W)
StatUI (R)
Requeat (Al
Mnlk (Riw)
Statue (R)
Request (Rl
Meek (RIW)
Level triggered, active low @
I/O Control Regleter
IRO" Interrupt Regleter
FlO Interrupt Register
IROB Interrupt Register
(j) This signal is the fOE interrupt signal inverted.
®This signal is the Network card interrupt signal
inverted.
There is acontrol register which provides access to a
small number of I/O pins. These are used for the /2C
interface, and for the 10 chip interface. The 10 pin is held
low during reset,
and then tri-stated. The 1
2Cinterface
pins are tri-stated on reset. The registers are also shown
in Figure 1.2. The functionality of these registers is similar
to the corresponding registers
in laC, except it is not
possible to generate aFlO from the
10 1/0 bit, and not all
the bits
in the registers are implemented. Referto the lac
data sheet, and Figure 1.2for further detail.
Figure 1.2: I/O Control and Interrupt Registers
Two timers, the same as those in lac are provided,
which are clocked at the same 2MHz rate. Note that the
lac documentation is incorrect in stating that Tinterval =
latch/2j.LS, it should say (Iatch+1 )/2I-lS. Note also that if a
latch command is issued immediately after ago
command, the value latched may
be the new value, but
may be the old value of the counter. This also occurs
in
laC, and should therefore not be aproblem.
1-4 Issue
1, September 1994 System
description

Acorn Risc PC
and one bit (E) is used to enable and disable the channel.
The status bits, and the Cbit of the control register are
described later.
DMA transfers are constrained to asingle physical page
by the following mechanism. The bottom
12 bits (page
offset) ofthe current pointer is incremented on each DMA
transfer by the programmed increment, and is compared
to the bottom 12bits of the end pointer. The page number
is not incremented, and is not compared. This has the
effect that it is possible to program the end pointer to be
less than the initial pageoffset, causing the DMA address
to wrap around at the end of the page. This is unlikely to
be useful.
In order to implement the double buffering mechanism,
each pair of registers is used alternately. An interrupt is
raised when one of the pair completes its transfer. If the
other pair has been programmed by this time, DMA
continues using this pair.
Figure 1.3: DMA Address registers
(one set per channel)
28 1211 0
Page[16:0} IOHsel[11 :0] C!Jrrent A
31 30
11 0
~I
I
End[ll :0] End A
28
1211 0
Page[16:0] IOHset[11
:OJ
ClJrrent B
31 30 11
0
[I[g
IEnd[11:0] End B
7 6 540
~l
Inc(4:0] Control
III
Enable
Oir
Clear
210
@EEl
Status
~
AlB
Inl
Overrun
The increment field in the control register determines the
channel increment as follows:
00001 Byte
00010 Half-word
00100 Word
10000 Quad-word
The I/O
DMA channels support byte, half-word and word
transfers only. The VIDC sound channel can support
quad-word DMA, but only when DMA is to
VI DC, not
when
it is from the CO DEC. The increment has adifferent
meaning for the video channel (see later).
Technical Reference Manual
The direction bit in the control register defines the
direction of the DMA transfer. When set, the transfer is
from peripheral to memory. Sound channel auses this bit
to control whether VIDC sound output mode, or CODEC
sound input mode is
in use.
Each DMA channel is controlled by asimple state
machine. The state machine is able to run when the
enable bit is set. The current state
is visible in the status
register and these bits are read only. The AlB bit
indicates which pairof currenVend pointers is
in use. The
Int bit indicates when the channel
is requesting an
interrupt. The Overrun bit indicates when achannel has
stopped because
it finished atransfer, and the other
pointer pair had not been programmed. Writing a1to the
Cbit of the control register resets the state machine to
state 110. The Cbit
of the control register is self clearing
and always reads zero.'
The S(Stop) and L(Last) bits in each end registercontrol
the behaviour of the channel when transfer of abuffer
completes. The Sbit must be set if the TC pin
is to be
asserted at the
endof the buffer. The Lbit is an indication
that the next transfer on that buffer will be the last.
It is
normally set by 10MD, but must
be set by the ARM in the
case where the channel is being initialised for asingle
tran·sfer. For buffers that require more than one transfer,
the Lbit should be cleared when the end register is
written.
In Figure 1.4 the three bits shown beside each state
correspond to the three bits of the status register, and
directly reflect the state of the DMA state machine. At
reset, the state machine enters state 110. This state and
state
111 are the idle states in which no DMA transfers
occur. The transition between states occurs either
by a
buffer finishing,
or by the ARM programming the next
pointer pair. The current and end pointers must be
programmed
in that order, as it is the write to the end
pointerwhich actually causes the state transition.
In practice, acomplete DMA transaction is performed by
asoftware state machine, as shown
in Figure 1.5, where
N
is the buffer numberbeing transferred and LastN is the
buffer number of the last buffer to be transferred, which
should have the Stop bit set when programmed. When
the last buffer has been programmed in, and the next
interrupt happens, adummy value
is programmed into
the next buffer pair in order to clear the interrupt. The
foUowing interrupt happens after the last buffer has been
transferred, at which point DMA can be disabled and the
channel reallocated. When the Wait for Ibox is
encountered, the software checks the I(Int) bit:
if set, it
continues to the next step; if clear, the software exits and
waits for the next DMA interrupt. After abufferwith the S
bit set has been transferred, the hardware always enters
one of the idle states;
it never continues to the other
buffer. The scheme is designed to cope with all possible
cases of overrun.
System description
Issue 1, September 1994 1-5

Acorn Risc PC
Technical Reference Manual
Figure 1.4: Hardware DMA state machine diagram
Finished
(StopA)
Busy (Buff Aactive)
g(000)
IFiniShed
(not
StopA)
Finished
(StopB)
Busy (Buff Aactive)
Write Buff A ~ ~
------4
7Int Write Buff B
'\
/ BuffA 7
'" Finished (010)
T r.::~~BI
(110)
Idle or Write Buff B
~
(Write Buff A
Buff B
(001)
Busy (Buff Bactive)
~
nt ~
Buff B
(011 )
Busy (Buff Bactive)
Finished
Write Buff B
)
Idle or Write Buff A
Figure 1.5: Software DMA state machine diagram
Program BunB with
bun., N, C( wilh
garbago •N>LaslN
OIA
Wait lori,
chock .Illiu.
Program But1A with
butt.r N, or wilh
garbolgo K N>LaslN
Yo.
1-6 Issue
1, September 1994 System description

Acorn Risc PC
Additionally there is aset of interrupt registers for the
DMA channels. For each channel there
is amask bit, a
status bit, and arequest bit, the status bit being a
replication of the Ibit in the DMA state machine. There
are 6interrupting DMA channels in total, and the interrupt
registers are arranged such that there
is aDMA channel
per bit of each register, with 2bits per register spare, as
shown
in Figure 1.6.
In Figure 1.6, the DMA interrupt status register indicates
which channels have interrupts outstanding. Achannel
generates an interrupt when it reaches the end of the
current buffer. An interrupt will be generated
if the
relevant DMA interrupt mask
is enabled. The DMA
request register holds the logical AND of the DMA
interrupt status and DMA interrupt mask registers,
indicating which channels are requesting
an interrupt.
When using, for example, an 8-slot backplane where the
data lines are buffered by a'245 device or similar on the
backplane, IOMD provides an output enable signal
(PBOE) which can be programmed to
be active or
inactive during DMAs from peripheral to memory.
In this
way the '245 buffer can be
di~abled for DMAs from
'internal' peripherals, such
as the Network card, or
enabled for DMAs from 'external' peripherals on
expansion cards. To do this, the DMAEXT register
is
used. Bits 3:0 of the DMAEXT register map to //0 DMA
channels 3to
0, and setting the relevant bit to a 1
indicates that the peripheral
is external. There are no
DMAEXT bits for the sound DMA channel, as the sound
CODEC is always an on-board peripheral.
Figure 1.6: DMA Interrupt registers
DMA Interrupt request register (DMARQ)
IIIDMA ''G
ue"channolO
DMA request channel 1
DMA request channel 2
'-- DMA request channel 3
1...- DMA request sound chan. 0
1...- DMA request sound chan. 1
Technical Reference Manual
DMA Interrupt mask register (DMAMSK)
DMA Interrupt status register (DMAST)
DMA External register (DMAEXT)
System description
Issue 1, September 1994
.'
1-7

Acorn Risc PC
RegIsters
The following table lists the registers in IOMD. The
physical base address of these registers is &0320 0000,
the same
as the address of the IOC internal registers in
previous platforms. The size field indicates the width of
the register. although some bits may not be used in a
register.
Table 1.3: Register definitions
Technical Reference Manual
Name
Address
Size Read Write
Function
Reset state
IOCR 0
(8)
Status Control
110 ~ntrol
-1-
KBOOAT
4(8) Rx Data Tx Data Keyboard data -x-
KBOCR 8(8) Status Control Keyboard
~ntrol
-0-
IROSTA 10
(B)
Status
---
IROA status
IRORQA
14 (B)
Request Clear IROA requesVc:lear
-x-
IROMSKA 1B
(B)
Mask'
Mask
IRQAmask
-0-
IROSTB 20
(B)
Status .
'.
---
IROB status
IROROB 24
(B)
Request
---
IROB request
IROWoSKB 2B
(8) Mask Mask
IROBmask
-0-
FIOST 30
(8)
Status
--
FlO status
FlORO 34 (8) Request
---
FlO request
FIOMSK 38 (8) Mask Mask FlO mask -0-
TOLOW 40
(8)
Count Low Latch Low Timer 0low bits -x-
TOHIGH 44
(8) Count High Latch High Timer 0high bits -x-
TOGO
48 (B)
---
Go~mmand
Timer 0Go ~mmand
-x-
TOLAT
4C (8)
---
Latch ~mmand
Timer 0Lateh emd -x-
T1LOW 50
(8) Count Low Latch Low Timer 1low bits -x-
T1HIGH 54
(B) Count High Latch High Timer 1high bits -x-
T1GO 58 {(8)
---
Go~mmand
Timer 1Go oommand
-x-
T1LAT 5C (8)
---
Latch ~mmand Timer 1Lateh emd -x-
ROMCRO
80
(B)
RomCrO RomCrO ROM oontrol bank 0-0-
ROMCR1 84 (8) RomCr1 RomCr1 ROM oontrol bank 1-0-
ORAMCR 88
(8) OramCr OramCr DRAM oontrol -0-
VREFCR
8C
(8) VrelCr VrefCr
VRAM &refresh oontrol -0-
FSIZE 90
(8) Size Size Flybaek line size -x-
100
94
(B) 100
--
Chip ID no. low byte
101 98 (8)
101
--
Chip ID no. high byte
VERSION 9C (8) Version -Chip version number
IIOUSEX
AO
(16) MouseX MouseX Mouse Xposition -x-
IIOUSEY
A4 (16) MouseY MouseY Mouse Yposilion -x-
OMATCR Co (8) OmaTa OmaTa OACK timing
~ntrol
-x-
IOTCR
C4
(8) loTer loTer
110 liming ~ntrol
-x-
ECTCR C8 (8) EeTcr EeTcr Expansion card timing -x-
1-8 Issue 1, September 1994 System description