Acorn Risc PC Product manual

Acorn Rise PC
Technical Reference Manual

Acorn Risc PC
Contents
About this manual
Safety
Part 1 - System description
Introduction
CPU and control
Memory system
Video and audio system
Peripheral control
Expansion and I/O system
Part 2 - Interface specifications
Introduction
Keyboard and mouse
Serial port
Parallel port
Video system
Audio system
OPEN Bus
DRAM SIMMs
VRAM
Floppy drive
,IDE -hard disc
Links, plugs and sockets
Part 3 - Parts lists
Rise PC main PCB assembly parts list
Rise PC
2W Backplane PCB assembly parts list
Rise PC
4W Backplane PCB assembly parts list
Rise PC 2MB HD final assembly parts list
Rise PC 5MB HD final assembly parts list
Rise PC 9MB HD final assembly parts list
Risc PC ARM610 PCB assembly parts list
Rise PC VRAM 1MB PCB assembly parts list
Rise PC VRAM 2MB PCB assembly parts list
Appendix A - Power On Self Test
Appendix 8 - Monitor adaptor cables
Appendix C - Engineering drawings
Appendix D - System chipset pinouts
Appendix E - Mechanical and electrical data
Technical Reference Manual
iv
iv
1-1
1-1
1-3
1-10
1-14
1-18
1-19
2-1
2-1
2-1
2-6
2-9
2-12
2-15
2-16
2-23
2-25
2-29
2-35
2-44
3-1
3-1
3-6
3-6
3-7
3-8
3-9
3-10
3-11
3-11
A-1
8-1
C-1
D-1
E-1
Contents
Issue 1, September 1994
,.
III

Acorn Risc PC Technical Reference Manual
Part 1 - System description
Introduction
The Acorn Risc PC family is built around the Advanced
Risc Machines (ARM) chipset, comprising the ARM
processor, the I/O and Memorycontroller (IOMD) and the
Video Controller (VIDC). All products feature 10MD and
VI DC 20 and offer the following features:
DMA Enhanced Bus Interface (DEBI) -where
capabilities include 32-bit data transfer and the
support
of up to two general purpose DMA channels
for transfer between I/O and memory
PC-AT compatible keyboard interface
Support for Video RAM (VRAM)
1-, 2-, 4-, 8-, 16- &32-bit pixel depths
Pixel rates in excess of 110 MHz
Support for up to 256
MB of DRAM via two DRAM
SIMM sockets
Interchangeable ARM CPU card
OPEN Bus connector for second bus master or
additional CPU.
Ablock diagram of the main system components is
shown in Figure 1.1 overleaf.
General
Initially, model variants feature either an ARM 610 or
ARM700 processor with the option for aFloating Point
Accelerator
({PA) to plug in alongside the ARM700. the
processor is resident on a small plug in card which fits in
to one of the two 'OPEN Bus' slots on the main PCB.
Variants are also likely to appear which feature
an Intel-
based processor resident
in the second OPEN Bus slot.
The number of expansion bus slots available is either
none, 2
or 4(with architectural support for up to 8). The
backplane PCBs are easily interchangeable
as they plug
into the 132-way edge connector
on the main PCB. A
network slot is provided so that adding networkcapability
does not detract from the numberof free expansion card
slots available. This new Acorn propriety interface is,
therefore, incompatible with the existing
A30xO and
A4000 network expansion cards.
Memory upgrading is provided for by the use of DRAM
Single In-line Memory Modules (SIMMs). Two sockets
are provided for this purpose and the machine uses
industry-standard modules chosen to meet the system
specifications. VRAM is provided on a plug-in daughter
card; this is an Acorn proprietary upgrade module and
plugs into the Dual In-line Memory Module (DIMM)
connector on the motherboard.
The Parallel, Serial, floppy disc and Integrated Drive
Electronics (IDE) hard disc sub-systems are handled by
an industry-standard PC clone Universal Peripheral
Controller device (Le. 'combo' IC). This provides PC-
standard control signals and allows each of these
interfaces to
be (broadly) compatible with the PC world.
Anew version of RISC OS 3is provided with these
machines
in two 1MB ROMS on the main PCB. This
version, 3.50, provides all the necessary software and
user interfaces
to make use of the hardware: for instance
anew screen mode selector to cater for the increased
number of screen modes available with VIDC 20. Some
other functional improvements over version 3.11 have
also been included. The reader is referred to the
RISC as 3UserGuide for the Rise PC and RISC as3
Programmer's Reference Manual,
Vol. 5(version 3.5
supplement) for further details.
System chipset: ARM, IOMD, vIDe and
peripheral controller
ARM
From the ARM 600 onwards, all ARM processors provide
afull 32-bit address bus and a32-bit program counter.
The
ARM 6xO and 7xO also have the ability to be
configured in a26-bit address space mode for either
instruction fetches ordataoperations. RISC OS 3version
3.5 operates
in 26-bit address space for instruction
fetches
and 32-bit address space for data access. The
ARM610 (and 700) also feature 4KB and 8KB caches
respectively and both use write-back buffers to improve
on chip memory performance. Both devices also feature
an on-board memory management unit (MMU) with a
4KB page size.
IOMD
From the ARM600 onwards, the Memory Management
Unit is integrated within the ARM CPU. This has allowed
memory control and refresh (previously provided by
MEMC),
10 control (previously provided by 10C) and PC
specific I/O signals to drive the
PC Combo device
(previously provided by lOEB) together with some new
functionality to
be implemented in one device: the I/O
Memory Device, or 10MD. Essentially, 10MD provides
the following:
•direct interface to ARM61 0
or ARM700
•
DRAM control for2SIMMs providing 4banks of DRAM
•VRAM control and interface
to VIDC20, including
generation of transfer cycles
•DMA Interface to CD-quality digital sound chip
•Video and sound DMA channels similar to that
provided by MEMC
•four general purpose 1/0 DMA channels
•.. 16-bit byte-steered bus, for on-board peripherals such
as the network and IDE interfaces
two general purpose counter /timers and system
interrupt control registers
•interrupt line allocation similar to previous machines
•
PC keyboard interface
•Quadrature mouse interface.
System description
Issue 1, September 1994
1-1

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Expansion Interfaces
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IDE
Hard disc
page 1-18
Peripheral Control
~ Uni-Direclional Buffer
page 1-3
CPU &Control
II !=. Parallel
Serial
Mouse buttons
IQuadrature Mouse
I IBM PS/2 COrJ1lalible Keyboard
~ Bi-Direclional Buffer
page 1-10
- - - - - - - - - -I _. _
~ Uni-Directional Latch
page 1-14
Video IAudio IRandom Access Memory
Key
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Acorn Risc PC
VIDe
VIDC20 provides higher resolutions and colour depths
than previously available on Acorn platforms.
It is used in
either 32 or 54-bit DRAM access mode to interface (via
10M
D) with either system DRAM or 1or 2MB of VRAM.
Although
VI DC20 provides its own VRAM modes, the use
of 64-bit mode allows better provision for future
performance improvements. Colourdepth
is 1, 2, 4, 8, 16
or 32 bits per pixel and using anovel Phase Lock Loop
(PLL) frequency synthesizer pixel rates are continuously
selectable between 8and 135 MHz. VIDC20 supports the
old style VIDC1A 8channel 8bits stereo sound, but also
has ahigh quality digital stereo 16-bit serial sound
interface which is compatible with the Philips 1
2S
standard.
Peripheral controller
The FDC37C665 Peripheral controller or 'Combo' device
is memory mapped in the system 10 space and connects
to the lower 8bits of the buffered data bus. This device
provides the Floppy disc, Parallel and Serial interfaces,
along with some of the IDE control signals, although in
the system block diagram, only the IDE datapath and the
IDE control signals provided by 10MD are shown.
Architecture
The block diagram in Figure 1.1 shows how the system is
built up. The ARM, second CPU, 10MD, ROMs, DRAM
and VRAM (DRAM port) are all connected to the
unlatched data bus. 10MD uses the unlatched processor
address bus to generate the row and column addresses
for the DRAM and VRAM,
or suitable control signals for
I/O accesses'or ROM enable. The CPU databus passes
through byte steering logicinternalto 10MO and emerges
as the 16-bit on-board peripheral data bus 80[15:0]. This
bus allows OMA data to be transferred to or from the I/O
system at arbitrary byte locations. The Motherboard
1/0
devices use 80[15:0], which, along with the upper 16 bits
of data latched by four'74ACT57
4s undercontrol of
10MD, provides the 32-bit word, half word
or byte wide'
data bus to and from the DEBI expansion interface.
Technical Reference Manual
CPU and control
ARM CPU &OPEN Bus
The ARM processor is fitted to adaughtercard which
connects to the system via one of the OPEN Bus
connectors (see OPEN
Buson page 2-16). The ARM 61 C
card contains the ARM, a60 MHz can oscillatortogether
with adivide by 2circuit based on a 74ACT74in order
to
ensure aclean symmetrical 30 MHz clock signal and a
74ACT08 AND gate.
Syst~m Clock generation
The masterclock source, clk64, is a64MHz signal which
is applied to 10MD ancfprovides all the system timing.
The DRAM timing generators use both edges of a32MHz
clock, which
is generated from the 64MHz by dividing by
two. The peripheral bus is clocked from the master clock
divided by 4(16MHz). The video RAM serial interface
uses 64MHz divided by 3to generate
sc which clocks the
VRAM serial ports at 21.33MHz using a
2:1 mark space
ratio. The VIDC20 pcJk signal must be the same
as sc
during video RAM datatransfer, but must be the same as
mclk during cursor DMA, VIDC20 programming (Nprog
activity), and sound DMA (if the VIDC20 sound system
is
being used).
In addition to clk64 there is a24M Hz clock source which
provides areference clock
to both VIDC20 and the
FOC37C665 device.
rOMO
Interrupt control logic and 10C timers
IOMD has anumberofinterrupt inputs which can be used
to generate irq and fiq interrupts.
In addition, there are
internal interrupts generated by the DMA channels, the
keyboard interface and the 10C timers 0and
1. Aset of
registers similar to those
in 10C allow the interrupt
sources to be controlled by the processor. Some IOC
r.egister bits are unused, and some pin polarities are
different to 10C. Refer to Figure 1.2for the register bit
allo.cations, and to Table
1.1 for the interrupt active
levels.
Table 1.1: Interrupt active polarities
Interrupt
Description
Npliq Podula fiq inpul. Levellriggered,
activalow
Npirq Podula Irq input. Levellriggered, aClive low
Nsintr Serial interrupt input. Level triggered. ac1ive low
Nscirq Level triggered, active low
<D
Nlintr Floppy inlerrupt requesl. Levellriggered, active low
Nindex 'Floppy disc index input. Falling edge Iriggered
lIyl;Jack Flyback Irom VIDe. rising edge Iriggered
Idrq Floppy drq inlerrupl. Levellriggered. active high
'pintr Prinler inlerrupt request. Rising edge triggered
System description
Issue 1, September 1994 1·3

Acorn Risc PC
Technical Reference Manual
Table 1.1: Interrupt active polarities
DMA
Description
Priority Channel
o(highest) Cursor and DRAM Video
,Sound chan. 0(VIDC sound
OUI and linear sound in)
2VRAM transfer
cyde
3Sound chan.:' (linear sound
OUI)
4DRAM and VRAM refresh
5
va DMA channels ('round robin belween channels 0 to 3)
6(lowest) ARM
Table 1.2: DMA channels priority
There are four general purpose 1/0 DMA channels, and
two sound channels.
In addition, there are two further
channels for video and cursor data. The DMA channels
have fixed priorities as shown below.
The state machine which controls bus activity has a
number
of points at Which arbitration for the bus takes
place. Arbitration always takes place while the processor
performs
an idle cycle'and before it starts amemory
access.
In addition, arbitration occurs during sequential
memory accesses
as follows:
DRAMNRAM -sequential bursts of
up to awords can
occur uninterrupted by DMA.
In the absence of DMA
requests these bursts can extend to 256 words.
•
ROM -uninterrupted burst accesses of up to 4words
can occur. If non-burst ROM is used, arbitration occurs
on every access.
•PROG -uninterrupted bursts of
up to 4words can
occurwhere the access
is to an 10MD internal register.
Where the access is to the VIDC control register,
arbitration occurs on every word.
1/0 - an 10ROIIOGT mechanism is used for
programmed 1/0 and (non-I/O) DMA can occur during
1/0 cycles.
I/O and sound DMA
The I/O and sound DMA channels have two sets of
pointers,
so that data transfers may be 'double buffered'
as
is the case with the MEMC1 asound DMA channel.
The DMA pointers consist of two pairs
(A and B) of 29-bit
current address registers, and 12 bit end pointers which
also have 2control bits
in them, The current and end
pointer addresses are inclusive addresses, and the end
address
is the address of the last transfer, which will
depend upon the transfer size. The current address
registers are divided into two fields. The lower 12 bits
form
an offset into a4K page. The upper 17 bits form a
static page number. The end register consists
of a12 bit
page offset
in the lower 12 bits of the register, and two
control bits in the most significant bits of the register.
Each channel also has an a.bit control register, and a
three bit status register. The control register is readable
and writable, and the status register
is read only. Five of
the control register bits (Inc[ 4:0)) control the amount by
which the current pointer is incremented after each
transfer. Another bit (D) controls the direction of transfer,
Control (RIW)
StetUI (Rj
Requeat (R)
Mllk(RIW)
Cleer(W)
StatUI (R)
Requeat (Al
Mnlk (Riw)
Statue (R)
Request (Rl
Meek (RIW)
Level triggered, active low @
I/O Control Regleter
IRO" Interrupt Regleter
FlO Interrupt Register
IROB Interrupt Register
(j) This signal is the fOE interrupt signal inverted.
®This signal is the Network card interrupt signal
inverted.
There is acontrol register which provides access to a
small number of I/O pins. These are used for the /2C
interface, and for the 10 chip interface. The 10 pin is held
low during reset,
and then tri-stated. The 1
2Cinterface
pins are tri-stated on reset. The registers are also shown
in Figure 1.2. The functionality of these registers is similar
to the corresponding registers
in laC, except it is not
possible to generate aFlO from the
10 1/0 bit, and not all
the bits
in the registers are implemented. Referto the lac
data sheet, and Figure 1.2for further detail.
Figure 1.2: I/O Control and Interrupt Registers
Two timers, the same as those in lac are provided,
which are clocked at the same 2MHz rate. Note that the
lac documentation is incorrect in stating that Tinterval =
latch/2j.LS, it should say (Iatch+1 )/2I-lS. Note also that if a
latch command is issued immediately after ago
command, the value latched may
be the new value, but
may be the old value of the counter. This also occurs
in
laC, and should therefore not be aproblem.
1-4 Issue
1, September 1994 System
description

Acorn Risc PC
and one bit (E) is used to enable and disable the channel.
The status bits, and the Cbit of the control register are
described later.
DMA transfers are constrained to asingle physical page
by the following mechanism. The bottom
12 bits (page
offset) ofthe current pointer is incremented on each DMA
transfer by the programmed increment, and is compared
to the bottom 12bits of the end pointer. The page number
is not incremented, and is not compared. This has the
effect that it is possible to program the end pointer to be
less than the initial pageoffset, causing the DMA address
to wrap around at the end of the page. This is unlikely to
be useful.
In order to implement the double buffering mechanism,
each pair of registers is used alternately. An interrupt is
raised when one of the pair completes its transfer. If the
other pair has been programmed by this time, DMA
continues using this pair.
Figure 1.3: DMA Address registers
(one set per channel)
28 1211 0
Page[16:0} IOHsel[11 :0] C!Jrrent A
31 30
11 0
~I
I
End[ll :0] End A
28
1211 0
Page[16:0] IOHset[11
:OJ
ClJrrent B
31 30 11
0
[I[g
IEnd[11:0] End B
7 6 540
~l
Inc(4:0] Control
III
Enable
Oir
Clear
210
@EEl
Status
~
AlB
Inl
Overrun
The increment field in the control register determines the
channel increment as follows:
00001 Byte
00010 Half-word
00100 Word
10000 Quad-word
The I/O
DMA channels support byte, half-word and word
transfers only. The VIDC sound channel can support
quad-word DMA, but only when DMA is to
VI DC, not
when
it is from the CO DEC. The increment has adifferent
meaning for the video channel (see later).
Technical Reference Manual
The direction bit in the control register defines the
direction of the DMA transfer. When set, the transfer is
from peripheral to memory. Sound channel auses this bit
to control whether VIDC sound output mode, or CODEC
sound input mode is
in use.
Each DMA channel is controlled by asimple state
machine. The state machine is able to run when the
enable bit is set. The current state
is visible in the status
register and these bits are read only. The AlB bit
indicates which pairof currenVend pointers is
in use. The
Int bit indicates when the channel
is requesting an
interrupt. The Overrun bit indicates when achannel has
stopped because
it finished atransfer, and the other
pointer pair had not been programmed. Writing a1to the
Cbit of the control register resets the state machine to
state 110. The Cbit
of the control register is self clearing
and always reads zero.'
The S(Stop) and L(Last) bits in each end registercontrol
the behaviour of the channel when transfer of abuffer
completes. The Sbit must be set if the TC pin
is to be
asserted at the
endof the buffer. The Lbit is an indication
that the next transfer on that buffer will be the last.
It is
normally set by 10MD, but must
be set by the ARM in the
case where the channel is being initialised for asingle
tran·sfer. For buffers that require more than one transfer,
the Lbit should be cleared when the end register is
written.
In Figure 1.4 the three bits shown beside each state
correspond to the three bits of the status register, and
directly reflect the state of the DMA state machine. At
reset, the state machine enters state 110. This state and
state
111 are the idle states in which no DMA transfers
occur. The transition between states occurs either
by a
buffer finishing,
or by the ARM programming the next
pointer pair. The current and end pointers must be
programmed
in that order, as it is the write to the end
pointerwhich actually causes the state transition.
In practice, acomplete DMA transaction is performed by
asoftware state machine, as shown
in Figure 1.5, where
N
is the buffer numberbeing transferred and LastN is the
buffer number of the last buffer to be transferred, which
should have the Stop bit set when programmed. When
the last buffer has been programmed in, and the next
interrupt happens, adummy value
is programmed into
the next buffer pair in order to clear the interrupt. The
foUowing interrupt happens after the last buffer has been
transferred, at which point DMA can be disabled and the
channel reallocated. When the Wait for Ibox is
encountered, the software checks the I(Int) bit:
if set, it
continues to the next step; if clear, the software exits and
waits for the next DMA interrupt. After abufferwith the S
bit set has been transferred, the hardware always enters
one of the idle states;
it never continues to the other
buffer. The scheme is designed to cope with all possible
cases of overrun.
System description
Issue 1, September 1994 1-5

Acorn Risc PC
Technical Reference Manual
Figure 1.4: Hardware DMA state machine diagram
Finished
(StopA)
Busy (Buff Aactive)
g(000)
IFiniShed
(not
StopA)
Finished
(StopB)
Busy (Buff Aactive)
Write Buff A ~ ~
------4
7Int Write Buff B
'\
/ BuffA 7
'" Finished (010)
T r.::~~BI
(110)
Idle or Write Buff B
~
(Write Buff A
Buff B
(001)
Busy (Buff Bactive)
~
nt ~
Buff B
(011 )
Busy (Buff Bactive)
Finished
Write Buff B
)
Idle or Write Buff A
Figure 1.5: Software DMA state machine diagram
Program BunB with
bun., N, C( wilh
garbago •N>LaslN
OIA
Wait lori,
chock .Illiu.
Program But1A with
butt.r N, or wilh
garbolgo K N>LaslN
Yo.
1-6 Issue
1, September 1994 System description

Acorn Risc PC
Additionally there is aset of interrupt registers for the
DMA channels. For each channel there
is amask bit, a
status bit, and arequest bit, the status bit being a
replication of the Ibit in the DMA state machine. There
are 6interrupting DMA channels in total, and the interrupt
registers are arranged such that there
is aDMA channel
per bit of each register, with 2bits per register spare, as
shown
in Figure 1.6.
In Figure 1.6, the DMA interrupt status register indicates
which channels have interrupts outstanding. Achannel
generates an interrupt when it reaches the end of the
current buffer. An interrupt will be generated
if the
relevant DMA interrupt mask
is enabled. The DMA
request register holds the logical AND of the DMA
interrupt status and DMA interrupt mask registers,
indicating which channels are requesting
an interrupt.
When using, for example, an 8-slot backplane where the
data lines are buffered by a'245 device or similar on the
backplane, IOMD provides an output enable signal
(PBOE) which can be programmed to
be active or
inactive during DMAs from peripheral to memory.
In this
way the '245 buffer can be
di~abled for DMAs from
'internal' peripherals, such
as the Network card, or
enabled for DMAs from 'external' peripherals on
expansion cards. To do this, the DMAEXT register
is
used. Bits 3:0 of the DMAEXT register map to //0 DMA
channels 3to
0, and setting the relevant bit to a 1
indicates that the peripheral
is external. There are no
DMAEXT bits for the sound DMA channel, as the sound
CODEC is always an on-board peripheral.
Figure 1.6: DMA Interrupt registers
DMA Interrupt request register (DMARQ)
IIIDMA ''G
ue"channolO
DMA request channel 1
DMA request channel 2
'-- DMA request channel 3
1...- DMA request sound chan. 0
1...- DMA request sound chan. 1
Technical Reference Manual
DMA Interrupt mask register (DMAMSK)
DMA Interrupt status register (DMAST)
DMA External register (DMAEXT)
System description
Issue 1, September 1994
.'
1-7

Acorn Risc PC
RegIsters
The following table lists the registers in IOMD. The
physical base address of these registers is &0320 0000,
the same
as the address of the IOC internal registers in
previous platforms. The size field indicates the width of
the register. although some bits may not be used in a
register.
Table 1.3: Register definitions
Technical Reference Manual
Name
Address
Size Read Write
Function
Reset state
IOCR 0
(8)
Status Control
110 ~ntrol
-1-
KBOOAT
4(8) Rx Data Tx Data Keyboard data -x-
KBOCR 8(8) Status Control Keyboard
~ntrol
-0-
IROSTA 10
(B)
Status
---
IROA status
IRORQA
14 (B)
Request Clear IROA requesVc:lear
-x-
IROMSKA 1B
(B)
Mask'
Mask
IRQAmask
-0-
IROSTB 20
(B)
Status .
'.
---
IROB status
IROROB 24
(B)
Request
---
IROB request
IROWoSKB 2B
(8) Mask Mask
IROBmask
-0-
FIOST 30
(8)
Status
--
FlO status
FlORO 34 (8) Request
---
FlO request
FIOMSK 38 (8) Mask Mask FlO mask -0-
TOLOW 40
(8)
Count Low Latch Low Timer 0low bits -x-
TOHIGH 44
(8) Count High Latch High Timer 0high bits -x-
TOGO
48 (B)
---
Go~mmand
Timer 0Go ~mmand
-x-
TOLAT
4C (8)
---
Latch ~mmand
Timer 0Lateh emd -x-
T1LOW 50
(8) Count Low Latch Low Timer 1low bits -x-
T1HIGH 54
(B) Count High Latch High Timer 1high bits -x-
T1GO 58 {(8)
---
Go~mmand
Timer 1Go oommand
-x-
T1LAT 5C (8)
---
Latch ~mmand Timer 1Lateh emd -x-
ROMCRO
80
(B)
RomCrO RomCrO ROM oontrol bank 0-0-
ROMCR1 84 (8) RomCr1 RomCr1 ROM oontrol bank 1-0-
ORAMCR 88
(8) OramCr OramCr DRAM oontrol -0-
VREFCR
8C
(8) VrelCr VrefCr
VRAM &refresh oontrol -0-
FSIZE 90
(8) Size Size Flybaek line size -x-
100
94
(B) 100
--
Chip ID no. low byte
101 98 (8)
101
--
Chip ID no. high byte
VERSION 9C (8) Version -Chip version number
IIOUSEX
AO
(16) MouseX MouseX Mouse Xposition -x-
IIOUSEY
A4 (16) MouseY MouseY Mouse Yposilion -x-
OMATCR Co (8) OmaTa OmaTa OACK timing
~ntrol
-x-
IOTCR
C4
(8) loTer loTer
110 liming ~ntrol
-x-
ECTCR C8 (8) EeTcr EeTcr Expansion card timing -x-
1-8 Issue 1, September 1994 System description

Acorn Risc PC
Table 1.3: Regislor definitions
Technical Reference Man~al
Name Address
Size Read
Wrlle
Funcllon
Reselslale
OMAEXT CC
(B)
OmaExl OmaExl OMA external control -x-
100CURA 100 (32) 100CurA 100CurA
110 OMA 0CurA -x-
100ENOA 104 (32) 100EndA 100EndA
110 OMA 0EndA -x-
100CURB 108 (32) 100CurB 100CurB
110 OMA 0CurB
·x-
100ENDB lOC (32) 100EndB 100EndB
110 OMA 0EndB -x-
100CR 110
(B)
10OControi 10OControi
va OMA 0Control
xOOOOOOO
100ST 114
(B)
100SIatus -.
va OMA 0Status xxxxxll0
101CURA 120 (32) 101CurA 101CurA
va OMA 1CurA
101ENOA 124 (32)
101 EndA 101EndA
110 OMA 1EndA
101CURB 128 (32) 101CurB 101CurB
va OMA 1CurB as
110 0
101ENOB 12C (32) 101EndB 101EndB
va OMA 1EndB
101CR 130 (8) 101Controi
10 1Control
va OMA 1Control
101ST 134 (8)
10 1Status
--
va OMA 1Sialus
102CURA 140 (32) 102CurA 102CurA
VO oMA 2CurA
102ENOA 144 (32) 102EndA 102EndA
VO OMA 2EndA
102CURB 148 (32) 102CurB 102CurB
110 OMA 2CurB as va 0
102ENOB 14C (32) 102EndB 102EndB
va OMA 2EndB
102CR 150 (8) 102Controi 102Controi
VO OMA 2Control
102ST 154 (8) 102SIalus -
110 OMA 2Stalus
103CURA 160 (32) 103CurA 103CurA
va DMA 3CurA
103ENOA ,164 (32) 103EndA 103EndA
110 DMA 3EpdA
103CURB 168 (32) 103CurB 103CurB
va OMA 3CurB as
110 0
103ENOB 16C (32) 103EndB 103EndB
VO OMA 3EndB
103CR 170 (8) 103Controi 103Controi
VO OMA 3Control
103ST 174
(B)
103SIalus
--
va oMA 3Stalus
SOOCURA 180 (32) SOOCurA SOOCurA Sound OMA 0CurA
SDOENOA 184 (32) SOOEndA SDOEndA Sound OMA 0EndA
SDOCURB 100
(32)
SDOCurB SDOCurB Sound DMA 0CurB as
110 0
SOOENOB 18C (32) SOOEndB SDOEndB Sound OMA 0EndB
SOOCR 190
(B)
SoOControl SOOControl Sound OMA 0Control
SOoST 194 (8) SOOStaluS
--
Sound OMA 0Slatus
S01CURA lAO (32) S01CurA S01CurA
Sound OMA 1CurA
So1ENOA lA4 (32) S01EndA SOlEndA
Sound OMA 1EndA
S01CURB lAB
(32) SOl CurB SOl CurB Sound OMA 1CurB as
110 0
S01ENOB lAC
(32) SolEndB
SolEndB
Sound OMA 1EndB
SOlCR lBO
(8) SOl Control SOl Control Sound
oMA 1Control
SOlST 184
(8) SO 1Stalus
--
Sound oMA 1Status
CURSCUR
lCO
(32) CursCur CursCur Cursor OMA CurrenI
·x·
CURSINIT lC4 (32) Curslnil Curslnil Cursor OMA Init
·x·
VIOCUR
100 (32)
VloCur
VloCur
Video oMA Currenl -x-
System description
Issue 1, September 1994
1-9

Acorn Risc PC Technical Reference Manual
Table 1.3: Register definitions
Name
Addross
Size
Read
Write Function
Reset slale
VIOENO 104
(32) VIOEnd
VIOEnd
Video OMA End
-x·
VIOSTART
108 (32) VIOStal1
VIOStan
VideO DMA SIan
·x·
VIOINIT
10C (32) VIDlnil
VIOlnil
Video DMA Inil
-x-
VIDCR
1EO (8) VIDConlrol VIOConlrol
Video DMA Control
xxOOOOOO
o MAST
1FO (8)
Stalus
.. -
OMA interrupt status
OMARQ
1F4
(8)
Request
---
OMA Interrupt request
OMAMSK 1F8 (8)
Mask Mask
OMA inlerrupt mask
.0-
Reset and power-on reset
10MD has an active high power on reset input, with
Schmitt level input,
and abidirectional active low reset
pin.
The reset pin is driven low during power on reset, and
may be
pulled low at anytimeto resetthe chip. The 10 I/O
bit is driven
low during reset. The POR bit in the" IRQA
interrupt register is set on power on reset. The JTAG"
interface is reset by an internal
power on reset cell in
10MD.
During reset, Nfiq
becomes an input and taking it low
invokes test features. Nfiq should be pulled up by an
external
pull-up resistor.
Memory system
The system physical memory map is shown below. For
the purposes of OM A, the VRAM appears in the whole of
the bottom half of the address space, as bit 28 of the
DMA address selects between DRAM and VRAM in this
implementation.
The total memory map is 512MBytes, as
only 29 address bits from
the ARM are connected to
10MD. However, this
does not prevent future platforms
having alarger physical memory map.
Figure 1.7: Rise PC System Memory map
1COO 0000
1800 0000
1000 0000
1400 0000
0800 0000
0400 0000
0300 0000
0200 0000
0100 0000
0000 0000
DRAM SIMM 1Bank 1
DRAM SIMM1
Bank 0
DRAM SIMMO Bank 1
DRAM SIMMO
Bank 0
EXlended address space (EASI cards)
Reserved
va including old podules and IOMO reg.
VRAM
Extension ROM
Main ROM
Hex address
2000 0000
Since each SIMM may have one or two banks on it, and
as each bankwill usually be less than
64MB, the physical
DRAM address
map may be discontiguous.
The primary use of the 1
2Cbus is to enable the CPU to
talk to the
PCF 8583, acombined battery-backed real
time clock
(RTC) and the CMOS RAM IC. The bus is also
tracked
to the expansion bus.
The
12C bus is a two-wire bus specified by Philips. The
two signals are clock and data, both of which are of the
open
collector type with a4k7 pull-up. .
The CPU
controls the bus by writing (& reading) to the I/O
control
register in 10MD (address &0320 0000), bit 0=
data, bit 1=clock. Note that the higherbits in this register
are used to
control other functions. The appropriate'
operating system calls (see RISe as 3Programmer's
Reference
Manua~ should be used to read or write to
devices on
FC bus.
A
1.2V rechargeable cell is used to provide the batte!)'
back-up. This istrickle charged from the +5v supply when
the computer is on.
PC and RTC
1-10
Issue 1, September 1994
System description

Acorn Risc PC
I/O address space
The 1/0 address space beginning at 0300 0000 is
allocated as shown in the
1/0 section and the podule
address space is the same as
in previous platforms.
However, the Extended Address Space interface
allocates 16MB per card.
There are two types of peripheral access supported by
10MD. PROG address space
is accessed with fixed
timing and the access cycles are not divisible by DMA.
True 1/0 address space accesses may be interrupted by
non I/O DMA. The 10MD internal PROG address space
is from 0320 0000 to 0324 0000 and this includes all
10MD internal registers. There
is also an external PROG
address space from 03400000 to 037F FFFF. Accesses
to 0340 0000 to 035F FFFF activate the Nprog pin.
Accesses to addresses from 0360 0000 to 037FFFFFdo
not activate the Nprog pin. This area is intended for
OPEN Bus second bus master system registers.
Accesses to addresses
in the range 0350000 to 035F
FFFF and 0370 0000
to 037F FFFF arbitrate for the
memory bus on quad word boundaries, and do not
arbitrate for the VIDC programming bus first. Accesses in
the range
0340 0000 to 034F FFFF and 0360 0000 to
036F FFFF arbitrate for the memory bus on every
accesses, and arbitrate for the VIDC data bus first. Thus
VIDC should be programmed at location 0340 0000,
as
this activates the Nprog pin, and arbitrates for the VIDC
programming bus at the start of the cycle.
Table 1.4: CAS/RAS mapping
Technical Reference Manual
True 1/0 address space is from 0300 0000 to 0400 0000
excluding those areas which are mapped to PROG space
as detailed above. Thare is also another area of
1/0
space from 0800 0000 to 1000 0000. The 1/0 address
map is detailed
in the section DEBI Expansion IIFon
page 1-19.
Accesses to SIO space
in the S1 to S3 area are assumed
to be internal peripherals by 10M
D, and will not assertthe
PBOE signal on a read, and accesses to S10 space in the
S4 to
S7 area are assumed to be externa~herals,
and will thus assert the PBOE signal. The PBOE signal is
always asserted when not reading.
RAM control
10MDwilldirectly control two standard 32-bitwide, 72-pin
SIMMS. Each SIMM has one
or two RAS lines, and 4
CAS lines, one for each byte in the word. Thus, 10MD has
4
RAS lines and 4CAS lines in total. In addition, 10MD
directly supports VRAM, and there is an additional RAS
line
to select the VRAM
There are 12 RA address lines, and 3control bits to
control address multiplexing options, meaning there are
8possible options, of which 4are considered useful, as
shown below. The most significant bit of the DRAM size
control
is only applicable for VRAM, and is therefore not
presentfor DRAM, and is assumed bythe hardware to be
z!3ro.
RA[11:0) 1
11
110 19
1817
16 Is
14
13
12 11 To
I
Size 000 (Size 00 for DRAM)
PArow
125 123 1 21 120
-119
118
117
116
.115
114
113 112
11M, 4M, and 16M DRAM
PA col I
24
12
2111
110
19 18 17 16
[ 5
14
13 12
I&1bank 1M VRAM
Size 001 (Size 01 lor DRAM)
PA row
125
123 1
21
1
11
119118 117
116 115
114 113 112
I256K DRAM &1bank
PAcol
I 24 122
111 110 1 9 18 17 16 15
14
13 12
-\ 256K VRAM
Size 010
PArow
125 123 121 120 119 118
117
116 115
114 113
112
I2bank VRAM (256K)
PA col
124 122
112
111
110
I9 18
17
16 15
14
13
I
Size 110
PArow
125 1
23
I 21 120
119 118
117
116
115
114
113
122
I2bank VRAM (1 M)
PA col
124
122 112
1
11
110
I9 18 17 16
-15
14
-, 31
System description Issue 1, September 1994 1-11

Acorn Risc PC
A[27:26] are decoded to select the DRAM bank, and
hence the appropriate RAS line. This means that the
physical memory map may be discontiguous if each bank
does not contain the maximum 64MB. Normally, the
VRAM used will be 256Kx32, or 256Kx64, with the two
banks interleaved on aword basis on the DRAM interiace
side (see video interiace section).
An a-bit register (DRAMCR) is provided to control the
DRAM row address options and
is shown below. Four
pairs of two bits control the DRAM row address mapping
for each RAM bank. Another control register (VREFCR)
is used to control the VRAM column address options
which will vary depending
on whether one or two
megabytes of VRAM are fitted. The VRAM control
register also contains the refresh timing information, and
is shown in Figure 1.11 on page 1-13. The format of the
DRAM control register is shown
in Figure 1.8. The
DRAMCR
is reset to zero when rOMD is reset.
Figure 1.9: Example DRAM control signals (read)
Technical Reference Manual
Figure 1.8: DRAM Control Register
DRAM (and VRAM) control and timing is controlled by a
state machine running at 32MHz. The DRAM interiace
supports page-mode DRAMs. S-cycles run at 16MHz,
and N-cycles take 2.5times the S-cycle time,
Le. they run
at 6.4MHz. This means that S-cycles take 2cycles ofthe
32M
Hz clock, and N-cyclestake 5cycles of the 32MHz
clock.
An example DRAM timing waveform is shown in
Figure 1.9. Note that the CAS signal is delayed by half a
32MHz clock cycle for awrite, to allow more set up time
for data into the RAM.,The column address is also
delayed by half a32MHz clock cycle during writes,
in
orderto ensure that there is enough column address hold
time.
32M Hz
mdk
Nmreq
Nras
Ncas
(Read)
Ra(11 :0) Row Col CoI+1 CoI+2 CoI+3
1-12 Issue 1J
September 1994
System description

Acorn Risc PC
Figure 1.10: Example DRAM control signals (write)
Technical Reference Manual
32MHz
mclk
Nmreq
Nras
Ncas
(Write)
Ra(11 :0)
Row Col CoI+1
DRAM refresh is performed using CAS-before-RAS
refresh. Arefresh control register (VREFCR) of which 2
bits are currently defined for refresh operation, is
provided to control the refresh rate. This register also
contains the VRAM control bits. The register
is reset to
zero when IOMo is reset. The refresh rate is derived from
the reference clock (64MHz),
and, can be set to 16 or
1281lS, or disabled. Unused bits in this register should be
written to
0, but their state is undefined when read,
including after reset. Thus bits
4, 2and 1are all
undefined on aread. DRAM refreshes are staggered by
IOMD, to minimise the instantaneous powerconsumption
required.
Figure 1.11; VRAM and Refresh Control
Register (VREFCR)
o
Rale
o
0000 •Refresh off
0001 •16uS
1000. 128uS
All other values undefinec
System description
Issue 1, September 1994 1-13

Acorn Rise PC
ROM control
Technical Reference Manual
Video and audio system
00 0 Brstl BrstO Sp2 Spl
Spo
IOMD will support two 16MB banks of ROM with
individually controllable timing parameters. The access
time can be varied from around 220nS downwards
in
steps of 31.25nS. In addition, support is provided for
burst mode ROMs which allow rapid accessto sequential
addresses controlled by AO and A1. Five control bits per
bank are used to control these parameters. Three bits
control the basic access speed, and two bits control
whether burst is used and the burst access speed.
In
burst mode, subsequent accesses are shorter than the
initial access time. There are two ROM control registers,
one for each ROM bank, with the bit allocation
as shown
in the diagram below. The ROM control registers
(ROMCRO and ROMCR1) are reset to zero when IOMD
is reset. Unlike machines based on MEMC1A, IOMD
allows writes to be made to the ROM areas. The ARM
MMU should be programmed to prevent writes to the
ROM space if the ROM area does not contain writable
memory such
as SRAM.
During sequential accesses to ROM, Nromcs will stay
low, and the ARM addresses change. Thus Nromcs
is a
combinatorial signal, and afalling edge on
it cannot be
relied upon. The timing of Nromcs
is the same for reads
and writes. Nromcs typically rises 0
to 5nS before mclk
falls
at the end of the cycle.
Figure 1.12: ROM Control Register,
one per ROM
bank (ROMCRO &ROMCR1)
7
.1
Burst speed
00", Burst off
01 '" 125nS
10", 93.7505
11", 62.5nS
o
Initial speed
000 - 218.75n8
001 '" 187.5nS
010 '" 156.25nS
011 '" 12505
100",93.75nS
101 '" 62.505
VIDC20 Video interface
The video system supports 1or 2MB of VRAM, but will
also work with DRAM. VIDC
is used in 32 bit DRAM
interface mode for DRAM or one bank of VRAM
(1 MB)
and 54 bit DRAM interface mode fortwo banks of VRAM
(2MB). Cursor, sound and programming information
come from the main data bus, as does the video data
when VRAM is not used. When used, the VRAM serial
ports connect directly to
VI DC's data input ports with the
main data bus isolated from the lower 32 bit SAM
data
port by four74ACT244buffers controlled by an active low
output enable signal (Nedoe) generated by rOMD. During
cursor DMA (horizontal retrace time), programming and
sound DMA the VRAM serial port is also disabled. When
both banks of VRAM are fitted,
nWE and nOE (or DT) are
used to interleavethe VRAM banks' databussesontothe
main system data bus on aword basis, using
A(2) to
select the required bank.
At the start of each frame, IOMD does afulltransferto the
VRAM, to initialise the video pointer in the SAM.
It then
does split transfers whenever needed, as indicated by
the qsf pin of the VRAM. The full transfer is done on the
last but one line of the flyback period. This is to ensure
that the VRAM serial port is loaded with new data if the
frame bufferhas been updated during flyback. To do this,
IOMD counts the flyback lines, and when the last line but
one
is reached, it does the transfer. The 8bit FSIZE
register
in IOMD is programmed with the number of
flyback lines minus
1.
The VRAM serial ports are clocked at 21.33MHz using a
'bursty' clock. When VIDC20 asserts vidrq the response
from IOMD
is to assert vidak and to clock the VRAM
serial port clock sc four times. The VRAM serial clock
is
derived from the 54MHz reference clock by dividing by 3,
such that the clock is high for 264MHz periods, and low
for one 64MHz period. Data
is clocked out of the VRAM
serial port on the rising edge of sc and is clocked into
VIDe on the falling edge of pclk, which is the same as sc
during video data transfers (see Figure 1.13). pclk
is the
same
as mclk during cursor, programming and sound
transfers. Achange
on the qsf output from the VRAM
indicates that atransfer cycle
is required. The current
video pointer VCUR
is then incremented by the split port
SAM length, and atransfercycle is requested to the main
bus arbiter.
1·14
Issue 1, September 1994
System description

Acorn Risc PC
Technical Reference Manual
.Figure 1.13: VRAM clock signals
pclk
Data clocked into
VIDC on falling edge
15nS
data
Data clocked out
of SAM on
rising edge l
310$
1·'--·1
t-----i
~ ~
vidack
Using a21.33MHz interface to VIDC gives atheoretical
peak bandwidth from the frame buffer to the display of
as.33MB/sec for a 1MB VRAM machine using a32-bit
interface, and 170.66MB/secfor a2MB VRAM machine,
using the 64 bit interface. However,
in practice the overall
system bandwidth requirements mean thatthe sustained
best case maximum is 80 MB/sec and 160 M8/sec
respectively and in order to provide asafety margin, the
bandwidth limit file stored in the 1800t directory on the
hard disc sets the maximum bandwidths to
76 M8/sec
and 152 MB/sec respectively.
Cursor DMA
The cursor DMA channel is controlled by two 29 bit
registers: inn and current. Data
is transferred from the
current register address in quad words under control of:
vidrq, vidak and vnc. The init register
is copied to the
current register during flyback. There is no control
register for this channel and hence no interrupts may
be
generated. It is enabled and disabled with the video
transferchannel. Cursordatacan be held in eitherVRAM
or DRAM. The format of the cursor registers
is shown in
the IOMD register definition section.
Video DMA
The video transferchannel is similar in structure to that of
the older MEMC1 adevice used in previous platforms and
is controlled by start, end, initand current registers which
are all 32 bits wide. Please refer to the section on IOMD
for alist of all 10MD's registers.
VIDStart
is programmed with the address of the start of
memory used for the screen buffer and VIDEnd
is
programmed with the address of the last transfer of the
video buffer memory. Thus it equals the address of the
end of the video buffer, minus the transfer size,
Le. quad
word
(16 bytes) in DRAM mode orthe half-SAM length in
VRAM mode. One bank of 1Mbyte VRAM made up from
4off 2Mbit (256K"8) VRAMs has ahalf-SAM length of
1"4"51212.1024 bytes. Two banks have ahalf-SAM
length of
2"4"51212.2048 bytes.
The addresses for the start and end of the video buffer
memory have the following restrictions on their values:
They must lie within the bounds of asingle16MB
aligned block in the physical address space.
"
In D RAM mode they must each be on a quad word
boundary
System description Issue 1, September 1994 1-15

Acorn Risc PC
• In VRAM mode, they must each be on ahalf-SAM
boundary and the buffer size must be amultiple of 2
times the half-SAM length
(Le. W4096 bytes for 2
banks of VRAM and
W2048 for the 1bank case).
Note the VIDStart and VIDEnd values written to IOMDwill
always differ by an odd number of half-SAM lengths
in
VRAM mode due to VIDEnd being programmed with the
screen memory end address less the half-SAM length
as
mentioned above.
The video init (VIDlnit) register
is programmed with the
address of the start of the screen data to be displayed,
Le. the address of the first pixel in the frame. This address
must be amultiple of Nbytes where N
is 16 (Le. 4words)
in DRAM mode, 8 (2 words) on 2bank VRAM machines,
and 4
(1 word) on 1bank VRAM machines. It is
recommended that addresses are aligned to 16 byte
boundaries to ensure compatibility with all possible video
configurations. However, finer address resolution in
VRAM modes would allow, for example, finer horizontal
scrolling to be performed
in certain specialist
applications.
NB Older platforms based on MEMC1NIDC1 also have
alignment restrictions of 16 bytes
on VIDlnit.
During flyback, the current register, VIDCur,
is initialised
to VIDlnit. VIDCur then increments by Inc (VIDCR[4:0J)
until either the end of the frame data,
or the end of the
video buffer area is reached.
In the latter case VIDCur is
reloaded with the value in VIDStart, and continues to: '
increment from there,
Le. the data for the frame is
wrapped around within the physical memory area defined
by
VI DStart and VIDEnd. This mechanism allows for
efficient vertical scrolling of the video display.
Video address incrementing
The video transfer DMA channel in IOMD generates the
VRAM transfer addresses and is designed to use VRAMs
with split SAM ports. On
eCjch split transfer, one, half of
the SAM
is loaded with new data and so the video
increment is the half SAM
lengt,h. The video start'and end
addresses must therefore be on half-SAM boundaries.
If the VIDlnit register is equal to or greater than the
VIDEnd register, implying the frame start address
is
somewhere in the last half-SAM of the video buffer, then
the video last bit
in the VIDlnit register will need to be set
manually. This is because the comparison
as to whet~er
atransfer is the last in the buffer is always done during a
video transfer cycle, for the next video transfer
Cycle.
In VRAM mode, bits 7:0 of the video address are not
compared when checking VIDCur against VIDEnd. The
number of bits compared depends upon the value
programmed into Inc,
if programmed to 1, meaning 256
bytes, then all of bits 23:8 are compared,
if 2(512 bytes),
bits 23:9 are compared,
if 4only bits 23:1 0are compared,
and
so on. This ensures that the current pointer when
compared with the end address, will always match the
end address, even if it is not aligned on ahalf-SAM
boundary. Generally,
if the increment is 2Nbytes, then
bits 23:N will be compared:
Increment
in bytes =2N=Inc x256
Technical Reference Manual
N • log2(lnc'256) •8+log2{lnc), where Nis the least
significant bit compared.
Note, Inc must always be apower of
2, Le. there must
only ever be one bit set in the increment field in
VI OCR.
VIDCur is incremented by the half-length ofthe SAM port
after each transfer. When the VRAM has swapped to the
other half of the SAM port, the next transfer cycle is
requested by the qsf pin changing state. Transfer cycles
consist of single VRAM accesses, with aspecial
combination of control signals applied to the VRAM. The
reader
is referred to asuitable VRAM datasheet for full
SAM transfer cycle details.
Since 4bYtes are transferred at atime
in a 1MByte VRAM
machine, and 8bytes are transferred
at atime in a
2MByte VRAM machine, the value
in the increment field
is the half-SAM length (256) multiplied by 41256 for
1MByte VRAM, or muttiplied by 8/256 for a2MByte
VRAM machine. So for 1MByte of VRAM, the video
increment
is 256 x 4/256 =4and for 2MByte of VRAM it
is 256 x 8/256 = 8.
When IOMD is used in DRAM mode it transfers quad
words and so Inc
is programmed with 16.
Frequency Synthesizer
The Frequency synthesizer which generates the pixel
clock for VIDC is based on aPhase Locked Loop (PLL).
This consists of three parts; aVoltage Controlled
Oscillator (VCO) built around the 74AC04 hex inverter
IC32 with suitable feedback components R197 and
C141, aPhase Comparator (implemented digitally inside
VI DC) and aLoop Filter which is essentially alow pass
fitter to smooth and integrate the phase comparator
output (Pcomp) consisting of R183, R186 and C122.
Pcomp appears as shown
in Figure 1.15 and the area
above
OV minus the area below OV when filtered provides
an average DC bias voltage to the VCO. The phase
comparator will cause.the positive Pcomp pulse and
therefore the average
DC bias voltage to increase slightly
if it detects that Vclkin is falling behind Refclk, or
decrease slightly if
it detects that Vclkin is speeding up
over Refclk. By programming the
r, vand nregisters in
VIDC the Pixclk output can be varied anywhere from 8Mz
up to
in excess of 110 MHz. The comparison frequency
is determined by the ratio: 2412r and the resulting pixel
clock
is equal to 24 x(Vir) x(1/n) MHz.
The VCO relies on the change
in propagation delay of a
74AC04 inverter with supply voltage. However, the
variation
in propagation delay of these parts with
temperature and batch
is large and thus an operational
safety margin is buitt
in to the circuit. At the time of
printing, the values of R197 and C141 around the
74AC04 have been chosen to allow best case operation
up to 150 MHz, with machines production line tested to
125 MHz
in order to guarantee operation up to 110 MHz.
Figure 1.16shows the typical VCO outputfrequency as a
function of input voltage.
1·16 Issue
1, September 1994
System description

Acorn Risc PC
Technical Reference Manual
VCII<in
------r------.,
Figure 1.14: VIDC Phase Comparator Block
Diagram
+2v f-_...,
PComp
--------{
Refclk (24 MHz)
-------...,
+2r f--...J
+n
Phase
Compare
Pixclk
Audio &1
25
circuitry
The standard sound system is based on the VIDC 1a
stereo sound hardware as used
in previous platforms.
External analogue anti-alias fillers are used which are
optimised for a20kHz sample rate. The high quality
sound output is available from a3.5mm stereo jack
socket at the rear
of the machine which will directly drive
plHsonal stereo headphones, or, alternatively, an
amplifier and speakers. One internal speaker
is fitted, to
provide mono audio. When ajack is inserted into the
headphone socket the internal speaker is muted.
Two auxiliary audio connectors and ahigh quality 16 bit
Sound output on the main PCB cater for future upgrades
(refer to Interface specifications on page
2-1 for details).
Figure 1.15: Phase Comparator output from
VIDC
20
,-_u
Period .. 1 Phase
Comparison Frequency Difference
Figure 1.16: VCO frequency against control
voltage
ro<+___ .
150 ~
~100················································· [:7~ .
&V
··························V··························· .
50 t---j----:7"~--j---t---+---l---1
/~ :.
o -F--~~-+---I-~-.;..--+----4--"""
1.5 22.5 33.5 44.5
Vin (VOIIS)
,
VIDe sound system hardware
VIDC contains an independent sound channel consisting
of the following components: Afour-word FIFO buffers
16
a-bit sound samples, with aDMA request issued
whenever the last byte is consumed from the FIFO. The
sample bytes are read out at aconstant sample rate
programmed into the a-bit Audio Frequency Register.
This may be programmed to allow samples to be output
synchronously at any integer value between 6and 255
microsecond intervals.
The sample data bytes are treated
as sign plus 7-bit
logarithmic magnitude and, after exponential digital to
analogue conversion, de-glitching and sign-bit steering,
are output as acurrent at one of the audio output pins to
be integrated and filtered extflrnally.
VIDC also contains abank of eight stereo image position
registers, each of three bits. These eight registers are
sequenced through at the sample rate with the first
register synchronised
to the first byte clocked out of the
FIFO. Every sample time
is divided into eight time slots
and the 3-bit image value programmed for each register
is used to pulse width modulate the output amplitude
between the LEFT and RIGHT audio current outputs
in
multiples of time slot subdivisions. This allows the signal
to be spatially positioned
in one of seven stereo image
positions.
IOMD sound system hardware
Please refer to I/O and sound DMA on page 1-4 which
describes the operation of both the
110 and Sound DMA
channels.
System description
Issue 1, September 1994 1·17

Acorn Risc PC
Peripheral control
The PC combochip provides all the peripheral interlaces:
IDE, Serial, Parallel and Floppy, with 10MDproviding the
keyboard and mouse circuitry. Full details
of all these are
given
in Interface specifications on page 2-1.
I/O bus
The I/O bus on the Risc PC is 32 bits wide, of which the
lower 16 bits pass through 10MD, and the upper 16 bits
are latched and buffered by an external latch. Logic
in
10MD is used to position bytes and half words to the
appropriate position within the word, for transfer to and
from memory. The lower 16 bits from 10MD connect
directly to the on-board peripherals, and via a
bidirectional bufferto the lower 16 bits of the podule bus.
10MD latches the lower 16 bits of the word,
and provides
control signals for the external latch and buffer.
The bus supports DMA, and the signals are similar
to a
cut-down PC-AT bus (i.e. Intel-style control signals, read
strobe, write strobe, DACK etc). The bus
is clocked at
16MHz, but anumber of clockticks are required for each
transfer.
In addition, the bus emulates the I/O bus of
previous Acorn 32-bit machines.
An 8MHz 10RQIIOGT
style interface, and the 8MHz 'S-space' interface signl;lls
are provided.
I/O Cycle types
There are three types of access timing to the 110 bus, the
first two of which are present
in M EMC1 allOC system,
and the other one being new to 10MD. The first (8MHz
fixed)
is the IOC controlled type, in which one of four'
timings is selected by bits 20:19 of the address. These
cycles are based on
an 8MHz clock (externally derived
c1kS). The second type of access (8MHz variable) is also
based
on an SMHz clock, and uses the Niorq and Niogt
signals, which are referenced'lo the ref8m pin. The third
type of access (16MHz) is referenced to CLK16, the
16MHz
110 clock, and is used for on-board peripherals
(e.g. combo), for DACK timing to peripherals using DMA,
and for the extended address space expansion cards..
The basic timings used for these devices are controlled
by the
110, DMA and expansion card timing control .
registers (IOTCR, DMATCR, and ECTCR respectively).
On-board I/O peripherals such
as the combo chip ant!
DMA have four timings available (types Ato D), and
expansion cards have only two timings available, these
being types Aand C. .
Various different cycle timings may
be selected for the
16MHz accesses. These are known
as types A to D,
where type Dis the fastest this has half a16MHz tick'of
setup and hold of CS/DACK relative to lOR/lOW and a
pulse-width of one 16MHz tick
on lOR/lOW. Type C i§
similar, but has apulse-width of two 16MHz ticks for
lOR/lOW. Type Bhas one and ahalf clock ticks
of setup
and half atick of hold of CS/DACK to lOR/lOW, and a 3
tick wide 10RIIOW pulse, and type Ahas one and ahalf
Technical.Reference Manual
ticks of setup and hold of CS/DACK to IORIIOW, and a
four tick wide 10RIIOW pulse. Theirtimings are shown in
Table 1.7on page 1-24. Expansion cards have only
timings Aand Cavailable to them. The fastest
two types
reduce the minimum CS/DACKwidth
to one tickfor DMA,
whilst keeping it 2ticks for programmed I/O.
The slower
two timings have aminimum of 2ticks high for both CS
and DACK.
The point
at which the DMA request must go away to
ensure that another DMA does not happen varies
depending upon whether the DMA is aread
or awrite,
and upon the relative phase of rclk and
c1k16 at the time.
For reliability, however, it is recommended that DREQ is
removed
by the time DACK rises again.
1-18
Issue 1, September 1994 System
description