Acromag PMC440 Series User manual

Series PMC440 PCI Mezzanine Card
32-Channel Isolated Digital Input Module
With Interrupts
USER’S MANUAL
ACROMAG INCORPORATED
30765 South Wixom Road
P.O. BOX 437
Wixom, MI 48393-7037 U.S.A.
Tel: [phone]
Fax: [phone]
Copyright 2000, Acromag, Inc., Printed in the USA.
Data and specifications are subject to change without notice.
8500-673-A00K000
retired

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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The information contained in this manual is subject to change
without notice. Acromag, Inc. makes no warranty of any kind with
regard to this material, including, but not limited to, the implied
warranties of merchantabilityand fitness for a particular purpose.
Further, Acromag, Inc. assumes no responsibility for any errors that
mayappear in this manual and makes no commitment to update, or
keep current, the information contained in this manual. No part of
this manual may be copied or reproduced in any form, without the
prior written consent of Acromag, Inc.
Table of Contents Page
1.0 GENERAL INFORMATION............................................... 2
KEY PMC440 FEATURES................................................ 2
PCI MEZZANINE CARD INTERFACE FEATURES......... 3
SIGNAL INTERFACE PRODUCTS.................................. 3
PMC MODULE ActiveX CONTROL SOFTWARE............ 3
PMC MODULE VxWORKS SOFTWARE……….............. 3
2.0 PREPARATION FOR USE................................................ 3
UNPACKING AND INSPECTION..................................... 3
CARD CAGE CONSIDERATIONS................................... 3
BOARD CONFIGURATION.............................................. 3
CONNECTORS................................................................. 4
Front Panel Field I/O Connector P1............................... 4
Noise and Grounding Considerations............................. 4
PCI Local Bus Connector ........................………........... 4
3.0 PROGRAMMING INFORMATION.................................... 5
PCI CONFIGURATION ADDRESS SPACE……...……... 5
CONFIGURATION REGISTERS……………...………….. 5
MEMORY MAP….............................................................. 5
Standard (Default) Mode Memory Map........................... 6
Enhanced Mode Memory Maps...................................... 6
REGISTER DEFINITIONS................................................ 7
THE EFFECT OF RESET................................................. 10
PMC440 PROGRAMMING CONSIDERATIONS..........… 11
Basic Input Operation..................................................... 11
Enhanced Operating Mode............................................. 11
Event Sensing................................................................ 11
Change-Of-State Detection............................................ 11
Debounce Control.......................................................... 11
Interrupt Generation....................................................... 12
Programming Example................................................... 12
4.0 THEORY OF OPERATION............................................... 13
PMC440 OPERATION...................................................... 13
PMC INTERFACE LOGIC…............................................. 13
PMC MODULE SOFTWARE............................................ 14
5.0 SERVICE AND REPAIR.................................................... 14
SERVICE AND REPAIR ASSISTANCE........................... 14
PRELIMINARY SERVICE PROCEDURE......................... 14
6.0 SPECIFICATIONS............................................................. 14
PHYSICAL……………………............................................ 14
ENVIRONMENTAL…………………………………………. 14
INPUTS.............................................................................. 15
PCI LOCAL BUS INTERFACE…………........................... 15
APPENDIX......................................................................... 16
CABLE, SCSI-2 to Flat Ribbon (Shielded):
MODEL 5028-187………................................................... 16
TERMINATION PANEL: MODEL 5025-552..................... 16
DRAWINGS Page
4501-859 PMC MECHANICAL ASSEMBLY..............…... 17
4501-869 PMC440 FIELD CONNECTIONS.................... 18
4501-870 PMC440 BLOCK DIAGRAM.................…........ 19
4501-758 CABLE, SCSI-2 to Flat Ribbon (Shielded)
5028-187…..……………….............................. 20
4501-464 TERMINATION PANEL 5025-552................... 21
IMPORTANT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible adverse
effects of power, wiring, component, sensor, or software failures in
designing any type of control or monitoring system. This is
especially important where economic property loss or human life is
involved. It is important that the user employ satisfactory overall
system design. It is agreed between the Buyer and Acromag, that
this is the Buyer's responsibility.
1.0 GENERAL INFORMATION
The PCI Mezzanine Card (PMC) Series PMC440 has 32-
channels of isolated digital inputs. Inputs of this module are bipolar
and can be used to sense positive or negative voltages in 3 ranges
according to the model:
MODEL INPUT RANGE THRESHOLD
PMC440-1 ±4V to ±18V DC or AC peak ±4V Maximum
PMC440-2 ±16 to ±40V DC or AC peak ±16V Maximum
PMC440-3 ±38 to ±60V DC or AC peak ±38V Maximum
The inputs normallyfunction as independent input level
detectors without interrupts. However, each input line includes built-
in event sense circuitry with programmable polarity, debounce, and
interrupt support. Inputs also include hysteresis for increased noise
immunity. The PMC440 utilizes state of the art Surface-Mounted
Technology (SMT) to achieve its wide functionality and is an ideal
choice for a wide range of industrial I/O applications that require a
high-density, highly reliable, high-performance interface at a low
cost.
KEY PMC440 FEATURES
•High Channel Count - Provides programmable monitor and
control of 32 optically-isolated input points
•Wide Range Bipolar Input Voltage - Three model ranges
provide interface capabilityfor bipolar voltages from ±4 to ±60V
DC or AC peak (see Specifications section).
•Optically Isolated - Individual bipolar opto-couplers provide
isolation. There are four groups (ports) of 8 channels each
which include separate port commons to ensure port-to-port
isolation. Individual ports are isolated from each other and from
the logic.
•Programmable Polarity Event Interrupts - Interrupts are
software programmable for positive (low-to-high) or negative
(high-to-low) input level transitions on all 32 channels. Using
two channels per input, change-of-state transitions may also be
configured.
•Input Hysteresis - Isolated inputs include hysteresis for
increased noise immunity.
•Programmable Debounce - The event sense input circuitry
includes programmable debounce times for all 32 channels.
Debounce time is the duration of time that must pass before
the input transition is recognized as valid at the ASIC input.
This helps prevent false events and increases noise immunity.
•Reverse Polarity Protection - Bipolar inputs are not polarized
and are inherently reverse polarity protected.
•No Configuration Jumpers or Switches - All configuration is
performed through software commands with no internal
jumpers to configure or switches to set.

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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•ASIC Based Monitor - State of the art ASIC (Application
Specific Integrated Circuit from Ziatech Corporation) provides
the 32 channel input and event functionality.
PCI MEZZANINE CARD INTERFACE FEATURES
•High density - Single-width PMC Target module.
•Field Connections – All digital inputs and common
connections are made through a single 50-pin SCSI-2 front
panel I/O connector.
•8-bit I/O - Port register Read/Write is performed through 32-
bit, 16-bit, or 8-bit data transfer cycles in the PCI memory
space, however, only8-bits will contain valid port data in each
access.
•Compatibility – IEEE P1386.1 compliant PMC module which
complies to PCI Local Bus Specification Revision 2.2.
Provides one multifunction interrupt. 5V signaling compliant
and 3.3V signaling tolerant.
SIGNAL INTERFACE PRODUCTS
(See Appendixfor more information on compatible products)
This PMC Module will mate directly to any standard PMC
carrier/CPU board that supports one single width PMC mezzanine
module. Once connected, the module is accessed via a 50 pin front
panel connector.
The cables and termination panels, described in the following
paragraphs, are also available. For optimum performance with the
PMC440 digital input module, use of the shortest possible length of
shielded input cable is recommended.
Cables:
Model 5025-187 (SCSI-2 to Flat Ribbon Cable, Shielded): A
round 50 conductor shielded cable with a male SCSI-2
connector at one end and a flat female ribbon connector at the
other end. The cable is used for connecting the PMC440
module to Model 5025-552 termination panels.
Termination Panel:
Model 5025-552: DIN-rail mountable panel provides 50 screw
terminals for universal field I/O termination. Connects to
Acromag PMC440, via SCSI-2 to Flat Ribbon Cable, Shielded
(Model 5028-187).
PMC MODULE ActiveX CONTROL SOFTWARE
Acromag provides a software product (sold separately)
consisting of PMC module ActiveX (Object Linking and Embedding)
controls for Windows 98, 95, ME, 2000 and Windows NT
compatible application programs (Model PMCSW- ATX, MSDOS
format). This software provides individual controls that allow
Acromag PMC modules to be easily integrated into Windows
application programs, such as Visual C++, Visual Basic,
MicrosoftOffice97 applications and others. The ActiveX
controls provide a high-level interface to PMC modules, eliminating
the need to perform low-level reads/writes of registers, and the
writing of interrupt handlers—all the complicated details of
programming are handled by the ActiveX controls. These functions
consist of an ActiveX control for each Acromag PMC module.
PMC MODULE VxWORKS SOFTWARE
Acromag provides a software product (sold separately)
consisting of PMC module VxWorkslibraries. This software
(Model PMCSW-API-VXW, MSDOS format) is composed of
VxWorks(real time operating system) libraries for all Acromag
PMC modules. The software is implemented as a library of “C”
functions which link with existing user code to make possible simple
control of all Acromag PMC modules.
2.0 PREPARATION FOR USE
UNPACKING AND INSPECTION
Upon receipt of this product, inspect the shipping carton for
evidence of mishandling during transit. If the shipping carton is
badlydamaged or water stained, request that the carrier's agent be
present when the carton is opened. If the carrier's agent is absent
when the carton is opened and the contents of the carton are
damaged, keep the carton and packing material for the agent's
inspection.
For repairs to a product damaged in shipment, refer to the
Acromag Service Policy to obtain return instructions. It is suggested
that salvageable shipping cartons and packing material be saved for
future use in the event the product must be shipped.
This board is physically protected with
packing material and electrically
protected with an anti-static bag
during shipment. However, it is
recommended that the board be
visually inspected for evidence of
mishandling prior to applying power.
The board utilizes static-sensitive
components and should only be
handled at a static-safe workstation.
CARD CAGE CONSIDERATIONS
Refer to the specifications for loading and power requirements.
Be sure that the system power supplies are able to accommodate
the power requirements of the carrier board, plus the installed IP
modules, within the voltage tolerances specified.
IMPORTANT: Adequate air circulation must be provided to prevent
a temperature rise above the maximum operating temperature.
The dense packing of the PMC modules to the carrier/CPU
board restricts air flow within the card cage and is cause for
concern. Adequate air circulation must be provided to prevent a
temperature rise above the maximum operating temperature and to
prolong the life of the electronics. If the installation is in an industrial
environment and the board is exposed to environmental air, careful
consideration should be given to air-filtering.
BOARD CONFIGURATION
Power should be removed from the board when installing PMC
modules, cables, termination panels, and field wiring. Refer to
Mechanical Assembly Drawing 4501-859 and the following sections

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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for configuration and assemblyinstructions. Model PMC440 digital
input boards have no hardware jumpers or switches to configure.
CONNECTORS
Front Panel Field I/O Connector P1
The front panel connector P1 provides the field I/O interface
connections. The front panel connector is a SCSI-2 50-pin female
connector (AMP 787082-5 or equivalent) employing latch blocks and
30 micron gold in the mating area (per MIL-G-45204, Type II, Grade
C). Connects to Acromag termination panel 5025-552 from the front
panel via round shielded cable (Model 5028-187).
Front panel connector P1 pin assignments are shown in (Table
2.1).
Table 2.1: PMC440 Field I/O Pin Connections (P1)
Pin Description Number Pin Description Number
IN00 1 IN16 21
IN01 2 IN17 22
PIN02 3 PIN18 23
OIN03 4 OIN19 24
RNC 5 RNC 25
TIN04 6 TIN20 26
IN05 7 IN21 27
0IN06 8 2IN22 28
IN07 9 IN23 29
COM0 10 COM2 30
IN08 11 IN24 31
IN09 12 IN25 32
PIN10 13 PIN26 33
OIN11 14 OIN27 34
RNC 15 RNC 35
TIN12 16 TIN28 36
IN13 17 IN29 37
1IN14 18 3IN30 38
IN15 19 IN31 39
COM1 20 COM3 40
No Connection 41
No Connection 42
No Connection 43
No Connection 44
No Connection 45
No Connection 46
No Connection 47
No Connection 48
No Connection 49
No Connection 50
Input channels are divided into four ports of eight channels
each. Channels of a port share a common signal connection with
each other. Isolation is provided between ports and between each
port and the PMC logic. With respect to interrupt generation and
events, event polarities maybe defined as positive (low-to-high), or
negative (high-to-low) for individual nibbles (groups of 4 input lines,
or half ports). Change-of-State detection would require 2 input
channels--one detecting positive events, one detecting negative
events.
Note that the inputs of this device are bipolar, and may be
connected in any direction with respect to the port common.
Further, do not confuse port commons with signal ground. Refer to
Drawing 4501-869 for example input connections.
Noise and Grounding Considerations
Input lines of the PMC440 are optically isolated between the
logic and field input connections. Likewise, separate port commons
facilitate port-to-port isolation. Consequently, the field I/O
connections are isolated from the carrier/CPU board and backplane,
thus minimizing the negative effects of ground bounce, impedance
drops, and switching transients. However, care should be taken in
designing installations to avoid inadvertent isolation bridges, noise
pickup, isolation voltage clearance violations, equipment failure, or
ground loops.
PCI Local Bus Connector
The PMC440 module provides a 32-bit PCI interface to the
carrier via two 64 pin connectors. These connectors are 64-pin
female receptacle header (AMP 120527-1 or equivalent) which
mates to the male connector of the carrier/CPU board (AMP
120521-1 or equivalent). This provides excellent connection integrity
and utilizes gold-plating in the mating area. Threaded metric screws
and spacers are supplied with the PMC module to provide additional
stability for harsh environments (see Drawing 4501-859 for
assembly details). The pin assignments of the PCI local bus
connector are standard for all PMC modules according to the PCI
Mezzanine Card Specification (see Tables 2.2 and 2.3).
Table 2.2: PMC Connector Pin Assignments for J1 (32-bit PCI)
Signal Name Pin # Signal Name Pin #
TCK 1 -12V 2
GND 3 INTA# 4
INTB# 5INTC# 6
BUSMODE1# 7 +5V 8
INTD# 9PCI-RSVD* 10
GND 11 PCI-RSVD* 12
CLK 13 GND 14
GND 15 GNT# 16
REQ# 17 +5V 18
V(I/O) 19 AD[31] 20
AD[28] 21 AD[27] 22
AD[25] 23 GND 24
GND 25 C/BE[3]# 26
AD[22] 27 AD[21] 28
AD[19] 29 +5V 30
V(I/O) 31 AD[17] 32
FRAME# 33 GND 34
GND 35 IRDY# 36
DEVSEL# 37 +5V 38
GND 39 LOCK# 40
SDONE# 41 SBO# 42
PAR 43 GND 44
V(I/O) 45 AD[15] 46
AD[12] 47 AD[11] 48
AD[09] 49 +5V 50
GND 51 C/BE[0]# 52
AD[06] 53 AD[05] 54
AD[04] 55 GND 56
V(I/O) 57 AD[03] 58
AD[02] 59 AD[01] 60
AD[00] 61 +5V 62
GND 63 REQ64# 64
# Indicates that the signal is active low.

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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BOLD ITALIC Signals are NOT USED by this PMC Model.
Table 2.3: PMC Connector Pin Assignments for J2 (32-bit PCI)
Signal Name Pin # Signal Name Pin #
+12V 1 TRST# 2
TMS 3TDO 4
TDI 5GND6
GND 7 PCI-RSVD* 8
PCI-RSVD* 9PCI-RSVD* 10
BUSMODE2# 11 +3.3V 12
RST# 13 BUSMODE3# 14
+3.3V 15 BUSMODE4# 16
PCI-RSVD* 17 GND 18
AD[30] 19 AD[29] 20
GND 21 AD[26] 22
AD[24] 23 +3.3V 24
IDSEL 25 AD[23] 26
+3.3V 27 AD[20] 28
AD[18] 29 +GND 30
AD[16] 31 C/BE[2]# 32
GND 33 PCI-RSVD 34
TRDY# 35 +3.3V 36
GND 37 STOP# 38
PERR# 39 GND 40
+3.3V 41 SERR# 42
C/BE[1]# 43 GND 44
AD[14] 45 AD[13] 46
GND 47 AD[10] 48
AD[08] 49 +3.3V 50
AD[07] 51 PCI-RSVD 52
+3.3V 53 PCI-RSVD 54
PCI-RSVD 55 GND 56
PCI-RSVD 57 PCI-RSVD 58
GND 59 PCI-RSVD 60
ACK64# 61 +3.3V 62
GND 63 PCI-RSVD 64
# Indicates that the signal is active low.
BOLD ITALIC Signals are NOT USED by this PMC Model.
3.0 PROGRAMMING INFORMATION
This Section provides the specific information necessary to
program and operate the PMC440 module.
This Acromag PMC440 is a PCI Local Bus Specification version
2.2 compliant PCI bus target onlyPMC module. The carrier/CPU
connects a PCI host bus to the PMC module.
The PCI bus is defined to address three distinct address
spaces: I/O, memory, and configuration space. The PMC module
can be accessed via the PCI bus memory space and configuration
spaces, only.
The PCI card’s configuration registers are initialized by system
software at power-up to configure the card. The PMC440 module is
a Plug-and-Play PCI card. As a Plug-and-Play card the board’s
base address and system interrupt request line are not selected via
jumpers but are assigned by system software upon power-up via the
configuration registers. A PCI bus configuration access is used to
access a PCI card’s configuration registers.
PCI Configuration Address Space
When the computer is first powered-up, the computer’s system
configuration software scans the PCI bus to determine what PCI
devices are present. The software also determines the configuration
requirements of the PCI card.
The system software accesses the configuration registers to
determine how many blocks of memory space the carrier requires. It
then programs the PMC module’s configuration registers with the
unique memory address range assigned.
The configuration registers are also used to indicate that the
PMC module requires an interrupt request line. The system
software then programs the configuration registers with the interrupt
request line assigned to the PMC module.
Since this PMC module is relocatable and not fixed in address
space, this module’s device driver provided by Acromag uses the
mapping information stored in the module’s Configuration Space
registers to determine where the module is mapped in memory
space and which interrupt line will be used.
Configuration Registers
The PCI specification requires software driven initialization and
configuration via the Configuration Address space. This PMC
module provides 256 bytes of configuration registers for this
purpose. The PMC440 contains the configuration registers, shown
in Table 3.1, to facilitate Plug-and-Play compatibility.
The Configuration Registers are accessed via the Configuration
Address and Data Ports. The most important Configuration
Registers are the Base Address Registers and the Interrupt Line
Register which must be read to determine the base address
assigned to the PMC440 and the interrupt request line that goes
active on a PMC440 interrupt request.
Table 3.1 Configuration Registers
Reg.
Num. D31 D24 D23 D16 D15 D8 D7 D0
0Device ID=4B4B Vendor ID= 16D5
1Status Command
2Class Code=118000 Rev ID=00
3BIST Header Latency Cache
432-bit Memory Base Address for PMC440
4K-Byte Block
5 : 10 Not Used
11 Subsystem ID=0000 Subsystem Vendor
ID=0000
12 Not Used
13,14 Reserved
15 Max_Lat Min_Gnt Inter. Pin Inter. Line
MEMORY MAP
This board is allocated a 4K byte block of memory that is
addressable in the PCI bus memory space to control the
configuration and status monitoring of 32 digital input or event
channels.
This board operates in two modes: Standard Mode and
Enhanced Mode. Standard Mode provides digital input voltage
monitoring of 32 isolated signal lines. In Standard Mode, each input
line is configured as a simple input without interrupts. Data is read
from (or written to) one of eight groups (ports) as designated by the
address and read and write signals. The ASIC of this model is

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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capable of I/O, but this model is intended for input only. A Mask
Register is used to disable writes to I/O ports designed for input
only. Enhanced Mode includes the same functionality of Standard
Mode, but adds access to 32 additional event sense inputs
connected to each input point of ports 0-3. Individual inputs also
include selectable hardware debounce in Enhanced Mode. For
event sensing, the Enhanced Mode allows a specific input level
transition (High-to-Low, Low-to-High, or Change-of-State) to be
detected and optionally generate an interrupt.
Memory is organized and addressed in separate banks of eight
registers or ports (eight ports to a bank). The Standard Mode of
operation addresses the first group of 8 registers or ports (ports 0-3
for reading inputs, Ports 4, 5, & 6 which are not used on this model,
and Port 7 which is the Mask Register). The mask register is
included to mask writes to input points, since the input points of this
model are intended for input only, while the digital ASIC is capable of
output control. If the Enhanced Mode is selected, then 3 additional
banks of 8 registers are accessed to cover the additional
functionality in this mode (events, interrupts, and debounce). The
first bank of the Enhanced Mode (bank 0) is similar in operation to
the Standard Mode. The second bank (bank 1) provides event
sense and interrupt control. The third bank is used to configure the
debounce circuitry to be applied to input channels in the Enhanced
Mode. Two additional mode-independent registers are provided to
enable the interrupt request line, generate a software reset, and
store the interrupt vector.
The memory space address map for the PMC470 is shown in
Table 3.2. Note the base address for the PMC module must be
added to the addresses shown to properly access the PMC
registers. Registers are 8-bit only and are aligned on a 32-bit
boundry. Thus, the 8-bit registers can be accessed over the PCI
bus via 8-bit, 16-bit, or 32-bit accesses. Note that only the lower 8-
bits will contain valid data.
Note that some functions share the same register address. For
these items, the address lines are used along with the read and write
signals to determine the function required.
Standard (Default) Mode Memory Map
The following table shows the memory map for the Standard
Mode of operation. This is the Default mode reached after power-up
or system reset. Standard Mode provides simple monitoring of 32
digital input lines without interrupts. Data is read from or written to
one of eight groups (ports) as designated bythe address and read
and write signals. A Mask Register is used to disable writes to input
ports, since this model is intended for input only. That is, the ASIC
used by this model is capable of output, and since this model is
intended for input only, then each port (group of 8 input lines) must
be blocked (masked) from writes.
To switch to Enhanced Mode, four unique bytes must be written
to port 7, in consecutive order, without doing any reads or writes to
any other port and with interrupts disabled. The data pattern to be
written is 07H, 0DH, 06H, and 12H, and this must be written after
reset or power-up.
Table 3.2A: PMC440 R/W Space Address (Hex) Memory Map
Hex
Base
Addr+ MSB D15 D08 LSB D07 D00
Hex
Base
Addr+
001 INTERRUPT REGISTER 000
STANDARD MODE (DEFAULT) REGISTER DEFINITIONS:
201 Not Driven4READ1- Port 0
Register IN00-IN07 200
205 Not Driven4READ1- Port 1
Register IN08-IN15 204
209 Not Driven4READ1- Port 2
Register IN16-IN23 208
20D Not Driven4READ1- Port 3
Register IN24-IN31 20C
211 Not Driven4READ/WRITE2- Port 4
NOT USED 210
215 Not Driven4READ/WRITE2- Port 5
NOT USED 214
219 Not Driven4READ/WRITE2- Port 6
NOT USED 218
21D Not Driven4READ/WRITE - Port 7
WRITE MASK REGISTER
AND
ENHANCED MODE
SELECT REGISTER3
21C
221
↓
↓↓
↓
2FD NOT USED5220
↓
↓↓
↓
2FC
Notes (Table 3.2A):
1. Writes to these registers are possible, but this model is intended
for input only and writes should not be done. Writes to these
registers may be blocked via the Write Mask Register of Port 7.
2. The ASIC of this model is capable of a greater channel count,
but only 32 channels are used by this model, and as a result,
ports 4, 5, & 6 are not used.
3. Writing four unique bytes (07H, 0DH, 06H, and 12H) to port 7, in
consecutive order, will switch to Enhanced Mode. Do this
without doing any reads or writes to anyother port, with
interrupts disabled, and after reset or power-up.
4. Bits 15-8 of these registers are not used. Bits 15-8 will be driven
high (1’s).
5. The PMC will respond to addresses that are "Not Used".
6. Bits 31-16 of these registers will be read (0’s).
Enhanced Mode Memory Maps
The following table shows the memory maps used for the
Enhanced Mode of operation. Enhanced Mode includes the same
functionality of Standard Mode, but allows each input port’s event
sense input and debounce logic to be enabled.
In Enhanced Mode, a memory map is given for each of 3
memory banks. The first memory bank (bank 0) has the same
functionality as the Standard Mode. Additionally, its port 7 register is
used to select which bank to access (similar to Standard Mode
where port 7 was used to select the Enhanced Mode). Bank 1
provides read/write access to the 32 event sense inputs. Bank 2
provides access to the registers used to control the debounce
circuitry of these event sense inputs.

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Table 3.2B: PMC440 R/W Space Address (Hex) Memory Map
Hex
Base
Addr+ MSB D15 D08 LSB D07 D00
Hex
Base
Addr+
001 INTERRUPT REGISTER 000
ENHANCED MODE, REGISTER BANK [0] DEFINITIONS:
201 Not Driven1READ3- Port 0
Register IN00-IN07 200
205 Not Driven1READ3-Port 1
Register IN08-IN15 204
209 Not Driven1READ3- Port 2
Register IN16-IN23 208
20D Not Driven1READ3- Port 3
Register IN24-IN31 20C
211 Not Driven1READ/WRITE4- Port 4
NOT USED 210
215 Not Driven1READ/WRITE4- Port 5
NOT USED 214
219 Not Driven1READ/WRITE4- Port 6
NOT USED 218
21D Not Driven1READ - Port 7
READ MASK REGISTER
(Also Current Bank Status)
21C
21D Not Driven1WRITE - Port 7
WRITE MASK REGISTER
(Also Bank Select Register)
21C
ENHANCED MODE, REGISTER BANK [1] DEFINITIONS:
201 Not Driven1READ - Port 0
Event Sense Status Reg.
(Port 0 Input points 0-7)
200
201 Not Driven1WRITE - Port 0
Event Sense Clear Register
(Port 0 Input points 0-7)
200
205 Not Driven1READ - Port 1
Event Sense Status Reg.
(Port 1 Input points 8-15)
204
205 Not Driven1WRITE - Port 1
Event Sense Clear Register
(Port 1 Input points 8-15)
204
209 Not Driven1READ - Port 2
Event Sense Status Reg.
(Port 2 Input points 16-23)
208
209 Not Driven1WRITE - Port 2
Event Sense Clear Register
(Port 2 Input points 16-23)
208
20D Not Driven1READ - Port 3
Event Sense Status Reg.
(Port 3 Input points 24-31)
20C
20D Not Driven1WRITE - Port 3
Event Sense Clear Register
(Port 3 Input points 24-31)
20C
211 Not Driven1READ - Port 4
NOT USED 210
211 Not Driven1WRITE - Port 4
NOT USED 210
215 Not Driven1READ - Port 5
NOT USED 214
215 Not Driven1WRITE - Port 5
NOT USED 214
219 Not Driven1READ - Port 6
Event Status for Ports 0-3
and Interrupt Status Reg.
218
219 Not Driven1WRITE - Port 6
Event Polarity Control
Register for Port 0-3
218
21D Not Driven1READ - Port 7
Current Bank Status Reg. 21C
21D Not Driven1WRITE - Port 7
Bank Select Register 21C
ENHANCED MODE, REGISTER BANK [2] DEFINITIONS:
201 Not Driven1READ/WRITE - Port 0
Debounce Control Register
(for Ports 0-3)
200
205 Not Driven1READ/WRITE - Port 1
Debounce Duration Reg. 0
(for Ports 0-3)
204
209 Not Driven1NOT USED 208
20D Not Driven1WRITE ONLY - Port 3
Debounce Clock Select 20C
211
↓
↓↓
↓
219 Not Driven1Port 4,5,6
NOT USED2210
↓
↓↓
↓
218
21D Not Driven1READ/WRITE - Port 7
Bank Status/Select Register 21C
INDEPENDENT FIXED FUNCTION REGISTERS:
221
↓
↓↓
↓
239 NOT USED2220
↓
↓↓
↓
238
23D Not Driven1READ/WRITE
Interrupt Enable Register
(Bit 0=1 enables INTREQ0)
& Software Reset Generator
(Bit 1=1 Generates Reset)
23C
241
↓
↓↓
↓
2FD NOT USED2240
↓
↓↓
↓
2FC
Notes (Table 3.2B):
1. Bits 15-8 of these registers are not used. Bits 15-8 will be driven
high (1’s).
2. The PMC will respond to addresses that are "Not Used".
3. Writes to these registers are possible, but this model is intended
for input only and writes should not be done. Writes to these
registers may be blocked via the Write Mask Register of Port 7.
4. The ASIC of this model is capable of a greater channel count,
but only 32 channels are used by this model, and as a result,
ports 4, 5, & 6 are not used.
5. Bits 31-16 of these registers will be read as (0’s).
REGISTER DEFINITIONS
Interrupt Register, (Read/Write) - (Base + 00H)
This read/write register is used to: enable board interrupt,
determine the pending status of interrupts, and release an interrupt.
The function of each of the interrupt register bits are described
in Table 3.3. This register can be read or written with either 8-bit,
16-bit, or 32-bit data transfers. A power-up or system reset sets all
interrupt register bits to 0.

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Table 3.3: Interupt Register
BIT FUNCTION
0 Board Interrupt Enable Bit. This bit must be set to
logic “1” to enable generation of interrupts from the
PMC module. Setting this bit to logic “0” will disable
board interrupts. (Read/Write Bit)
1 Interrupt Pending Status Bit. This bit can be read to
determine the interrupt pending status of the PMC
module. When this bit is logic “1” an interrupt is
pending and will cause an interrupt request if bit-0 of
the register is set. When this bit is a logic “0” an
interrupt is not being requested.
7 to 2 Not Used1
8 Software Reset
Writing a logic “1” to this bit will cause a reset of PMC
module. Bit-0 of this register will not be affected.
15 to 9 Not Used1
Notes (Table 3.3):
1. All bits labeled “Not Used” will return logic “0” when read.
STANDARD MODE REGISTERS
Port Registers
(Standard Mode, Ports 0-3, Read, Write Restricted)
Four registers are provided to monitor 32 possible input points.
Data is read from one of four groups of eight input lines (Ports 0-3),
as designated by the address and read and write signals. Each port
assigns the least significant data line (D0) to the least significant
input line of the port grouping (e.g. IN00 for port 0 to D0). A read of
this register returns the status (ON/OFF) of the input point.
Although the ASIC used by this model is capable of output, the
PMC440 is intended for input only and writes to these registers
should be blocked. Writing ‘1’ to this register will cause the input to
always read as 0, and changes in the input will be ignored (until a 0
is written or a reset occurs). A Mask Register is used to disable
writes to ports intended for input only. That is, each port (group of 8
input lines) should be masked from writes.
On power-up or reset, the ports are reset to 0, forcing the
outputs to be set high/OFF (outputs are not used by this model).
Write Mask Register & Enhanced Mode Select Register
(Standard Mode, Port 7, Read/Write)
The ASIC used by the PMC440 is capable of output. However,
the ports of this model are intended for input onlyand writes to these
ports should be avoided. This register is used to mask the ability to
write data to the four I/O ports of this model. Writing a ‘1’ to bits 0-3
of the Mask Register will mask ports 0-3 respectively, from
inadvertent writes. A read of this register will return the status of the
mask in bits 0-3.
Standard Mode Write Mask Register (Port 7)
BIT WRITE TO REGISTER READ FROM REGISTER
0 Port 0 Write Mask Port 0 Write Mask
1 Port 1 Write Mask Port 1 Write Mask
2 Port 2 Write Mask Port 2 Write Mask
3 Port 3 Write Mask Port 3 Write Mask
4-7 NOT USED NOT USED
Bits 4-7 of this register are not used. On power-up reset, this
register defaults to the unmasked state, allowing writes to the output
ports.
This register is also used to select the Enhanced Mode of
operation. To switch to Enhanced Mode, four unique bytes must be
written to port 7, in consecutive order, without doing any reads or
writes to any other port and with interrupts disabled. The data
pattern to be written is 07H, 0DH, 06H, and 12H, in order, and this
must be written immediately after reset or power-up.
ENHANCED MODE
BANK 0 REGISTERS
Port Registers
(Enhanced Mode Bank 0, Ports 0-3, Read, Write Restricted)
Four input registers are provided to monitor 32 possible input
points. Data is read from one of four groups (Ports 0-3) of eight
input lines, as designated by the address. Each port assigns the
least significant data line (D0) to the least significant input line of the
port grouping (e.g. IN00 of port 0 to D0). A read of this register
returns the status (ON/OFF) of the input signal. Although the ASIC
used bythis model is capable of output, the PMC440 is intended for
input only and writes to these registers should be blocked. Writing
‘1’ to this register will cause the input to always read as 0, and
changes in the input will be ignored (until a 0 is written or a reset
occurs). A Mask Register is used to disable writes to ports intended
for input only. That is, each port (group of 8 input lines) should be
masked from writes (see below).
Write Mask Register And Bank Select Register 0
(Enhanced Mode Bank 0, Port 7, Read/Write)
The ASIC used by the PMC440 is capable of output. However,
the ports of this model are intended for input onlyand writes to these
ports should be avoided. This register is used to mask the ability to
write data to the four I/O ports of this model. Writing a ‘1’ to bits 0-3
of the Mask Register will mask ports 0-3 respectively, from
inadvertent writes. A read of this register will return the status of the
mask in bits 0-3.
Enhanced Mode Write Mask Register (Port 7)
BIT WRITE TO REGISTER READ FROM REGISTER
0 Port 0 Write Mask Port 0 Write Mask
1 Port 1 Write Mask Port 1 Write Mask
2 Port 2 Write Mask Port 2 Write Mask
3 Port 3 Write Mask Port 3 Write Mask
4-5 NOT USED NOT USED
6 Bank Select Bit 0 Bank Status Bit 0
7 Bank Select Bit 1 Bank Status Bit 1
Bits 6 & 7 of this register are used to select/monitor the bank of
registers to be addressed. In Enhanced Mode, three banks (banks
0-2) of eight registers may be addressed. Bank 0 registers are
similar to the Standard Mode bank of registers. Bank 1 allows the
32 event inputs to be monitored and controlled. Bank 2 registers
control the debounce circuitry of the event inputs. Bits 7 and 6
select the bank as follows:

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Enhanced Mode Bank Select
Bit 7 Bit 6 BANK OF REGISTERS
00 Bank 0 - Read Input Signals
01 Bank 1 - Event Status/Clear
10 Bank 2 - Event Debounce Control, Clock, and
Duration
11 INVALID - DO NOT WRITE
On power-up reset, this device is put into the Standard Mode
and this register defaults to the unmasked state (allowing writes to
the ports which should be avoided), and bank 0 (Default).
BANK 1 REGISTERS
Event Sense Status & Clear Registers For IN00-IN31
(Enhanced Mode Bank 1, Ports 0-3, Read/Write)
Each input line of each port includes an event sense input.
Reading each port will return the status of each input port’s sense
lines. Writing ‘0’ to a bit position of each port will clear the event on
the corresponding line. When writing ports 0-3 of Enhanced Mode
bank 1, each data bit written with a logic 0 clears the corresponding
event sense flip/flop. Further, each data bit of ports 0-3 must be
written with a 1 to re-enable the corresponding event sense input
after it is cleared. Reading ports 0-3 of the Enhanced Mode bank 1
returns the current event sense flip/flop status.
Port 0 Event Sense/Status Register (Ports 1-3 are Similar)
BIT READ PORT WRITE “0” WRITE “1”
0 Port 0 IN00
Event Status Clear IN00 Event Sense Flip/Flop Re-enable IN00 Event Sense
1 Port 0 IN01
Event Status Clear IN01 Event Sense Flip/Flop Re-enable IN01 Event Sense
2 Port 0 IN02
Event Status Clear IN02 Event Sense Flip/Flop Re-enable IN02 Event Sense
3 Port 0 IN03
Event Status Clear IN03 Event Sense Flip/Flop Re-enable IN03 Event Sense
4 Port 0 IN04
Event Status Clear IN04 Event Sense Flip/Flop Re-enable IN04 Event Sense
5 Port 0 IN05
Event Status Clear IN05 Event Sense Flip/Flop Re-enable IN05 Event Sense
6 Port 0 IN06
Event Status Clear IN06 Event Sense Flip/Flop Re-enable IN06 Event Sense
7 Port 0 IN07
Event Status Clear IN07 Event Sense Flip/Flop Re-enable IN07 Event Sense
Event Interrupt Status Register For Ports 0-3
(Enhanced Mode Bank 1, Port 6, Read Only)
Reading this register will return the event interrupt status of
input ports 0-3 (bits 0-3) and the interrupt status flag (bit 7). Bit 7 of
this register indicates an event sense was detected on any of the 4
event sense ports (“1” = interrupt asserted/event sensed). Notethat
the interrupt status flag may optionallydrive the Interrupt Request
Line of the PMC440 (see Interrupt Enable Register).
Event Interrupt Status Register For Ports 0-3
BIT READ EVENT STATUS REGISTER
0 Port 0 Interrupt Status (IN00-IN07)
1 Port 1 Interrupt Status (IN08-IN15)
2 Port 2 Interrupt Status (IN16-IN23)
3 Port 3 Interrupt Status (IN24-IN31)
4-6 NOT USED
7 Interrupt Status Flag
Event Polarity Control Register For Ports 0-3
(Enhanced Mode Bank 1, Port 6, Write Only)
A write to this register controls the polarity of the input sense
event for nibbles of ports 0-3 (channels 0-31, four channels at a
time). A “0” written to a bit in this register will cause the
corresponding event sense input lines to flag negative events (high-
to-low transitions). A “1” will cause positive events to be sensed
(low-to-high transitions). The polarity of the event sense logic must
be set prior to enabling the event input logic. Note that no events will
be detected until enabled via the Event Sense Status & Clear
Register. Further, interrupts will not be generated unless the
PMC440 has been enabled via the Interrupt Register.
Event Polarity Control Register
BIT WRITE “1” (NEGATIVE) WRITE “0” (POSITIVE)
0 Negative Events on
Port 0 IN00 through IN03 Positive Events on Port 0 IN00 through IN03
1 Negative Events on
Port 0 IN04 through IN07 Positive Events on Port 0 IN04 through IN07
2 Negative Events on
Port 1 IN08 through IN11 Positive Events on Port 1 IN08 through IN11
3 Negative Events on
Port 1 IN12 through IN15 Positive Events on Port 1 IN12 through IN15
4 Negative Events on
Port 2 IN16 through IN19 Positive Events on Port 2 IN16 through IN19
5 Negative Events on
Port 2 IN20 through IN23 Positive Events on Port 2 IN20 through IN23
6 Negative Events on
Port 3 IN24 through IN27 Positive Events on Port 3 IN24 through IN27
7 Negative Events on
Port 3 IN28 through IN31 Positive Events on Port 3 IN28 through IN31
Bank Select Register
(Enhanced Mode Bank 1, Port 7, Write Only)
Bits 6 & 7 of this register are used to select/monitor the bank of
registers to be addressed. In Enhanced Mode, three banks (banks
0-2) of eight registers may be addressed. Bank 0 is similar to the
Standard Mode bank of registers. Bank 1 allows the 32 event inputs
to be monitored and controlled. Bank 2 registers control the
debounce circuitry of the event inputs. Bits 0-5 of this register are
not used. Bits 7 and 6 select the bank as follows:
Bank Select Register
BIT Function
0-5 NOT USED
6 Bank Select Bit 0
7 Bank Select Bit 1
Bank Select Register (Write)
Bit 7 Bit 6 BANK OF REGISTERS
00 Bank 0 - Read Inputs
01 Bank 1 - Event Status/Clear
10 Bank 2 - Event Debounce Control, Clock, and
Duration
11 INVALID - DO NOT WRITE
Bank Select Status Register 1
(Enhanced Mode Bank 1, Port 7, Read Only)
Bits 0-5 of this register are not used. Bits 6 & 7 of this register
are used to indicate the bank of registers to be addressed. In
Enhanced Mode, three banks (banks 0-2) of eight registers may be
addressed. Bank 0 is similar to the Standard Mode bank of

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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registers. Bank 1 allows the 32 event inputs to be monitored and
controlled. Bank 2 registers control the debounce circuitry of the
event inputs. Bits 7 and 6 of this register select the bank as follows:
Bank Selected Status Register (Read)
Bit 7 Bit 6 BANK OF REGISTERS
00 Bank 0 - Read Inputs
01 Bank 1 - Event Status/Clear
10 Bank 2 - Event Debounce Control, Clock, & Duration
11 INVALID - DO NOT WRITE
BANK 2 REGISTERS
Debounce Control Register
(Enhanced Mode Bank 2, Port 0, Read/Write)
This register is used to control whether each individual port is to
be passed through the debounce logic before being recognized by
the circuitry. A “0” disables the debounce logic, and a “1” enables
the debounce logic. Debounce applies to both inputs and event
sense inputs, and onlyin Enhanced Mode.
Debounce Control Register
BIT DEBOUNCE CONTROL “0” “1”
0 Port 0 (IN00-IN07) Disable Enable
1 Port 1 (IN08-IN15)
2 Port 2 (IN16-IN23)
3 Port 3 (IN24-IN31)
4-7 NOT USED
Debounce Duration Register 0
(Enhanced Mode Bank 2, Port 1, Read/Write)
This register controls the duration required by each input signal
before it is recognized by each individual ASIC input in the
Enhanced Mode. Register 0 controls debounce for ports 0-3. If the
debounce clock has been selected (see Debounce Clock Select
Register), then the 8MHz internal system clock will allow the
debounce times shown below to be selected (actual times vary to
within minus 25% of nominal). Note that this timeapplies to the
ASIC input and does not include the optocoupler time delay.
Debounce Duration Register 0: Duration (8MHz):
BIT DEBOUNCE CONTROL Bit 1,0 Time
0 Port 0 Debounce Value Bit 0 00 3-4us
1 Port 0 Debounce Value Bit 1 01 48-64us
2 Port 1 Debounce Value Bit 0 10 0.75-1ms
3 Port 1 Debounce Value Bit 1 11 6-8ms
4 Port 2 Debounce Value Bit 0
5 Port 2 Debounce Value Bit 1
6 Port 3 Debounce Value Bit 0
7 Port 3 Debounce Value Bit 1
Note that with the 8MHz clock enabled, a debounce value of 00
sets 3-4us, 01 sets 48-64us, 10 sets 0.75-1ms, and 11 sets 6-8ms.
The default value is 00, setting a 3-4us debounce period. This
register is cleared following a reset (setting debounce to 3-4us).
Note that the debounce clock must be reselected to re-enable
debounce following a reset (see below).
Debounce Clock Select Register
(Enhanced Mode Bank 2, Port 3, Write Only)
This register selects the source clock for the event sense input
debounce circuitry. If bit 0 of this register is 0 (default value), then
the debounce source clock is disabled. If bit 0 is set to 1, then the
8MHz internal system clock is enabled. This bit must be
programmed to “1” to use debounce. Bits 1-7 of this register are not
used and will always read as zero. This register is cleared following
a reset, disabling use of the 8MHz debounce clock.
Bank Select (Write) & Status (Read) Register 2
(Enhanced Mode Bank 2, Port 7, Read and Write)
Bits 0-5 of this register are not used. Bits 6 & 7 of this register
are used to indicate (read) or select (write) the bank of registers to
be addressed. In Enhanced Mode, three banks (banks 0, 1, & 2) of
eight registers may be addressed. Bank 0 registers are similar to
the Standard Mode bank of registers. Bank 1 allows the 32 event
inputs to be monitored and controlled. Bank 2 registers control the
debounce circuitry of the event inputs. Bits 7 and 6 select/indicate
the bank as follows:
Bank Select (Write) & Status(Read) Register
Bit 7 Bit 6 BANK OF REGISTERS
00 Bank 0 - Read Input Signals
01 Bank 1 - Event Status/Clear
10 Bank 2 - Event Debounce Control, Clock, & Duration
11 INVALID - DO NOT WRITE
INDEPENDENT FIXED FUNCTION CONTROL REGISTERS
Interrupt Enable & Software Reset Register (Read/Write, 23CH)
Bit-0 of this register specifies if the internal event sense
interrupts are to drive INTA# or not. This bit defaults to 0 (interrupt
request disabled) and event interrupts are only flagged internally.
That is, you would have to poll the Event Status Register to
determine if an interrupt had occurred and the INTA# line would not
be driven. If bit-0 of this register is set to “1”, then interrupts will
drive the INTA# line. Note bit-0 of the Interrupt Enable Register is at
Base Address + 23CH and must always be set to enable interrupts.
This bit is cleared following a system reset, but not a software reset
(see below).
Note, to enable interrupts and the driving of INTA#, you must
also set bit-0 high in the Interrupt Register at Base Adrress +000H.
Writing a 1 to the bit-1 position of this register will cause a
software reset to occur (be sure to preserve the current state of bit 0
when conducting a software reset). This bit is not stored and merely
acts as a trigger for software reset generation (this bit will always
readback as 0). The effect of a software reset is similar to a system
reset, except that it only resets the digital ASIC chip that provides
the field interface functions. Likewise, the Interrupt Enable Bit of this
register is not cleared in response to a software reset (these are not
stored in the ASIC). Bits 2-7 of this register are not used and will
always read low (1’s).
THE EFFECT OF RESET
A power-up or bus-initiated software reset will place the module
in the Standard Operating Mode (input only, no event sensing, no
interrupts, and no debounce). A reset will also clear the mask

SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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register and enable writes to the input points of the ASIC (input lines
of this model should be masked from writes). Further, all event
inputs are reset, set to positive events, and disabled following reset.
A false input signal is ensured for inputs left floating (i.e. reads as
0). The Interrupt Enable Register (IER) is also cleared (except for
IER generated software resets).
Another form of software reset (IER register initiated) acts
similar to a system or power-up reset, except that it only resets the
digital ASIC chip installed on the module.
PMC440 PROGRAMMING CONSIDERATIONS
To make programming and communicating with the board
easier, Acromag provides a software product (sold separately)
consisting of PMC module VxWorkslibraries. This software
(Model PMCSW-API-VXW, MSDOS format) is composed of
VxWorks(real time operating system) libraries for all Acromag
PMC modules. The software is implemented as a library of “C”
functions which link with existing user code to make possible simple
control of all Acromag PMC modules.
Acromag, also provides a software product (sold separately)
consisting of PMC module ActiveX (Object Linking and Embedding)
controls for Windows 98, 95, ME, 2000 and Windows NT
compatible application programs (Model PMCSW- ATX, MSDOS
format) to program and communicate with the board.
Basic Input Operation
Note that the input lines of this module are assembled in groups
of eight. Each group of eight lines is referred to as a port. Ports 0-3
control and monitor input lines 0-31. Additionally, ports are grouped
eight to a bank. There are four banks of ports used for controlling
this module (Standard Mode, plus Enhanced Mode Banks 0, 1, and
2), plus 2 additional registers for enabling the interrupt request line,
and generating a software reset.
Each port input line is bipolar and accepts both positive and
negative input voltages in three ranges according to the model
number. Individual input lines of a port share a common signal
connection with each other. Separate commons are provided for
each port to facilitate port-to-port isolation. A high signal is derived
from the absolute value of the input voltage measured between the
input line and the port common for the input ranges of 4-18V
(PMC440-1 models), 16-40V (PMC440-2 models), and 38-60V
(PMC440-3 models). Inputs are non-inverting and inputs left floating
(not recommended) will register a low (false=0) input indication.
In both the Standard and Enhanced operating modes, each
group of eight parallel input lines (a port) are isolated and gated to
the data bus D0..D7 lines. A high input will read as “1” and all inputs
include hysteresis and programmable debounce. Because the ASIC
used by this model is capable of output, individual ports should be
masked from writes to the port since they are intended for input only.
Enhanced Operating Mode
In the Enhanced Mode of operation, each port input mayact as
an event sensor and generate interrupts. Likewise, programmable
debounce logic is also available. Event sensing is used to
selectively sense high-to-low level, or low-to-high level transitions on
the input lines at the range thresholds of 4V (“-1” units), 16V (“-2”
units), and 38V (“-3” units). Event polarities maybedefined as
positive or negative for individual nibbles (groups of 4 input lines, or
half ports). Interrupts may also be triggered by events. The optional
debounce logic can act as a filter to “glitches” or transients present
on received signals.
Because the ASIC used by this model is capable of I/O, while
the module is intended for input only, individual input ports should be
masked from writes to the port. Otherwise, writing a “1” to an input
line will cause the input to always read 0 (until a “0” is written or a
reset occurs).
The Enhanced Mode is entered by writing four unique bytes to
the Standard Mode Port 7 register, in consecutive order, without
doing any reads or writes to any other ports and with interrupts
disabled. The data pattern to be written is 07H, 0DH, 06H, and 12H,
and this must be written immediately after reset or power-up.
In Enhanced Mode, there are three groups (or banks) of eight
registers or ports. The first group, bank 0, provides register
functionality similar to Standard Mode (input level monitoring). The
second group, bank 1, provides monitor and control of the event
sense inputs. The third group, bank 2, is used to configure the
debounce circuitry for each input while in the Enhanced Mode.
Event Sensing
The PMC440 has edge-programmable event sense logic built-in
for all 32 input lines, IN00 through IN31. Event sensing may be
configured to generate an interrupt to the system, or to merely reflect
the interrupt internally. Event sensing is enabled in Enhanced Mode
onlyand inputs can be set to detect positive or negative events, on a
nibble-by-nibble (group of 4 input lines) basis. The event sensing is
enabled on an individual channel basis. You can combine event
sensing with the built-in debounce control circuitry to obtain “glitch-
free” edge detection of incoming signals.
To program events, determine which input lines are to have
events enabled and which polarity is to be detected, high-to-low level
transitions (negative) or low-to-high level transitions (positive). Set
each half-port (nibble) to thedesired polarity, then enable each of the
event inputs to be detected. Optionally, if interrupt requests are
desired, enable the interrupt request line and set bit 0 of the Interrupt
Register at offset Base Address +0. Note that all event inputs are
reset, set to positive events, and disabled after a power-up or
software reset has occured.
Change-Of-State Detection
Change-of-State signal detection requires that both a high-to-low
and low-to-high signal transition be detected. On the PMC440, if
change-of-state detection for an input signal is desired, two
channels connected to the same input signal would be required--one
sensing positive transitions, one sensing negative transitions. Since
channel polarity is programmable on a nibble basis (group of four),
the first nibble of a port could be configured for low-to-high
transitions, the second nibble for high-to-low transitions. As such,
up to 16 change-of-state detectors may be configured.
Debounce Control
Debounce control is built into the on-board digital ASIC
employed by the PMC440 and is enabled in the Enhanced Mode
only. With debounce, an incoming signal must be stable for the
entire debounce time before it is recognized as a valid input or event

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at the ASIC input. Note that the debounce time applies at the ASIC
input and does not include the optocoupler delay. You can combine
debounce with event sensing to obtain “glitch-free” edge detection of
incoming signals for all 32 channels. That is, the debounce circutry
will help filter out “glitches” or transients that can occur on received
signals, for error-free edge detection and increased noise immunity.
The debounce circuitry uses the 8MHz internal system clock to
derive the debounce times (see the Debounce Clock Select register
to enable the clock to be used). Debounce values of 3-4us, 48-
64us, 0.75-1ms, or 6-8ms may be selected (see the Debounce
Duration Register). As such, an incoming ASIC signal must be
stable for the debounce time before it is recognized as a valid input
or event.
Upon initialization of the debounce circuitry, be sure to delay at
least the programmed debounce time before reading any of the input
ports or event signals to ensure that the input data is valid prior to
being used by the software.
Interrupt Generation
This model provides control for generation of interrupts on
positive or negative events, for all 32 channels. Interrupts are only
generated in the Enhanced Mode for event channels when enabled
via the Event Sense/Status Register and when Bit 0 of the Interrupt
Enable Register is set to “1” at Base Adrress + 23CH. In addition,
bit-0 of the Interrupt Register at Base Address + 000H must be set
to logic “1”. Writing 0 to the corresponding event sense bit in the
Event Sense/Status Register will clear the event sense flip/flop.
Successive interrupts will onlyoccur if the event channel has been
reset by writing a 1 to the corresponding event sense bit in the Event
Sense/Status Register (after writing 0 to clear the event sense
flip/flop). Interrupts maybe reflected internally and reported by
polling the module, or optionally reported to the PCI bus by enabling
control of the Interrupt Request line (INTA#). Control of this line is
initiated via bit-0 of the Interrupt Enable Register (IER) and via bit-0
of the Interrupt Register.
Once INTA# goes active to signal an event it will stay active until
the conditions generating the interrupt have been cleared or returned
to normal. Also, the event sense bit must be cleared by writing a 0
to the required bit of the Event Sense Status Register. INTA# can
also be disabled by clearing bit-0 of the Interrupt Register at Base
Address + 000H.
Note that the state of the inputs (on/off) can be determined by
reading the corresponding port address while in bank 0 of the
Enhanced Mode. However, the event sense status can only be read
by reading the corresponding port address while in bank 1 of the
Enhanced Mode. Remember, the event sense status is a flag that is
raised when a specific positive or negative transition has occurred
for a given I/O point, while the state refers to its current level.
Note that the Interrupt Enable Register at Base Address + 23CH
is cleared following a power-up or bus initiated software reset. Also,
bit-0 of the Interrupt Register at Base Address + 000H is not
affected by asoftware reset. Keep this in mind when you wish to
preserve the information in this register following a reset.
Programming Example
The following example outlines the steps necessary to configure
the PMC440 for Enhanced Mode operation, to setup event-
generated interrupts, configure debounce, and read and write inputs.
It is assumed that the module has been reset and no prior (non-
default) configuration exists.
For this example, we will configure port 0 input points as a four-
channel change-of-state detector. For change-of-state detection,
both positive and negative polarities must be sensed and thus, two
channels are required to detect a change-of-state on a single input
signal. IN00-IN03 will be used to detect positive events (low-to-high
transitions), IN04-IN07 will be used to detect negative events (high-
to-low transitions). IN00 and IN04 will be tied to the first input
signal, IN01 & IN05 to the second, IN02 & IN06 to the third, and
IN03 & IN07 to the fourth. Any change-of-state detected on these
input signal lines will cause an interrupt to be generated.
1. After power-up or reset, themodule is always placed in the
Standard Operating Mode. To switch to Enhanced Mode, you
must write four unique bytes to the Port 7, Enhanced Mode
Select Register at Base Address + 21CH, in consecutive order,
without doing any reads or writes to any other ports and with
interrupts disabled. The data pattern to be written is 07H first,
followed by 0DH, followed by 06H, then 12H.
At this point, you are in Enhanced Mode bank 0. Port 7 would
now be used to access register banks 1 & 2.
2. Write 80H to the Port 7, Bank Status/Select Register at Base
Address + 21CH to select register bank 2 where debounce will
be configured for our port 0 input channels.
At this point, you are in Enhanced Mode Bank 2 where access
to the debounce configuration registers is obtained.
3. We need to enable the 8MHz system clock to generate our
debounce time. By default, the debounce clock is not enabled.
Select the 8MHz system clock as the debounce clock by writing
01H to the Port 3, Debounce Clock Select Register at Base
Address + 20CH of this bank.
4. The default debounce duration is 3-4us with the 8MHz clock
enabled in step 3. This time applies to the ASIC input signal
and does not include optocoupler delay. Write 01H to the Port
1, Debounce Duration Register 0 at Base Address + 204H of
this bank to select a 48-64us debounce time. An incoming
signal must be stable for the entire debounce time before it will
be recognized as a valid input transition by the ASIC.
Note that Debounce Duration Register 1 (port address 2) would
be used to configure debounce durations for ports 4 & 5. Since
ports 4 & 5 are not used by this model, Debounce Duration
Register 1 has no effect.
5. Enable the debounce circuitry for port 0 inputs by setting bit 0 of
the Debounce Control Register. Write 01H to the Port 0,
Debounce Control Register at Base Address + 200H of this
bank.
If the module had been configured earlier, you would first read
this register to check the existing settings of debounce enable
for the other ports of this module with the intent of preserving
their configuration by adjusting the value written above.

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6. Write 40H to Port 7, Bank Status/Select Register at Base
Address + 21CH to select register bank 1 where the event
polarity requirements of our application will be configured.
At this point, you are in Enhanced Mode Bank 1 where access
to the event polarity/status registers is obtained.
7. For change-of-state detection, both positive and negative
polarities must be sensed. As such, two channels are required
to detect a change-of-state on a single input signal. For our
example, IN00-IN03 will be used to detect positive events (low-
to-high transitions), IN04-IN07 will be used to detect negative
events (high-to-low transitions). Write 02H to the Port 6, Event
Polarity Control Register for Port 0-3 at Base Address + 218H
to set IN00-IN03 to positive edge detection, and IN04-IN07 to
negative edge detection.
Note that this port address has a dual function depending on
whether a read or write is being executed. As such, if the
current polarity configuration for the other ports must be
preserved, then it must be remembered since it cannot be read
back.
8. To enable event sensing for the port 0 input points, write FFH to
the Port 0, Event Sense Clear Register at Base Address + 200H
for input points in this bank.
Note that writing a 1 to a bit position enables the event sense
detector, while writing a 0 clears the event sensed without
enabling further event sensing.
9. Write 00H to the Port 7, Write Mask Register at Base Address +
21CH to select register bank 0 where the port 0 input channels
may be write-masked.
Note that the port 7 address bank selection only operates from
bits 6 & 7 of this register. Likewise, this register has a dual
function depending on whether a read or write is executed. As
such, the polarity settings cannot be read back and must be
remembered if they are to be preserved for successive writes.
At this point, you are in Enhanced Mode Bank 0 where access
to the write-mask register is obtained.
10. For our example, port 0 input points are to be used for inputs
only and writes to this port should be masked to prevent the
possibility of data contention between the built-in output
circuitry and the devices driving these inputs. Write 01H to the
Port 7, WriteMask Register at BaseAddress + 21CH tomask
writes to port 0.
11. Read 01H from the port 7, Write Mask Register at Base
Address + 21CH to verify bank 0 access (bits 6 & 7 are 0) and
port 0 write masking (bit 0 is 1).
12. (OPTIONAL) Write 01H to the Interrupt Enable Register (IER)
at Base Address + 23CH. Also, write 01H to the Interrupt
Register at Base Address + 000H to enable PMC470 control of
the Interrupt Request Line (INTA#).
When achange-of-state is detected, INTA# will be pulled low (if
the event sense detection circuitry has been enabled and IER bit
0=1). To enable further interrupts to occur for an event that has
already occurred for an I/O point, the Event Sense Status
Register must be written with a 1 to reenable event sensing for
subsequent events (but only after first writing 0 to the
corresponding bit position to clear the event sense flip/flop).
Note that the state of the inputs (on/off) can be determined by
reading the corresponding port address while in bank 0 of the
Enhanced Mode. However, the event sense status can only be
determined by reading the corresponding port address while in
bank 1 of the Enhanced Mode. Remember, the event sense
status is a flag that is raised when a specific positive or negative
transition has occurred for a given input point, while the state
refers toits current level.
4.0 THEORY OF OPERATION
This section provides a description of the basic functionality of
the circuitry used on the board. Refer to the Drawing 4501-870 as
you review this material.
PMC440 OPERATION
The PMC440 is built around a digital ASIC chip that provides
I/O interface and configuration functions. This chip performs
monitor and control functions of up to 48 open-drain outputs (only 32
are used by this model). The ASIC also provides debounce control
and event sensing functions.
A programmable logic device is installed on board to provide the
control interface necessary to operate the module. The Interrupt
Enable Register and Software Reset Control are also implemented
through the PLD.
Individual optocouplers for each channel provideisolation for the
PMC440. Channels are isolated from each other in groups of 8.
There are 8 channels to a group or port. Because the input lines of
a single port share a common connection, then individual inputs are
not isolated from each other within the same port. However,
separate port commons are provided to facilitate port-to-port
isolation.
Input optocouplers of this device are bipolar and accept voltages
in three ranges: ±(4-18V), ±(16-40V), and ±(38-60V), DC or AC
peak. The optocouplers connect directly to a digital ASIC I/O
controller that provides the I/O read/write functionality, interrupt
handling, and debounce control.
PCI INTERFACE LOGIC
The PCI bus interface logic is imbedded within the FPGA. This
logic includes support for PCI commands, including: configuration
read/write, and memory read/write. In addition, the PCI target
interface performs parity error detection, uses a single 4K base
address register, and implements target abort, retry, and disconnect.
The PMC440 logic also implements interrupt requests via interrupt
line INTA#. J1 and J2 connectors also provide ±12V and +5V to
power the module (±12V are not used).
A PCI bus read of the PMC module will initially terminate with a
retry. While the read data is moved to the read register (typically
1000ns), continued retries will result in retry terminations. The retry
termination allows the PCI bus to be free for other system
operations while the data is moved to the read register.

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A PCI bus write to the PMC module will result in 1)
immmediately accepting the write data and normal cycle termination
or 2) issue of a retry termination. A retry termination will be issued if
the previous write cycle has not completed on the PMC module. It
will typicallytake the PMC module 1000ns to write the data to the
required internal register. Thus if another write cycle is initiated on
the PCI bus before the typical 1000ns has lapsed, the write cycle will
be terminated with a retry.
A programmable logic device provides the control signals
required to operate the board. It decodes the selected addresses,
control signals, and interrupt handling. It also returns the
acknowledgement signal required by the carrier/CPU board per the
PMC specification. The program for the gate array is stored in
separate PROM memory and loaded upon power-up.
PMC Module Software
Acromag also provides a software product (sold separately)
consisting of PMC module ActiveX (Object Linking and Embedding)
controls for Windows 98, 95, ME, 2000 and Windows NT
compatible application programs (Model PMCSW- ATX, MSDOS
format). This software provides individual controls that allow
Acromag PMC modules to be easily integrated into Windows
application programs, such as Visual C++, Visual Basic,
MicrosoftOffice97 applications and others. The ActiveX
controls provide a high-level interface to PMC modules, eliminating
the need to perform low-level reads/writes of registers, and the
writing of interrupt handlers—all the complicated details of
programming are handled by the ActiveX controls. These functions
consist of an ActiveX control for each Acromag PMC module.
In adddition, Acromag provides a software product (sold
separately) consisting of PMC module VxWorkslibraries. This
software (Model PMCSW-API-VXW, MSDOS format) is composed
of VxWorks(real time operating system) libraries for all Acromag
PMC modules. The software is implemented as a library of “C”
functions which link with existing user code to make possible simple
control of all Acromag PMC modules.
5.0 SERVICE AND REPAIR
SERVICE AND REPAIR ASSISTANCE
Surface-Mounted Technology (SMT) boards are generally
difficult to repair. It is highly recommended that a non-functioning
board be returned to Acromag for repair. The board can be easily
damaged unless special SMT repair and service tools are used.
Further, Acromag has automated test equipment that thoroughly
checks the performance of each board. When a board is first
produced and when any repair is made, it is tested, placed in a burn-
in room at elevated temperature, and retested before shipment.
Please refer to Acromag's Service Policy Bulletin or contact
Acromag for complete details on how to obtain parts and repair.
PRELIMINARY SERVICE PROCEDURE
Before beginning repair, be sure that all of the procedures in
Section 2, Preparation For Use, have been followed. Also, refer to
the documentation of your carrier/CPU board to verify that it is
correctly configured. Replacement of the module with one that is
known to work correctly is a good technique to isolate a faulty
module.
CAUTION: POWER MUST BE TURNED OFF BEFORE
REMOVING OR INSERTING BOARDS
Acromag’s Application Engineers can provide further technical
assistance if required. When needed, complete repair services are
also available from Acromag.
6.0 SPECIFICATIONS
PHYSICAL
Physical Configuration…….…... Single PMC Module.
Height..............................… 15.11mm (0.595 in).
(See Drawing 4501-859)
Stacking Height.................
…
10.0 mm (0.394 in).
Length...............................
…
149.0 mm (5.866 in).
Width..............................….
.
74.0 mm (2.913 in).
Board Thickness.............…. 1.59 mm (0.062 in).
Connectors:
PCI Local Bus Interface...... Two 64-pin female receptacle
header (AMP 120527-1 or
equivalent).
Field I/O……..................…. 50-pin, SCSI-2, female receptacle
header (AMP 787082-5 or
equivalent).
Power Requirements PMC440
5V1Typical 160 mA
(±5%) Max. 185 mA
+12V Typical Not Used
(±5%) Max.
-12V Typical Not Used
(±5%) Max.
1. Maximum rise time of 100 millisecends
ENVIRONMENTAL
Operating Temperature.......…… 0 to +70°C.
Relative Humidity…....................
.
5-95% Non-Condensing.
Storage Temperature.…............. -55°C to 125°C.
Isolation……....................…...…
.
Logic and field connections are
optically isolated (see INPUT
specifications). Individual ports
are also isolated from each other.
However, input lines of individual
ports share a common connection
and are not isolated from each
other. Separate port commons are
provided to facilitate port-to-port
isolation. Logic and field lines are
isolated from each other for
voltages up to 250VAC, or 354V
DC on a continuous basis (unit will
withstand a 1500V AC dielectric
strength test for one minute
without breakdown). This complies
with test requirements outlined in
ANSI/ISA-S82.01-1988 for the
voltage rating specified.
Radiated Field Immunity (RFI).. Designed to comply with IEC1000-
4-3 Level 3 (10V/m, 80 to
1000MHz AM & 900MHz. Keyed)
and European Norm EN50082-1
with no data upsets.

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Electromagnetic Interference
Immunity (EMI)…...…..……...... No data upsets under the influence
of EMI from switching solenoids,
commutator motors, and drill
motors.
Surge Immunity……………….… Not required for signal I/O per
European Norm EN50082-1.
ESD Protection……..........….... Complies with IEC1000-2 Level 1
(2KV direct contact discharge at
input/output terminals) and
European Standard
EN50082-1.
Electric Fast Transient
Immunity (EFT)……………..….. Complies with IEC1000-4-4 Level
2 (0.5KV at field input and output
terminals) and European Norm
EN50082-1.
Radiated Emissions ………....... Meets or exceeds European Norm
EN50081-1 for class A equipment.
Warning: This is a class A product. In a domestic environment
this product may cause radio interference in which the
user maybe required to take adequate measures.
Reliability Prediction
Mean Time Between Failure…... MTBF = TBD hours (not available
at time of printing) @ 25°C,
Using MIL-HDBK-217F, Notice 2.
INPUTS
Input Channel Configuration……32 Optically isolated bipolar inputs.
For DC or AC voltage applications
within specified range limits.
Isolation Medium........................
.
Photo-transistor optocoupler,
Siemans SFH628A-4 or
equivalent. UL & VDE rated for
isolation voltage applications up to
400V DC or AC rms (optocoupler
only).
Bipolar Input Voltage Range....... AC or DC Volts peak, according to
model number: ±4V to ±18V
(Model PMC440-1); ±16V to ±
40V (Model PMC440-2); ±38V to
±60V (Model PMC440-3). Range
is determined by value of the input
current limiting SIP resistors
installed on the module (R5, R6,
R7, R8).
Input Threshold..........................
.
Input Low-to-High threshold is ±4V
Maximum, ±2.0V Typical
(PMC440-1); ±16V Maximum,
±6.4V Typical (PMC440-2); or
±38V Maximum, ±12.9V Typical
(PMC440-3). The PMC440-1
model may be used to interface
with open-drain TTL outputs when
used with an appropriate pullup to
+5V.
Input Hysteresis.........................
.
80mV Typical.
Input Capacitance……….……...
.
45pF Typical.
Turn-On Time.............................Measured to the point of positive
event interrupt detection (INTA#
pulled low) - 15us Typical (25°C)
for a 0 to threshold value input
step. This time decreases as the
magnitude of the step is increased
above the threshold.
Turn-Off Time............................
.
Measured to the point of negative
event interrupt detection (INTA#
pulled low) - 35us Typical (25°C)
for a threshold to 0V input step.
This time increases as the
magnitude of the step value is
increased from the threshold.
Input Debounce.......................... Each input includes debounce
circuitry with variable debounce
times. Debounce times are
programmable and derived from
the 8MHz system clock, in
combination with the debounce
duration register value. Debounce
times are applied at the ASIC input
and do not include optocoupler
delay time. Debounce values of 3-
4us, 48-64us, 0.75-1ms, and 6-
8ms may be configured. Note that
the debounce clock must be
enabled via the Debounce Select
register to utilize debounce.
Interrupts.................................... 32 channels of interrupts may be
configured for high-to-low, low-to-
high, and change-of-state (two
inputs required) event types.
Forward Voltage Drop.................1.1V Typical, 1.5V Maximum
(Diode) + I*R. Series input
current-limiting resistors are 2.2K
(PMC440-1), 12K (PMC440-2), or
27K (PMC440-3) and installed on
board.
Input Current..............................
.
Varies according to model number
and input signal voltagelevel. For
Model PMC440-1, the current is
computed by dividing the signal
level minus 1.5V, byits current
limiting resistor (2200Ωfor
PMC440-1, 12000Ωfor PMC440-
2, and 27000Ωfor PMC440-3).
PCI Local Bus Interface
Compatibility......................…..... Conforms to PCI Local Bus
Specification, Revision 2.2 and
PMC Specification, P1386.1/Draft
2.4. (See Note 2)
Electrical/Mechanical Interface... Single-Width PMC Module.
PCI Target ……………………… Implemented byAltera FPGA.
4K Memory Space Required…
…
One Base Address Register.
PCI commands Supported…….. Configuration Read/Write,
Memory Read/Write, 32,16, and 8-
bit data transfer types supported.
Signaling………………………… 5V Compliant, 3.3V Tolerant.
PCI bus Write Cycle Time1…… 150 nS Typical measured from
falling edge of FRAME# to the
falling edge of TRDY#.

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PCI bus Read Cycle Time1…… 150 nS Typical.
Notes (PCI Local Bus Interface):
1. Although the typical read or write PCI bus cycle time is only
150nS the actual read or write implemented on the PMC
Module will be typically 1000 nS. Thus, the PMC Module will
issue a RETRY when a new read or write cycle is implemented
before the PMC modules 1000 nS read or write has completed.
When the PMC Module issues a RETRY this frees the PCI
bus while the previous read or write operation is completed.
2. Due to the unique modular nature of the PMC440 assembly, it
is impossible to comply with the solder side component height
per the PMC Mechanical Standand. Refer to Mechanical
Assembly Drawing 4501-859 for details. You must determine
whether there will be adequate clearance for your application.
APPENDIX
CABLE: MODEL 5028-187 (SCSI-2 to Flat Ribbon, Shielded)
Type: Round shielded cable, 50-wires (SCSI-2 male connector at
one end and a flat female ribbon connector at the other end).
The cable length is 2 meters (6.56 feet). This shielded cable is
recommended for all I/O applications (both digital I/O and
precision analog I/O).
Application: Used to connect Model 5025-552 termination panel to
the PMC Module.
Length: Standard lenght is 2 meters (6.56 feet). Consult factory for
other lenghts. It is recommended that this length be kept to a
minimum to reduce noise and power loss.
Cable: 50 conductors, 28 AWG on 0.050 inch centers (permits
mass termination for IDC connectors), foil/braided shield inside
a PVC jacket.
Connectors: (One End): SCSI-2, 50-pin male connector with
backshell and spring latch hardware.
(Other End): IDC, 50-pin female connector with strain
relief.
Keying: The SCSI-2 connector has a “D Shell” and the IDC
connector has a polarizing key to prevent improper installation.
Schematic and Physical Attributes: See Drawing 4501-758.
Electrical Specifications: 30 VAC per UL and CSA (SCSI-2
connector spec.’s). 1 Amp maximum at 50% energized
(SCSI-2 connector spec.’s).
Operating Temperature: -20°C to +80°C.
Storage Temperature: -40°C to +85°C.
Shipping Weight: 1.0 pound (0.5Kg), packed.
TERMINATION PANEL: MODEL 5025-552
Type: Termination Panel For PMC Module Boards
Application: To connect field I/O signals to the PMC Module.
Termination Panel: Acromag Part 4001-040 (Phoenix Contact
Type FLKM 50). The 5025-552 termination panel facilitates the
connection of up to 50 field I/O signals and connects to the
PMC Module via a flat ribbon cable (Model 5025-551-x). Field
signals are accessed via screw terminal strips. The terminal
strip markings on the termination panel (1-50) correspond to
field I/O (pins 1-50) on the PMC module. Each PMC module
has its own unique pin assignments. Refer to the PMC module
manual for correct wiring connections to the termination panel.
Schematic and Physical Attributes: See Drawing 4501-464.
Field Wiring: 50-position terminal blocks with screw clamps. Wire
range 12 to 26 AWG.
Mounting: Termination panel is snapped on the DIN mounting rail.
Printed Circuit Board: Military grade FR-4 epoxy glass circuit board,
0.063 inches thick.
Operating Temperature: -40°C to +100°C.
Storage Temperature: -40°C to +100°C.
Shipping Weight: 1.25 pounds (0.6kg) packaged.

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