
vii PCI-1750/PCI-1750SO User Manual
Contents
Chapter 1 Overview...............................................1
1.1 Introduction ............................................................................................... 2
1.2 Features .................................................................................................... 2
1.3 Applications............................................................................................... 2
1.4 Specifications ............................................................................................ 2
Chapter 2 Installation...........................................5
2.1 Initial inspection......................................................................................... 6
2.2 Unpacking ................................................................................................. 6
2.3 Location of Connectors ............................................................................. 7
Figure 2.1 Location of Jumper and DIP switch ............................ 7
Table 2.1: JP2 : Power on configuration after hot reset .............. 7
Table 2.2: Board ID Setting (SW1) .............................................. 8
2.4 PCI-1750/PCI-1750SO Block Diagram ..................................................... 9
Figure 2.2 Block Diagram ............................................................ 9
2.5 Connector Pin Assignments ................................................................... 10
Table 2.3: Signal Description of I/O Connectors ....................... 10
2.6 Installation Instructions............................................................................ 12
Chapter 3 Operation............................................13
3.1 Operation ................................................................................................ 14
3.2 Isolated Digital I/O Ports ......................................................................... 14
3.2.1 Introduction ................................................................................. 14
3.2.2 Interrupt function of the DIO signals ........................................... 14
3.2.3 Power On Configuration.............................................................. 14
3.2.4 Isolated Inputs............................................................................. 15
Figure 3.1 PCI-1750 / PCI-1750SO isolated digital input connec-
tion............................................................................ 15
3.2.5 Isolated Outputs.......................................................................... 16
Figure 3.2 PCI-1750 isolated digital output connection (sink type)
16
Figure 3.3 PCI-1750SO isolated digital output connection (source
type).......................................................................... 16
3.3 Timer and Counter .................................................................................. 17
3.3.1 Introduction ................................................................................. 17
Figure 3.4 Block diagram of timer/counter................................. 17
3.3.2 Timer/Counter Frequency and Interrupt...................................... 17
3.3.3 One Shot and Interrupt ............................................................... 18
3.4 Interrupt Function .................................................................................... 19
3.4.1 Introduction ................................................................................. 19
3.4.2 IRQ Level .................................................................................... 19
3.4.3 Interrupt Control Register [Base + 32(Dec)] ............................... 19
Table 3.1: Interrupt control register bit map............................... 19
3.4.4 Interrupt Source Control.............................................................. 20
Figure 3.5 Interrupt source control............................................. 20
Table 3.2: Interrupt mode bit values .......................................... 20
3.4.5 Interrupt Triggering Edge Control ............................................... 20
Table 3.3: Triggering edge control bit values ............................ 20
3.4.6 Interrupt Flag Bit ......................................................................... 21
Table 3.4: Interrupt flag bit values ............................................. 21