Agilent Technologies 34950A User manual

Agilent Technologies
Agilent 34950A
64-Bit Digital I/O and
Counter Module
User’s Guide
Agilent Technologies, Inc.
Printed in Malaysia
Edition 1
June 2008 E0608
*34980-90050*
34980-90050

Notices
© Agilent Technologies, Inc. 2008
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Manual Part Number
34980-90050
Edition
First Edition, June 2008
Printed in Malaysia
Agilent Technologies, Inc.
3501 Stevens Creek Blvd
Santa Clara, CA 95052 USA
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Software Revision
This guide is valid for the firmware that
was installed in the instrument at the time
of manufacture. However, upgrading the
firmware may add or change product
features. For the latest firmware and
documentation, go to the product page at:
www.agilent.com/find/34980A
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CAUTION
A CAUTION notice denotes a haz-
ard. It calls attention to an operat-
ing procedure, practice, or the like
that, if not correctly performed or
adhered to, could result in damage
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conditions are fully understood and
met.
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operating procedure, practice, or
the like that, if not correctly per-
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in personal injury or death. Do not
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tions are fully understood and met.
ii Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide

Additional Safety Notices
The following general safety precautions
must be observed during all phases of oper-
ation of this instrument. Failure to comply
with these precautions or with specific
warnings or instructions elsewhere in this
manual violates safety standards of design,
manufacture, and intended use of the
instrument. Agilent Technologies assumes
no liability of the customer’s failure to com-
ply with the requirements.
General
Do not use this products in any manner not
specified by the manufacturer. The protec-
tive features of this product may be
impaired if it is used in a manner not speci-
fied in the operation instructions.
Before Applying Power
Verify that all safety precautions are taken.
Make all connections to the unit before
applying power.
Ground the Instrument
This product is provided with protective
earth terminals. To minimize shock hazard,
the instrument must be connected to the
ac power mains through a grounded power
cable, with the ground wire firmly con-
nected to an electrical ground (safety
ground) at the power outlet. Any interrup-
tion of the protective (grounding) conduc-
tor or disconnection of the protective earth
terminal will cause a potential shock haz-
ard that could result in personal injury.
Do Not Operate in an Explosive
Atmosphere
Do not operate the instrument in the pres-
ence of flammable gases or fumes.
Do Not Remove the Instrument
Cover
Only qualified, service-trained personal
who are aware of the hazards involved
should remove instrument covers. Always
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cover.
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Waste Electrical and Electronic
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2002/96/EC
This product complies with the WEEE
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Product Category: With reference to the
equipment types in the WEEE directive
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Alternating current
Frame or chassis
terminal
Standby supply. Unit is
not completely
disconnected from ac
mains when switch is off
Caution, risk of electric
shock
Caution, refer to
accompanying description
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide iii

iv Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
The Declaration of Conformity (DoC) for the 34980A mainframe
instrument can be found on page iii in the 34980A Mainframe User’s
Guide. That DoC applies to the 34980A mainframe and all available
plug- in modules.

Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide v
Contents
34950A 64-Bit Digital I/O Module with Memory and Counter . . . . . . . . . . . . . . . . . . . . . . .1
Bank and Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Electrical Characteristics for Digital I/O Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Operating Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Basic Digital I/O Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Channel Numbering and Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Reading Digital Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Writing Digital Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Channel Width and Polarity, Threshold, Level, and Drive . . . . . . . . . . . . . . . . . . . . . . . .6
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Setting the Handshake Line Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Synchronous Handshake Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Buffered I/O Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Buffered (Memory) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Deleting Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Buffered (Memory) Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Interrupt Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Memory Output Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Memory Input Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Pattern Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Totalizer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Initiated Measurement Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
34950A D-Sub Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
34950T Terminal Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

vi Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide

34950A 64-Bit Digital I/O Module with Memory and Counter
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 1
34950A 64-Bit Digital I/O Module with Memory and Counter
The 34950A has 64- bits of general-purpose digital I/O grouped in 8-bit
channels with programmable polarity, input thresholds, and output levels.
The module is segmented into two banks of four 8-bit channels. Each bank
has 64 Kb of volatile memory for pattern capture and pattern generation
with hardware interrupt capability. Up to three pins of handshaking are
available for each bank of 32 bits.
The module also has two 10 MHz frequency counter/totalizer measurement
input channels and a programmable clock output for frequency
synchronization or general clocking needs.
Bank and Channel Assignments
The digital channels are numbered by bank; 101 through 104 and 201
through 204 for banks 1 and 2 respectively. The counter/totalizer channels
are assigned channel numbers 301 and 302. The programmable clock is not
assigned a channel number.
Clock
Out
24 Bits
20 MHz - 10 Hz
CLK
32 Bits Counter/
Totalizer
2
IN
Gate
32 Bits Counter/
Totalizer
1
IN
Gate
Channel
301
Channel
101
Bit 0
Bit 7
Bit 8
Bit 15
Bit 16
Bit 23
Bit 24
Bit 31
Channel
102
Channel
103
Channel
104
DIO
Bank
1
8
8
8
8
INTR
Bank 1
Channel
201
Bit 0
Bit 7
Bit 8
Bit 15
Bit 16
Bit 23
Bit 24
Bit 31
Channel
202
Channel
203
Channel
204
DIO
Bank
2
8
8
8
8
INTR
Bank 2
H0
H1
H2
H0
H1
H2
Channel
302

2 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
34950A 64-Bit Digital I/O Module with Memory and Counter
Electrical Characteristics for Digital I/O Lines
The following simplified schematic shows the interface circuitry and
specifications for each of the 64 digital I/O lines:
Operating Considerations
See the Introduction to the Plug In Modules chapter of the 34980A
Mainframe User’s Guide for detailed environmental operating conditions
for the 34980A mainframe and its installed modules. That guidance sets
maximum per channel current and power ratings at rated voltage for
pollution degree 1 (dry) and pollution degree 2 (possible condensation)
conditions, for the Digital I/O module.
VREF
OE
DOUT
DIN
EN Zo = 10Ω
2.5 pF
VTHREF
+5V
+
-
1M
14.7 26.1
10K Vcc
+5V
+5.1V
I/O
1 of 64
Rpullup
Active Drive:
Vin 0V – 5V
Vout (L) 0.24V < Vout < 0.55V
4 m A < I o u t < 24mA
Vout (H) 1.6V < Vout < 5V
-4mA < Iout < - 2 4 m A
Open Collector:
Vout 0V – 5V
-4 mA < Iout < -24mA
Vcc (< 2V)
Vcc (> 2V)
215Ω< Rpullup < 1 kΩ
215Ω< Rpullup < 10 kΩ

Basic Digital I/O Operations
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 3
Basic Digital I/O Operations
Channel Numbering and Width
The digital channels are numbered by bank; 101 through 104 and 201
through 204 for banks 1 and 2 respectively.
Using SCPI commands you can group digital I/O channels together to
allow 16- or 32- bit operations. The first and third channels on a bank can
be control channels. Width and direction of the memory operations are
controlled by the width and direction of the first channel on the bank
(i.e., 101 or 201). In the SCPI language for the 34950A, BYTE refers to
8- bit operations, WORD refers to 16- bit operations, and LWORd refers to
32- bit operations.
This table illustrates how the channels are numbered for each operating
configuration.
Bank 1 Bank 2
Channel
BYTE (default) 101 102 103 104 201 202 203 204
8-bits 8-bits 8-bits 8-bits 8-bits 8-bits 8-bits 8-bits
WORD 101 103 201 203
16-bits 16-bits 16-bits 16-bits
LWORd 101 201
32-bits 32-bits

4 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
Basic Digital I/O Operations
Reading Digital Data
The simplest way to read a digital channel is using the MEASure:DIGital?
query. This query sets the channel to be an input channel and sets all
other channel parameters to the default settings.
For example, sending the following SCPI command to a Digital I/O module
installed in slot 1 of the mainframe will read the value of the 8- bit
channel 102. An unsigned integer value is returned that represents the
state of the 8 bits on channel 102.
MEAS:DIG? BYTE, (@1102)
By adding parameters to the command, you can set the channel width,
polarity, and threshold for read. For example, sending the following SCPI
command you can read the 32- bit channel 201.
MEAS:DIG? LWOR, (@1201)
To read digital data with more control over the channel parameters,
use the SCPI CONFigure and SENSe commands. The CONFigure commands
set up the digital I/O channel parameters. For example, sending the
following SCPI command to a Digital I/O module installed in slot 1 of the
mainframe, sets a 16- bit input channel (103) to use a 2.5 V input
threshold, and normal polarity.
CONF:DIG WORD, 2.5, NORM, (@1103)
Once configured, the data is read using the following command.
SENS:DIG:DATA:WORD? (@1103)
You may also read an individual bit using the SENSe commands.
This allows you to check the state of an individual bit in a channel
without having to create an input mask. For example, the following
command returns the state of bit 3 in the channel 101 byte.
SENS:DIG:DATA:BIT? 3, (@1101)
The acceptable range for the bit parameter is based on the channel width
as shown below:
•BYTE (8- bit): <bit> can range from ‘0’ to ‘7’
•WORD (16- bit): <bit> can range from ‘0’ to ‘15’
•LWORd (32- bit): <bit> can range from ‘0’ to ‘31’
The SENSe command differs from the MEASure command in that it will not
change the direction (input or output) of the channel. If the channel is
configured as an output, the SENSe command will return the value being
driven.

Basic Digital I/O Operations
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 5
Writing Digital Data
To write digital data, set the channel output parameters using the SOURce
commands. For example, sending the following SCPI commands to a Digital
I/O module in slot 1 sets a 32-bit channel to use normal polarity,
with active drive and a ‘set’ output voltage of 4 volts.
CONF:DIG:WIDT LWOR,(@1201)
CONF:DIG:POL NORM,(@1201)
SOUR:DIG:DRIV ACT,(@1201)
SOUR:DIG:LEV 4,(@1201)
The width and polarity parameters apply to both input and output
operations.
You can set a channel to output in either active drive or open collector
configurations. When set to ACTive, the module drives the digital lines for
both high and low. The voltage level that represents a logic ‘1’ can be set
using the SOURce:DIGital:LEVel command. Output voltages can range
from 1.66 V (default) to 5 V.
When the channel is set to OCOLlector, lines are driven low, but set to
high impedance (Hi- Z) when asserted. In the open collector mode, multiple
lines can be connected together by providing external pull- ups.
Once a channel has been configured, write digital data to the channel
using the SOURce:DIGital:DATA command.
SOUR:DIG:DATA:LWOR 26503,(@1201)
You may also use a hexadecimal format to represent values in the
commands. For example, to send the decimal value of 26503 in hex use
the command form:
SOUR:DIG:DATA:LWOR #h6787,(@1201)
Note that the data should match the channel width configured using
CONFigure:DIGital:DATA:WIDTh command. The data written is masked
by the configured width so that any extra bytes will be discarded.
For example: sending the value 65531 to a byte wide channel will result
in the channel discarding the upper byte and outputting 251.
NOTE When using external pull-ups in the open collector mode, the outputs will
not exceed 5 V.
NOTE Writing to a channel automatically configures the channel as an output.

6 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
Basic Digital I/O Operations
Channel Width and Polarity, Threshold, Level, and Drive
When the width of a channel is set to WORD or LWORd, the channel
direction (input or output) of the channels spanned by the width is
controlled by the channel in operation. That is, all grouped channels are
automatically set to the same input or output operation.
Channel settings of polarity, threshold, level, and drive mode are
unchanged when channels are combined. For example, consider the
following command sequence.
CONF:DIG:POL NORM,(@1101)
CONF:DIG:POL INV,(@1102)
CONF:DIG:WIDT WORD,(@1101)
This command sequence set the first 8 bits (channel 101) to normal
polarity for input and output operations, set the next 8 bits (channel 102)
to inverted polarity, and then combines the bits into a 16- bit channel.
When this WORD channel is used, the first eight bits will input or output
using normal polarity but the next 8 bits will read or written using
inverted polarity.
Threshold, level, and drive settings all behave in the same manner as the
polarity setting described above.

Handshaking
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 7
Handshaking
Handshaking provides a means to synchronize the input or output of
digital data. By default, no handshaking is used; data is input or output as
the command is executed. The handshake is configured per bank.
The 34950A provides a synchronous handshake mode (strobe handshake).
You can use this mode with basic input and output operations. You must
use this handshake mode to use buffered I/O (see “Buffered I/O
Operations” on page 14).
The handshake is performed using three lines on each bank. The lines are
labeled H0, H1, and H2. The function of each line is set by the input or
output mode in use. Since there are only three handshake lines per bank,
the SCPI handshake commands are only valid for the first channel in a
bank. Once handshaking is enabled, it applies to the width of the first
channel in the bank.
The three handshaking lines on each bank also differ slightly if you are
using buffered (memory) I/O (see page 14) or unbuffered I/O operations.
You can also perform unbuffered operations without any handshake. The
function of each line for each mode of operation is defined in the table
below.
The following handshake command sets the synchronous handshaking
mode for the channels in bank 1.
CONF:DIG:HAND SYNC, (@1101)
This form of the handshaking command also allows you to optionally set
the input threshold, output drive level, and polarity of all the handshake
lines. For example, the following command sets bank 2 to use synchronous
handshaking, with an input threshold of 2.5 V, an output drive level of
2.5 V, and normal polarity. Other parameters such as the handshake
timing are set to default values (refer to the Programmer’s Reference
Help file for details).
CONF:DIG:HAND SYNC, 2.5, 2.5, NORM, (@1201)
H0 H1 H2
Unbuffered Synchronous Input I/O Direction (output) Strobe (output) Not Used (Hi-Z)
Unbuffered Synchronous
Output
I/O Direction (output) Strobe (output) Not Used (Hi-Z)
Buffered Synchronous Input Start/Stop (output) Not Used (Hi-Z) Input Strobe (input)
Buffered Synchronous Output
(internal clock)
Start/Stop (output) Strobe (output) Not Used (Hi-Z)
Buffered Synchronous Output
(external clock)
Start/Stop (output) Not Used (Hi-Z) Output Strobe (input)

8 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
Handshaking
You can set parameters by using a sequence of commands instead of the
CONFigure macro command. For example, the following command sequence
sets the handshaking mode to synchronous, the output drive to open
collector, and the handshake rate to 1 MHz.
CONF:DIG:HAND:MODE SYNC, (@1101)
CONF:DIG:HAND:DRIV OCOL, (@1101)
CONF:DIG:HAND:RATE 1000000, (@1101)
Setting the Handshake Line Parameters
You can set the handshake lines’ input threshold, output drive mode, and
output drive voltage. These settings affect all the handshake lines in the
bank. Handshake line polarity can be set for each individual handshake
line.
For example, you can invert the polarity of the handshake line H1 on
bank 2 with the following command.
CONF:DIG:HAND:POL INV, H1, (@1201)
You can set the output drive mode, output voltage, and input threshold for
all handshake lines in each bank. For example, the following commands set
the drive mode to active, the drive voltage to 4.5 V, and the input
threshold to 1.0 V on bank 2.
CONF:DIG:HAND:DRIV ACT, (@1201)
SOUR:DIG:HAND:LEV 4.5, (@1201)
SENS:DIG:HAND:THR 1, (@1202)
NOTE The settings for drive mode, output drive level, and input threshold also
apply to the bank’s interrupt line.
NOTE When using external pull-ups in the open collector mode, the outputs will
not exceed 5 V.

Handshaking
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 9
Synchronous Handshake Mode
In the synchronous handshake mode, a strobe or clock signal is used to
transfer data to or from an external device. The strobe line (H1) is an
output and is pulsed once for each transfer.
Synchronous Unbuffered Inputs
For synchronous handshake unbuffered inputs the H0 line indicates the
direction of the transfer. This line is set high to indicate an input
operation. The H0 line will remain in the high state until the 34950A
direction is changed. The H1 line is the strobe output line. The H2 line is
not used and is set to high impedance.
The timing of the input operation is controlled by the TCYCLE parameter
set using the CONFigure:DIGital:HANDshake:RATE command. This setting
affects strobe width, memory clock rate, as well as the setup and hold
times. Alternatively, the reciprocal form of the command
CONFigure:DIGital:HANDshake:CTIMe can be used to specify the speed in
terms of time instead of a rate. TCYCLE begins when the 34950A executes
one of the input commands.
The timing should be set such that the device sending the data ensures
the data lines are valid prior to TSETUP time. The trailing edge of the
strobe line indicates the 34950A will latch the data within the THOLD time.
TSETUP is 90 ns and THOLD is 0 ns. Since THOLD = 0 µs, the sending device
can use the trailing edge of the strobe to initiate a change in the data
lines.
A synchronous unbuffered input is shown in the diagram below
(default handshake line polarity).
For example, the following SCPI commands set a 34950A in slot 5 to have
a 16- bit input using synchronous handshake. Two data inputs are then
performed and the strobe line is pulsed for each query. The I/O direction
line is set high following the first SENSe:DIGital:DATA:WORD? query and
remains high until the digital channel is reset or reconfigured.
CONF:DIG:WIDT WORD, (@5101)
CONF:DIG:DIR INP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
SENS:DIG:DATA:WORD? (@5101)
SENS:DIG:DATA:WORD? (@5101)
H0 (Direction)
H1 (Strobe)
Data In
Don't-Care Valid Don't-Care
T
SETUP
T
HOLD
T
CYC LE
T
CYC LE
/2 T
CYC LE
/2

10 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
Handshaking
Synchronous Unbuffered Outputs
For synchronous handshake unbuffered outputs, the H0 line indicates the
direction of the transfer. This line is set low to indicate an output
operation. The H0 line will remain in the low state until the 34950A
direction is changed. The H1 line is the strobe output line.
When the 34950A executes an output command, it sets the data lines and
waits for TCYCLE/2 before asserting the strobe line. The leading edge of the
strobe indicates the data is valid. The strobe line is asserted for TCYCLE /2
and then de- asserted. The H2 line is not used and is set to high
impedance.
The timing of the output operation is controlled by the TCYCLE parameter
set using the CONFigure:DIGital:HANDshake:RATE command. This setting
affects strobe width, memory clock rate, as well as the setup and hold
times. Alternatively, the reciprocal form of the command
CONFigure:DIGital:HANDshake:CTIMe can be used to specify the speed in
terms of time instead of a rate. The timing should be set such that the
device receiving the data can read the data lines during the TCYCLE/2 time.
A synchronous unbuffered output is shown in the diagram below (default
handshake line polarity).
For example, the following SCPI commands set a 34950A in slot 5 to have
a 16- bit output using synchronous handshake. Two data outputs are then
performed and the strobe line is pulsed for each. The I/O direction line is
set low following the first SOURce:DIGital:DATA:WORD command and
remains low until the digital channel is reset of reconfigured.
CONF:DIG:WIDT WORD, (@5101)
CONF:DIG:DIR OUTP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
SOUR:DIG:DATA:WORD #hFFFF, (@5101)
SOUR:DIG:DATA:WORD #h4DB5, (@5101)
H0 (Direction)
H1 (Strobe)
Data Out
Invalid Valid
T
CYC LE
T
CYC LE
/2 T
CYC LE
/2

Handshaking
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 11
Synchronous Buffered Inputs
You can use synchronous mode handshake with buffered (memory) input
operations. (Buffered operations are described in more detail beginning on
page 14.) For buffered input operations, the H0 line acts as a start/stop
line. This line will be set high when the memory input command is
executed and will return low when the memory input operation has
completed. The H1 line is not used and is set to high impedance.
An external strobe input on the H2 line controls the pace of memory
transfers. The sending device must ensure the data is valid before the
TSETUP and stays valid until after THOLD. TSETUP is 46 ns and THOLD is
10 ns.
A synchronous buffered input using an external clock is shown in the
diagram below (default handshake line polarity).
For example, the following SCPI commands set a 34950A in slot 5 to have
an 8- bit input using synchronous handshake with an external strobe input.
The number of bytes to read into memory is set to infinite (continuous
reading into memory until the memory is stopped). The memory is
enabled and then triggered. The start/stop line is set high following the
first byte handshake and remains high until the last byte is captured.
CONF:DIG:WIDT BYTE, (@5101)
CONF:DIG:DIR INP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
SENS:DIG:MEM:SAMP:COUN 0, (@5101)
SENS:DIG:MEM:ENAB ON, (@5101)
SENS:DIG:MEM:STAR (@5101)
H0 (Start/
Stop)
H2(Strobe In)
Data In
Valid Don't-Care
T
SETUP
T
HOLD
T
CYCLE
>100 ns
T
SETUP
T
HOLD
Valid
(LastCycle)
Don't-Care Don't-Care Don't-CareValid
>50ns

12 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
Handshaking
Synchronous Buffered Outputs
You can use synchronous mode handshake with buffered (memory) output
operations. (Buffered operations are described in more detail beginning on
page 14.) For buffered output operations, the H0 line acts as a start/stop
line. This line will be set high when the memory output command is
executed by the 34950A and will return low when the memory output
operation has completed.
Synchronous memory output operations can be paced using either the
internal strobe or an external strobe.
When using the internal strobe, the H1 line is the strobe output line.
The timing of the output operation when using the default INTernal clock
is controlled by the CONFigure:DIGital:HANDshake:RATE command.
This setting affects strobe width, memory clock rate, as well as the setup
and hold times. Alternatively, the reciprocal form of the command
CONFigure:DIGital:HANDshake:CTIMe can be used to specify the speed in
terms of time instead of a rate. The timing should be set such that the
device receiving the data can latch the data lines during the TCYCLE time.
The receiving device should detect the leading edge of the strobe line, wait
for the 34950A to set the data (TPD) and then latch the data. Latching the
data on the trailing edge of the strobe is recommended, however, you can
the data following TPD. TPD ranges from -23 to 23 ns.
A synchronous buffered output using the internal clock is shown in the
diagram below (default handshake line polarity).
H0 (Start/Stop)
H1 (Strobe Out)
Data Out
Valid
T
CYC LE
(LastCycle)
Invalid
T
PD
T
PD
T
PD
T
CYC LE
/2

Handshaking
Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide 13
Optionally, you can provide an external strobe input on the H2 line to
control the memory transfers. If you pace the memory inputs from an
external clock, the 34950A will sense the leading edge of the strobe and
set the data. The data will be valid after TPD and the receiving device may
latch the data. TPD ranges from 82 ns to 47 ns.
A synchronous buffered output using an external clock is shown in the
diagram below (default handshake line polarity).
For example, using the internal strobe, the following SCPI commands set
a 34950A in slot 5 to have a 32- bit output using synchronous handshake.
The number of times to output the traces is set to 4. A trace is then
loaded into memory and assigned to the channel. The memory is enabled
and then triggered. The start/stop line is set high following the first byte
handshake and remains high until the last byte is output.
CONF:DIG:WIDT LWOR, (@5101)
CONF:DIG:DIR OUTP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
SOUR:DIG:MEM:NCYC 4, (@5101)
TRAC:DATA:DIG:LWOR (@5101), mytrace, #hFFEEFFEE, #hBCBC9999
SOUR:DIG:MEM:TRAC mytrace,(@5101)
SOUR:DIG:MEM:ENAB ON, (@5101)
SOUR:DIG:MEM:STAR (@5101)
Using an external strobe, the following SCPI commands set a 34950A in
slot 5 to have an 8-bit output using synchronous handshake with an
external strobe input. The number of times to output the traces is set to
infinite (continuous output until the memory is stopped). The memory is
enabled and then triggered. The start/stop line is set high following the
first byte handshake and remains high until the last byte is output.
CONF:DIG:WIDT BYTE, (@5101)
CONF:DIG:DIR OUTP, (@5101)
CONF:DIG:HAND SYNC, (@5101)
CONF:DIG:HAND:SYNC:STR:SOUR EXT, (@5101)
SOUR:DIG:MEM:NCYC 0, (@5101)
TRAC:DATA:DIG:BYTE (@5101), mytrace, 260, 139
SOUR:DIG:MEM:TRAC mytrace,(@5101)
SOUR:DIG:MEM:ENAB ON, (@5101)
SOUR:DIG:MEM:STAR (@5101)
H0 (Start/Stop)
H2(ClockIn)
Data Out
Valid
T
CYC LE
(LastCycle)
Invalid
T
PD
T
PD
T
PD

14 Agilent 34950A 64-Bit Digital I/O and Counter Module User’s Guide
Buffered I/O Operations
Buffered I/O Operations
Each of the two banks on the 34950A has its own memory that can be
used to store patterns to output (traces) or to store input patterns. The
width of the first channel in each bank controls the width of the memory
operations. Memory may be used as:
•64K x 8 bits
•64K x 16 bits
•32K x 32 bits
Buffered (Memory) Output
Each bank on the 34950A has its own memory for use in buffered
transfers. Changing a bank from an input to an output will clear all
memory for that bank. For buffered outputs, you download “traces” of
digital data to the memory. Multiple traces (up to 32) can be downloaded
into each bank. A specified trace is then output using the handshaking
parameters set.
The general steps to output from memory are:
1Set the channel width and direction.
2Set the handshake mode.
3Set the trigger source.
4Set the number of times to output the trace.
5Load the trace(s) into memory.
6Set which trace to use.
7Enable the memory.
8Trigger the output.
Set the channel width and direction. Use the SOURce:DIGital:DATA command
to set the channel width and set the channel as an output. Additionally,
the data specified in the command will be the initial state of the data
lines before the memory operation begins.
Set the handshake mode. You must use synchronous handshaking mode.
You can use either an internal or external strobe (clock) to pace the
outputs. Handshaking is described in more detail on page 7.
Set the trigger source. By default, the trigger source is set to use a
software trigger. You can also use one of the interrupt lines (see page
page 18) as a trigger source.