AHA StarLite AHA3431 User manual

PS3431-0500
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: [phone]
fax: [phone]
e-mail: [email protected]
www.aha.com
advancedhardwarearchitectures
Product Specification
AHA3431 StarLiteTM
40 MBytes/sec Simultaneous
Compressor/Decompressor IC, 3.3V

Advanced Hardware Architectures, Inc.
PS3431-0500 i
Table of Contents
1.0 Introduction . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. .1
1.1 Conventions, Notations and Definitions. . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . . .1
1.2 Features . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. .1
1.3 Functional Overview . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. .2
2.0 System Configuration . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .. . . . .3
2.1 Microprocessor Interface. . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . .3
3.0 Functional Description . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. .6
3.1 Data Ports . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . .6
3.2 DMA Mode. . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .. .6
3.3 Pad Word Handling in Burst Mode . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. .9
3.4 DMA Request Signals and Status. . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . .9
3.4.1 FIFO Thresholds. . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . .9
3.4.2 Request Duringan End-of-Record. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .10
3.4.3 Request StatusBits . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .10
3.5 Data Format. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .11
3.6 Odd Byte Handling . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .11
3.6.1 Compression Input and Pad Bytes. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .11
3.6.2 Compression Outputand Pad Bytes . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .11
3.6.3 DecompressionInput, PadBytes and Error Checking. . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .11
3.6.4 Decompression Outputand Pad Bytes . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .11
3.7 Video Interfaces.. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .12
3.7.1 Video Input. . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .12
3.7.2 Video Output. . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..12
3.8 Algorithm. . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .13
3.9 Compression Engine. . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..13
3.10 Decompression Engine. . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .13
3.11 Prearming . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .13
3.12 Interrupts. .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .14
3.13 DuplexPrinting . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .14
3.14 BlankBands . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . .14
3.15 Low Power Mode. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..14
3.16 Test Mode . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .14
4.0 Register Descriptions . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .. . . .15
4.1 System Configuration0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .17
4.2 System Configuration1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .17
4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .18
4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .18
4.5 Compression Ports Status, Address 0x04 -Read Only. . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .18
4.6 DecompressionPorts Status, Address 0x05 - Read Only. . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .19
4.7 Port Control, Address 0x06 - Read/Write . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..20
4.8 Interrupt Status/Control 1, Address 0x07 - Read/Write. . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .20
4.9 Interrupt Mask 1, Address 0x09 - Read/Write. . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .21
4.10 Version, Address 0x0A - Read Only . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . .21
4.11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . .. . . . . . . .. . . . .22
4.12 Compression Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write . . . . .. . . . . . . .. . . . . . . ..22
4.13 Compression Control, Address 0x14 - Read/Write . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . ..23
4.14 Compression Reserved, Address 0x15 - Read/Write . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . .23
4.15 Compression Line Length, Address 0x16, 0x17 -Read/Write. . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .24
4.16 Decompression Control, Address 0x18 - Read/Write . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .24
4.17 Decompression Reserved, Address 0x1A- Read/Write . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .25

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4.18 Decompression Line Length,Address 0x1C, 0x1D - Read/Write . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .25
4.19 Compression Record Count, Address0x20, 0x21- Read/Write. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . .25
4.20 InterruptStatus/Control 2,Address 0x27- Read/Write. . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..25
4.21 InterruptMask 2, Address 0x29 - Read/Write. . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..26
4.22 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . .. . . . . . . .. . . . . . . . .26
4.23 Compression Byte Count, Address0x30, 0x31,0x32, 0x33 -Read/Write . . . . . . . .. . . . . . . .. . . . . . . . .26
4.24 Compression Control Prearm, Address 0x34 - Read/Write. . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .26
4.25 Pattern, Address 0x35 -Read/Write . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .27
4.26 Decompression Control Prearm, Address 0x38 - Read/Write. .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .27
4.27 Decompression Reserved, Address 0x3A- Read/Write . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .27
5.0 Signal Descriptions . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . .27
5.1 Microprocessor Interface. . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .28
5.2 Data Interface . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..29
5.3 Video Interface . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..30
5.4 System Control . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .30
6.0 Pinout . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..31
7.0 DC Electrical Specifications . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .33
7.1 Operating Conditions. . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .33
7.2 Absolute Maximum Stress Ratings . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .33
8.0 AC Electrical Specifications . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .34
9.0 Package Specifications. . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .40
10.0 Ordering Information. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . ..41
10.1 AvailableParts. . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .41
10.2 Part Numbering. . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..41
11.0 Related Technical Publications . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .42
Appendix A:Additional Timing Diagrams for DMA Mode Transfers . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..43
Appendix B:Recommended Power Decoupling Capacitor Placement . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .50

Advanced Hardware Architectures, Inc.
PS3431-0500 iii
Figures
Figure 1: Functional Block Diagram . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. .2
Figure 2: Microprocessor PortWrite (PROCMODE[1:0]=“01”) . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . .4
Figure 3: Microprocessor PortRead (PROCMODE[1:0]=“01”). . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. .4
Figure 4: Microprocessor PortWrite (PROCMODE[1:0]=“11”) . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . .5
Figure 5: Microprocessor PortRead (PROCMODE[1:0]=“11”). . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. .5
Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100. . .. . . . . . . .. . . . . . . . . . . .. .7
Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100. . . . . . . . . . .. . . . . . . .. . . . . .7
Figure 8: DMA Mode Timing for Four WordBurst Write,One Wait State, Strobe Conditionof DSC=100. . . . . . . . .7
Figure 9: DMA Mode Timing for Four WordBurst Read, OneWait State,Strobe Condition of DSC=100. . . . . . .. .8
Figure 10: DMA Mode Timing for Eight Word Burst Write, ZeroWait State,Strobe Conditionof DSC=100 . . . . . . . .8
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . .8
Figure 12: FIFO ThresholdExample (IFT=4,DSC=2, 1 Word Already in FIFO). . . . . . . .. . . . . . . . . . . .. . . . . . . . .10
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010 . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .10
Figure 14: Timing Diagram, VideoInput . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .12
Figure 15: Timing Diagram, VideoOutput. . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..12
Figure 16: Pinout. . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .32
Figure 17: Data InterfaceTiming. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..34
Figure 18: Request Deasserts at EOR, Strobe Conditionof DSC=0-3, 6-7;ERC=0 . . . . . . . . . . . .. . . . . . . .. . . . .34
Figure 19: Request Deasserts at EOR, Strobe Conditionof DSC=0-3, 6-7;ERC=1 . . . . . . . . . . . .. . . . . . . .. . . . .35
Figure 20: Request Deasserts at EOR, Strobe Conditionof DSC=4 or 5; ERC=0. . . . . . . . . .. . . . . . . . . . . .. . . . .35
Figure 21: Request Deasserts at EOR, Strobe Conditionof DSC=4 or 5; ERC=1. . . . . . . . . .. . . . . . . . . . . .. . . . .35
Figure 22: Output Enable Timing . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..36
Figure 23: Video Input Port Timing . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . .36
Figure 24: Video Output Port Timing. . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..37
Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0). . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .37
Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1). . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .38
Figure 27: Interrupt Timing . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..39
Figure 28: Clock Timing . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .39
Figure 29: Power On Reset Timing. . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .39
Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000...............................................43
Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000...............................................43
Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=000 ...............43
Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000...............44
Figure A5: DMA Mode Timingfor Eight Word Burst Write, ZeroWait State, StrobeConditionof DSC=000..............44
Figure A6: DMA Mode Timingfor Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000..............44
Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010...............................................45
Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010...............................................45
Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010 ...............45
Figure A10:DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010...............46
Figure A11:DMA Mode Timingfor Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010..............46
Figure A12:DMA Mode Timing for Eight Word Burst Read,Zero Wait State, Strobe Condition of DSC=010..............46
Figure A13:DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011...............................................47
Figure A14:DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011...............................................47
Figure A15:DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011 ...............47
Figure A16:DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011...............48
Figure A17:DMA Mode Timingfor Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011..............48
Figure A18:DMA Mode Timing for Eight Word Burst Read,Zero Wait State, Strobe Condition of DSC=011..............48
Figure A19:DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111...............................................49
Figure A20:DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111...............................................49

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Tables
Table 1: Data Bus and FIFO Sizes Supported by AHA3431 .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. .2
Table 2: AHA3431 Connection to Host Microprocessors. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . .3
Table 3: Microprocessor PortConfiguration. .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . .4
Table 4: Internal StrobeConditions for DMA Mode. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. .6
Table 5: Internal Registers. . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .15
Table 6: Data Port Timing Requirements. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..34
Table 7: Request vs. EOR Timing . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .36
Table 8: Output Enable Timing Requirements. . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .36
Table 9: Video Input Port Timing Requirements . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .36
Table 10: Video Output Port Timing Requirements. . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..37
Table 11: Microprocessor Interface Timing Requirements . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..38
Table 12: Interrupt TimingRequirements.. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .39
Table 13: Clock Timing Requirements. . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . ..39
Table 14: Power On Reset Timing Requirements . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . .39

PS3431-0500 Page 1 of 50
Advanced Hardware Architectures, Inc.
1.0 INTRODUCTION
AHA3431 is a lossless compression
coprocessor IC for hardcopy systems on many
standard platforms. The device is targeted for high
throughput and high resolution hardcopy systems.
TheAHA3431isfunctionallybackwardcompatible
to the AHA3411.
Enhancements to this product over the
AHA3411 include improved I/O timings, higher
operating frequency and data rate, and lower power.
Blank band generation in real time and
prearming registers between records enable
advanced banding techniques. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropriate registers are prearmed when switching
from one type to the next. Separate byte ordering
between the Compressor and the Decompressor
with bit order control into the compressor allow full
reversal of the image data for duplex printing
support.A system mayuse multiplerecordcounters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.
This document contains functional description,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is intended for system designers considering a
compression coprocessor in their embedded
applications.Softwaresimulationandananalysisof
the algorithm for printer and copier images of
various complexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
systemdesign.Section11.0 containsalistofrelated
technical publications.
1.1 CONVENTIONS, NOTATIONS AND
DEFINITIONS
–Active low signals have an “N”appended to the
end of the signal name. For example, CSN and
RDYN.
–A“bar”over asignal nameindicatesan inverseof
the signal. For example, SD indicates an inverse
of SD. This terminology is used only in logic
equations.
–“Signal assertion”means the output signal is
logically true.
–Hex values are represented with a prefix of “0x”,
such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.
–A range ofsignal names orregister bits is denoted
by a set of colons between the numbers. Most
significant bit is always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.
–A logical “AND”function of two signals is
expressed with an “&”between variables.
–Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
–In referencing microprocessors, an x, xx or xxx is
used as suffix to indicate more than one
processor. For example, Motorola 68xxx
processor family includes various 68000
processors from Motorola.
–Reserved bits in registers are referred as “res”.
–REQN or ACKN refer to eitherCI, DI, CO orDO
Request or Acknowledge signals, as applicable.
1.2 FEATURES
PERFORMANCE:
•40 MBytes/sec maximum sustained compression
and decompression rate
•160 MBytes/sec burst data rate over a 32-bit data
bus
•40 MBytes/sec synchronous 8-bit video in and
video out ports
•Maximum clock speeds up to 40 MHz
•Simultaneous compression and decompression at
full bandwidth
•Average 15 to 1 compression ratio for 1200 dpi
bitmap image data
•Advanced banding support: blank bands,
prearming
FLEXIBILITY:
•Big Endian or Little Endian; 32 or 16-bit bus
width and data bit/byte reordering for duplex
printing support
•Programmable Record Length, Record Count and
Scan Length Registers may be prearmed
•Scan line length up to 2K bytes
•Interfaces directly with various MIPS, Motorola
68xxx and Cold FIRE, and Intel i960 embedded
processors
•Pass-through mode passes raw data through
compression and decompression engines
•Counter checks errors in decompression
SYSTEM INTERFACE:
•Single chip compression/decompression solution
–no external SRAM required
•Four 16 ×32-bit FIFOs with programmable
threshold counters facilitate burst mode transfers
OTHERS:
•Low power modes
•Software emulation program available
•128 pin quad flat package
•3.3V operation
•Test pin tristates outputs
•Firmware, Register, Pinout and Functional
compatible with 5V, AHA3411

Page 2 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Figure 1: Functional Block Diagram
1.3 FUNCTIONAL OVERVIEW
The coprocessor device has three external high
speed synchronous data ports capable of
transferring once every clock cycle. These are a 32-
bit bidirectional data port,an 8-bit Video Input Data
(VID) port and a Video Output Data (VOD) port.
The 32-bit port is capable of transferring up to 4
bytes per clock. The VID and VOD are capable of
up to one byte per clock.
The device accepts uncompressed datathrough
the 8-bit VID port or the 32-bit data port into its
Compression In FIFO (CI FIFO). The 32-bit data
port may be configured for 16-bit transfers.
Compressed data is available through the 32-bit
data port via the Compressed Output FIFO (CO
FIFO). The sustained data rate through the
compression engine is one byte per clock.
Decompression data may be simultaneously
processed by the device. Decompression data is
accepted through the 32-bit data port, buffered in
the Decompression Input FIFO (DI FIFO) and
decompressed.Theoutputdataismadeavailableon
the 32-bit data port via the Decompression Output
FIFO (DO FIFO) or the 8-bit Video Output port.
The decompression engine is capable of processing
an uncompressed byte every clock.
The four FIFOs are organized as 16×32 each.
For data transfers through the three ports, the
“effective”FIFO sizes differ according to their data
bus widths. The table below shows the size of the
data port and the “effective”FIFO size for the
various configurations supported by the device.
Table 1: Data Bus and FIFO Sizes Supported by AHA3431
(From Scanner)
VIREQN
VID[7:0]
VIACKN
D[31:0]
DRIVEN
TEST CLK RSTN PROCMODE[1:0] PD[7:0]
PA[5:0]
CSN DIR RDYN INTRN
VOACKN
VOD[7:0]
VOREQN
VOEORN
VOEOTN
(To Printer)
COEORN
DOREQN COREQN DIREQN CIREQN SD DOACKN COACKN DIACKN CIACKN
VID
PORT
DATA
PORT
CI
FIFO
16x32
DI
FIFO
16x32
CLOCK
DATA PORT CONTROL
COMPRESSOR
DECOMPRESSOR
MICROPROCESSOR INTERFACE
CO
FIFO
16x32
DO
FIFO
16x32
VOD
PORT
AHA3431
StarLiteTM
8
8 8
888
32
32 32
6
8
COEOTN
OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE
Compression Data In 8 Video In 16 x 8
Compression Data In/Out 32 Data Port 16 x 32
Compression Data In/Out 16 Data Port 16 x 16
Decompression Data In/Out 32 Data Port 16 x 32
Decompression Data In/Out 16 Data Port 16 x 16
Decompressed Data Out 8 Video Out 16 x 8

PS3431-0500 Page 3 of 50
Advanced Hardware Architectures, Inc.
Table 2: AHA3431 Connection to Host Microprocessors
Movement of data for compression or
decompression is performed using synchronous
DMA over the 32-bit data port. The Video ports
support synchronous DMA mode transfers. The
DMA strobe conditions are configurable for the 32-
bit data port depending upon the system processor
and the available DMA controller.
Data transfer for compression or
decompression is synchronous over the three data
ports functioning as DMA masters. To initiate a
transfer into or out of the Video ports, the device
assertsVxREQN, the externaldevicerespondswith
VxACKN and begins to transfer data over the VID
or VOD busses on each succeeding rising edge of
the clock until VxREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.
The sections below describe the various
configurations, programming and other special
considerations indeveloping a compression system
using AHA3431.
2.0 SYSTEM CONFIGURATION
This section provides information on
connecting AHA3431 to various microprocessors.
2.1 MICROPROCESSOR INTERFACE
The device is capable of interfacing directly to
various processors for embedded application. Table
2 and Table 3 show how AHA3431 should be
connected to various host microprocessors.
All register accesses to AHA3431 are
performed on the 8-bit PD bus. The PD bus is the
lowest byte of the 32-bit microprocessor bus.
During reads of the internal registers, the upper 24
bits are not driven. System designers should
terminate these lines with Pullup resistors.
AHA3431providesfourmodesofoperationfor
themicroprocessorport.Bothactivehighandactive
low write enable signals are allowed as well as two
modes for chip select. The mode of operation is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal selects when CSN must be
active and also how long an access lasts.
When PROCMODE[1] is high, CSN
determines thelength ofthe access. CSN must be at
least 5 clocks in length. On a read, valid data is
driven onto PD[7:0] during the 5th clock. If CSN is
longer than 5 clocks, thenvalid data continuesto be
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYNisdrivenhighasynchronously.CSNmustbe
high forat leasttwo clocks. RDYN is always driven
(itisnottristatedwhenPROCMODE[1]ishigh).The
mode is typical of processors such as the Motorola
68xxx.
When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is only driven during the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode istypical of RISC processors such as the i960.
PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pinisanactivelowwriteenable.IfPROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.
For additional notes on interfacing to various
microprocessors, refer to AHA Application Note
(ANDC16),Designer’sGuideforStarLiteTM Family
Products. AHA Applications Engineering is
available to support with other processors not in the
Designer’s Guide.
PIN NAME i960Cx i960Kx IDT3081 Motorola
MCFS102(ColdFIRE)
PA A LAD Latched Address Latched Address
CSN CS CS System Dependent Decoded Chip Select
DIR W/R W/R WR R/W
PD D LAD A/D A/D[7:0]
SD WAIT READY System Dependent System Dependent
RDYN No Connect READY ACK TA
DRIVEN DEN System Dependent System Dependent System Dependent
CLOCK PCLK No Connect SYSCLK BCLOCK

Page 4 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Table 3: Microprocessor Port Configuration
Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)
Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)
PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR
00 Active high write fixed i960
01 Active low write fixed
10 Active high write variable
11 Active low write variable 68xxx, MIPS R3000
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0 D1
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
A2
D1

PS3431-0500 Page 5 of 50
Advanced Hardware Architectures, Inc.
Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”)
Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”)
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0

Page 6 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
3.0 FUNCTIONAL DESCRIPTION
This section describes the various data ports,
special handling, data formats and clocking
structure.
3.1 DATA PORTS
AHA3431 contains two datainput ports, CI and
DI, and two data output ports, CO and DO on the
same 32-bit data bus, D[31:0]. Data transfers are
controlled by external DMA control. The logical
conditions under which data is written to the input
FIFOs or read from the output FIFOs are set by the
DSC (Data Strobe Condition) field of the System
Configuration 1 register.
A strobe condition defines under what logical
conditions the input FIFOs are written or the output
FIFOs read. CIACKN, COACKN, DIACKN,
DOACKN, and SD pins combine to strobe data in a
manner similar to DMA controllers. The DMA
Mode sub-section describes the various data strobe
options.
3.2 DMA MODE
On the rising edge of CLOCK when the strobe
condition is met, the port with the active
acknowledge either strobes data into or out of the
chip. No more than one port may assert
acknowledge at any one time. Table 4 shows the
various conditions that may be programmed into
register DSC.
Figure 6 through Figure 11 illustrate the DMA
mode timings for single, four word and eight word
burst transfers for DSC=100 selection. For other
DSC settings, please refer to Appendix A. Note that
the only difference between odd and even values of
DSC is the polarity of SD. Waveforms are only
shownforpolaritiesofSDcorrespondingtospecific
systems.
Table 4: Internal Strobe Conditions for DMA Mode
DSC[2:0] LOGIC EQUATION SYSTEM CONFIGURATION
000 i960Cx with internal DMA controller. SD is connected to
WAITN.
001 No specific system
010 General purpose DMA controller
011 i960Kx with external, bus master type DMA controller.
SD is connected to RDYN.
100 No specific system
101 No specific system
110 No specific system
111 No specific system
ACKN()& ACKNdelayed ()& SD)(
ACKN()& ACKNdelayed ()& SD()
ACKN()& SD()
ACKN()& SD()
ACKNdelayed ()& SDdelayed ()
ACKNdelayed ()& SDdelayed ()
ACKN()& ACKNdelayed ()
ACKN()& ACKNdelayed ()
ACKNdelayed ACKN delayed 1 clock=
SDdelayed SD delayed 1 clock=

PS3431-0500 Page 7 of 50
Advanced Hardware Architectures, Inc.
Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100
Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100
Figure 8: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
DD0 D1
CLOCK
ACKN
SD
DRIVEN
DD1D0
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3

Page 8 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Figure 9: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition
of DSC=100
Figure 10: DMA Mode Timing for Eight Word Burst Write, Zero Wait State, Strobe Condition
of DSC=100
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition
of DSC=100
CLOCK
ACKN
SD
DRIVEN
DD1D0 D2 D3
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7
CLOCK
ACKN
SD
DRIVEN
DD0 D2D1 D3 D4 D5 D6 D7

PS3431-0500 Page 9 of 50
Advanced Hardware Architectures, Inc.
3.3 PAD WORD HANDLING IN
BURST MODE
The StarLitecompression algorithm appends
a 15 bit End-of-Record codeword to terminate a
compression record. If a word containing an End-
of-Record comes out during a burst read, the words
following the End-of-Record are invalid (pad)
words. This prevents a burst read from crossing
record boundaries. The first word of the next burst
read is the first word of the next record. Any pad
words not previously removed must be deleted.
Two methods are available to delete pad words.
During decompression pad words may be deleted
by using the Decompression Pause on Record
Boundaries bit (DPOR), in the Decompression
Control register. After the part is paused, the DI
FIFO mustbe reset byasserting theDIRSTbit inthe
Port Control register. Decompressor must also be
reset by asserting DDR bit in Decompression
Control register. The COEOTN signal is asserted
when an End-of-Record is present on the output of
the CO FIFO and the compression record counter
has decremented to zero, thus indicating the end of
a transfer comprised of one or more compressed
records.
Another method to remove pad words during
compression is to read the Compressed Byte Count
register after pausing at an End-of-Record and
subtractthisfromthe system’s receivedwordcount.
This difference is the number of pad words that
must be removed from the end of the compressed
record.
The COEORN signal is asserted when an End-
of-Record is present on the output of the CO FIFO.
COEORN is deasserted after the transfer. In some
systems COEORN can be used to generate a DMA-
done condition if conditioned with the
acknowledge.
3.4 DMA REQUEST SIGNALS
AND STATUS
AHA3431 requests data using request pins
(CIREQN, DIREQN, COREQN, DOREQN). The
requests are controlled by programmable FIFO
thresholds. Both input and output FIFOs have
programmable empty and full thresholds set in the
Input FIFO Threshold and Output FIFO Threshold
registers. By requesting only when a FIFO can
sustain a certain burst size, the bus is used more
efficiently.
Operationoftheserequestsignalsshouldnot be
confusedwiththerequestsignalsonthevideoports.
CIREQN or DIREQN active indicates space
available in the particular input FIFO, and
COREQN or DOREQN active indicates data is
available in the particular output FIFO. These
request signals inactive does not prevent data
transfers. The data transfers are controlled solely
with the particular acknowledge signal being active.
The input requests, CIREQN and DIREQN,
operate under the following prioritized rules, listed
in order of highest to lowest:
1) If the FIFO reset in the Port Control
register is active, the request is inactive.
2) If a FIFO overflow interrupt is active, the
request is inactive.
3) If the FIFO is at or below the empty
threshold, the request remains active.
4) If the FIFO is at or above the full threshold,
the request stays inactive.
The output requests, COREQN and DOREQN,
operate under the following prioritized rules, listed
in order of highest to lowest:
1) If the FIFO reset in the Port Control
register is active, the request is inactive.
2) If the output FIFO underflow interrupt is
active, the request is inactive.
3) If an EOR is present inthe outputFIFO, the
request goes active.
4) If the output FIFO is at or above the full
threshold, the request goes active.
5) If an EOR is read (strobed) out ofthe FIFO,
the request goes inactive during the same
clock asthe strobe (if ERC=0), otherwise it
goes inactive on the next clock.
6) If the output FIFO is at or below the empty
threshold, the request goes inactive.
3.4.1 FIFO THRESHOLDS
For maximum efficiency, the FIFO thresholds
should be set in such a way that the compressor
seldom runs out of data from the CI FIFO or
completely fills the output FIFO. The FIFOs are 16
words deep.
For example, in a system with fixed 8-word
bursts, good values for the thresholds are:
IET=3, IFT=4, OFT=D, OET=C
Setting the input full threshold to one higher
than the input empty threshold simply guarantees
that the request deasserts as soon as possible. The
latency between a word being strobed in and the
request changing due to a FIFO threshold condition
is 3 clocks. This should be kept in mind when
programmingthresholdvalues.RefertoSection4.0
of AHA Application Note (ANDC16), Designer’s
Guide for StarLiteTM Family Products for a more
thorough discussion of FIFO thresholds. The
following figure shows an example of an input
FIFO crossing its full threshold.

Page 10 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Figure 12: FIFO Threshold Example (IFT=4, DSC=2, 1 Word Already in FIFO)
Note: CIREQN deasserted when threshold counter exceeds IFT=4, but additional words are reading as long as
ACKN is asserted.
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010
3.4.2 REQUEST DURING AN END-OF-RECORD
The request deasserts at an EOR in one of two
ways. If ERC bit in System Configuration 1 is zero,
the request deasserts asynchronously during the
clock where the EOR is strobed out of the FIFO.
ThisleadstoalongoutputdelayforREQN,butmay
be necessary in some systems. For DSC values of 4
or 5, the request deasserts the first clock after the
acknowledge pulse for the EOR. If ERC is set to
one, then the request deasserts synchronously the
clock after the EOR is strobed out. The minimum
low time on the request in this case is one clock.
The request delay varies between the different
strobe conditions. See Section 8.0 AC Electrical
Specifications for further details.
3.4.3 REQUEST STATUS BITS
An external microprocessor can also read the
valueofeachrequestusingtheCIREQandCOREQ
bits in the Compression Port Status register and the
DIREQ and DOREQ bits in the Decompression
Port Status register. Please note the request status
bits are active high while the pins are active low.
CLOCK
D
CIACKN
CIREQN
Threshold
12345
678
12345678
9
Counter
EOR-2
CLOCK
D
ACKN
REQN
EOR-1 EOR
(ERC=0)
EORN
REQN
(ERC=1)

PS3431-0500 Page 11 of 50
Advanced Hardware Architectures, Inc.
3.5 DATA FORMAT
The width of the D bus is selected with the
WIDE bit in System Configuration 0. If WIDE=1,
then D is a 32-bit bus. If WIDE=0, D is a 16-bit bus.
If the bus is configured to be 16-bits wide
(WIDE=0), all data transfers occur on D[15:0] and
the upper 16 bits of the bus, D[31:16], should be
terminated with Pullup resistors. If WIDE=0, the
FIFO is sixteen words deep.
Since the compression algorithm is byte
oriented, it is necessary for AHA3431 to know the
ordering of the bytes within the word. The COMP
and DECOMP BIG bits in System Configuration 0
select between big endian and little endian byte
ordering for the compression and decompression
channel. Little endian stores the first byte in the
lower eight bits of a word (D[7:0]). Big endian
stores the first byte in the uppermost eight bits of a
word (D[31:24] for WIDE=1, D[15:8] for WIDE=0)
for the decompression engine or compression
engine.
REVERSE BYTE in the System Configuration
0register allows the bit order into the compression
engine to be swapped. This control is useful for
reversing a page of data for duplex printing
applications and has no significant impact on
compression ratio performance.
3.6 ODD BYTE HANDLING
All data transfers to or from either the
compression or decompression engines are
performed on the D bus on word boundaries. Since
no provision is made for single byte transfers,
occasionally words will contain pad bytes.
Following is a description of when these pad bytes
are necessary for each of the data interfaces.
3.6.1 COMPRESSION INPUT AND PAD BYTES
Uncompressed data input into AHA3431 is
treated as records. The length of these records is
fixed by the value in the Record Length or RLEN
register. This register contains the number of
uncompressed bytes in each record. If the value in
RLEN is not an integer multiple of number of bytes
per word as selected by WIDE, the final word in the
transfer of the record contains pad bytes. The
compressionenginesimplydiscardsthesepadbytes
and has no effect on either the dictionary or the
output data stream. The next record must begin on a
word boundary.
The minimum value for RLEN is 4 bytes.
3.6.2 COMPRESSION OUTPUT AND
PAD BYTES
Ifarecordendson abyteotherthanthelastbyte
inaword,thefinalwordcontains1,2 or3padbytes.
The pad bytes have a value of 0x00. This applies to
the 32-bit data port only.
3.6.3 DECOMPRESSION INPUT, PAD BYTES
AND ERROR CHECKING
This port recognizes the end of a record by the
appearance of a special End-of-Record sequence in
the data stream. Once this is seen, the remaining
bytes in the current word are treated as pad bytes
and discarded. The word following the end of the
record is the beginning of the next record.
When operating in decompression mode, the
Decompression Record Length (DRLEN) register
canbeusedtoprovideerrorchecking.Theexpected
length of the decompressed record is programmed
into the DRLEN register. The decompressor then
counts down from the value in DRLEN to zero.
A DERR interrupt is issued if an EOR is not
read out of the decompressor when the counter
expires or if an EOR occurs before the counter
expires(i.e., when the record lengths do not match).
If the DERR interrupt is masked,use of theDRLEN
register is optional.
When operating in pass-through mode, there is
no End-of-Record codeword for the decompressor
to see. In pass-through mode, the user must set the
record length in the DRLEN register.
3.6.4 DECOMPRESSION OUTPUT AND
PAD BYTES
When the decompressor detects an End-of-
Record codeword, it will add enough pad bytes of
value 0x00 to complete the current word as defined
by the WIDE bit in the System Configuration 0
register. For example, if a record ends on a byte
other than the last byte in a word, the final word
contains 1, 2 or 3 pad bytes. This applies to the 32-
bit data port only, not the VOD port. The VOD port
never outputs pad bytes since it is 8-bits wide.

Page 12 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Figure 14: Timing Diagram, Video Input
3.7 VIDEO INTERFACES
3.7.1 VIDEO INPUT
The video input port is enabled by the VDIE bit
inthe SystemConfiguration1register.Theportuses
VIREQNtoindicatethattheportcanacceptanother
byte. The value on VID[7:0] is written into
AHA3431 each clock that VIREQN and VIACKN
are both low.
ThevideoinputportassertsVIREQNwhenever
there isroom in the CI FIFO. The values in IET and
IFT are all ignored. The compression input FIFO is
16bytesdeepinthismode.The videoinputportcan
transfer up to one byte per clock (33 MB/sec). The
DMAinterfacecannotaccessthecompressioninput
FIFO when VDIE is set.
3.7.2 VIDEO OUTPUT
The video output port is enabled by the VDOE
bit in the System Configuration 1 register. The port
uses VOREQN to indicate that the byte on
VOD[7:0] is valid. An 8-bit word is read each clock
when both VOREQN and VOACKN are sampled
low on arising edge ofCLOCK. Padbytesat an end
of record are discarded by the video output port and
do not appear on VOD[7:0]. When the byte on
VOD[7:0] isthe last byte in a record, the VOEORN
signal goes low. To use VOEORN as an End-of-
Record indicator, it should be conditioned with
VOREQN and VOACKN. Unlike a DMA transfer,
there are no pad bytes after an End-of-Record.
VOEOTN operates similar to VOEORN. It
flags the end of an output transfer of one or more
decompressed records. VOEOTN is asserted when
the End-of-Record is at the output of the DO FIFO
and the decompression record count has
decremented to zero.
The port requests whenever a valid byte is
present on the output. The values in OET and OFT
are all ignored. The decompression output FIFO is
16 bytes deep in this mode. The video output port
can output up to one byte per clock. The DMA
interface cannot access the decompression output
FIFO when VDOE is set.
Figure 15: Timing Diagram, Video Output
CLOCK
VIREQN
VIACKN
VID[7:0] 0 3
don’t
care 1 2 don’t care 4 5 don’t care
CLOCK
VOREQN
VOACKN
VOD[7:0] 0 31 2 4 5
VOEORN,
VOEOTN

PS3431-0500 Page 13 of 50
Advanced Hardware Architectures, Inc.
3.8 ALGORITHM
AHA3431 compression is an efficient
implementation of an algorithm optimized for
bitonal images. For some comparison data refer to
theAHAApplicationNote(ANDC13),Compression
Performance: StarLiteTM: ENCODEB2 on
Bitonal Images. A software emulation of the
algorithm is available for evaluation.
3.9 COMPRESSION ENGINE
The compression engine supports either
compression or pass-through processes. The
compression engine is enabled with the COMP bit in
the Compression Control register. When the engine is
enabled, it takes data from the CIFIFO as it becomes
available.Thisdataiseithercompressedbytheengine
or passed through unaltered. This pass-through mode
is selected with the CPASS bit in the Compression
Control register. TheCPASSbitmayonlybechanged
when COMP is set to ‘0’. The contents of the
dictionary are preserved when COMP is changed.
However, when CPASS is changed, the contents are
lost.Consequently,thedevicecannotbechangedfrom
pass-throughmodetocompressionmodeorviceversa
without losing the contents of the dictionary.
The compressor can be instructed to halt at the
endofarecordoranendofmultiple-recordtransfer.
If the CPOR bit is set, the compressor stops taking
data out of the CI FIFO immediately after the last
byte of a record, and the COMP bit is cleared. If the
CPOT bitissetthecompressorhaltsattheendofthe
multiple-record transfer. The CEMP bit indicates
thecompressorhasemptiedalldata.Compressionis
restarted by setting the COMP bit.
The compression engine takes data from the
compression input FIFO at a maximum rate of 33
MBytes/sec. Two conditions cause the data rate to
drop below the maximum. The first is caused by the
compression input FIFO running empty ofdata to be
compressed. The second condition is caused by the
output FIFO filling. When this occurs, the engine
haltsandwaitsfortheFIFO.Whilehalted,theengine
goes into a low power standby mode. Refer to the
table in Section 7.1 for the extent of power savings.
The compression byte counter counts the number
of bytes output from the CO data port. The counter is
valid to read after a compression end of transfer
interrupt (CEOT), or pausing after End-of-Record.
3.10 DECOMPRESSION ENGINE
The decompression engine is enabled with the
DCOMP bit in the Decompression Control register.
When the engine is enabled, it takes data from the
DI FIFO as it becomes available. This data is either
decompressed by the engine or passed through
unaltered. Pass-through mode is selected with the
DPASS bit. DPASS may only be changed when
DCOMP is set to zero and DEMP is set to one. The
contents of the dictionary are preserved when
DCOMP is changed. However, when DPASS is
changed, the contents are lost. Consequently,
AHA3431 cannot be changed from pass-through
mode to decompression mode or vice versa without
losing the contents of the dictionary.
The decompressor can be instructed to halt at
the end of a record or an end of multiple-record
transfer. If the DPOR bit is set, the decompressor
stops taking data out of the DI FIFO immediately
after the last byte of a record, and the DCOMP bit is
cleared. If DPOT bit is set the decompressor halts at
the end of the multiple-record transfer. The DEMP
bit indicates the decompressor has emptied of all
data. Decompression is restarted by setting the
DCOMP bit.If DPOR or DPOT is set and data from
a second record enters the FIFO immediately after
the first record, bytes from the second record will
haveenteredthedecompressorpriortodecodingthe
EOR. An implication of this is that bytes from the
second record will remain in the decompressor and
preventDEMP fromsettingafterallofthedatafrom
the first record has left the decompressor. This
differsfromoperationofthecompressionengine.In
either mode, a DEOR interrupt is generated when
the last byteof a decompressed record isread out of
the chip, and DEOT when the last byte of a transfer
is read out of the chip.
The decompressor takes data from the
decompression input FIFO at the maximum clock
rate. AHA3431can maintainthis datarateaslong as
the decompression input FIFO is not empty or the
decompression output FIFO is not full.
Caveat:Changingthemodeforthedecompressor
between records or multiple-record transfers must be
done with the data of the following record or transfer
heldoffuntiltheDEORstatusbitistrueforthecurrent
recordandtheDecompression Control registershave
been reprogrammed. This reprogramming can occur
automatically with prearming.
3.11 PREARMING
Prearming is the ability to write certain registers
that apply to the next record while the device is
processing the current record. Prearming occurs
automatically at the end of a record. If a prearmable
register is written while the part is busy processing a
record,attheendoftherecordtheparttakesitsprogram
from the register value last written. Compression
Control and Decompression Control registers each
have separate corresponding prearm registers.

Page 14 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
The lower 3 bytes of both the Compression
Record Length and the Decompression Length
registers are prearmable. They may be changed and
the new values loaded into the respective counter at
the next End-of-Record. If the most significant byte
is written in either of the Record Length registers,
the counter is immediately reloaded with the new 4
byte value in the particular register.
3.12 INTERRUPTS
Nine conditions are reported in the Interrupt
Status/Control 1 and Status/Control 2 registers as
individual bits. All interrupts are maskable by
setting the corresponding bits in the Interrupt Mask
register. A one in the Interrupt Mask register means
thecorrespondingbitintheInterruptStatus/Control
register is masked and does not affect the interrupt
pin (INTRN). The INTRN pin is active whenever
any unmasked interrupt bit is set to a one.
An End-of-Record interrupt is posted when a
word containing an end-of-record is strobed out of
the compression or decompression output FIFO
(CEOR and DEOR respectively). A DEOR
interrupt is also reported if an end-of-record is read
from the video output port. A compression or
decompression end of transfer interrupt will also be
posted if this is the last record of a transfer.
End-of-Transfer interrupts are posted when an
EOR occurs that causes the counter to decrement to
zero. These are CEOT and DEOT, and they apply to
both the compression and decompression engines
respectively.
Four FIFO error conditions are also reported.
Overflowing the input FIFOs generates a CIOF or
DIOF interrupt. Anoverflow can only becleared by
resetting the respective FIFO via the Port Control
register.
Underflowing the output FIFOs (reading when
they are not ready) generates a COUF or DOUF.
Underflow interrupts are cleared by writing a one to
COUF or DOUF. In the event of an underflow, the
respective FIFO must be reset. Note that in systems
using fixed length bursts which rearbitrate during a
burst, the CO FIFO may request anotherburstwhen
the record actually finishes near the end of the
current burst. In this scenario a second burst takes
place causing a FIFO underflow. As longas a pause
onEnd-of-Recordisused,dataisnotcorrupted.The
FIFO simply must be reset.
3.13 DUPLEX PRINTING
Duplex Printing is the ability to print on both
sides of the page. AHA3431 supports this with
separate endian control for the Compressor and
Decompressor, and bit order control at the input to
the compressor. Bit order control allows reversal of
the data bits within each byte of data. For example,
reverse order means bit-7 is swapped with bit-0, bit-
6 is swapped with bit-1, etc.... During compression
operationofthebacksideofthe pagethedatawords
are sent to the AHA3431 device in reverse order.
The byte order is swapped if necessary by the
COMP BIG bit in the System Configuration 0
Register. The bit order within each byte is reversed
with the REVERSE BYTE bit in this same register.
Duringdecompressionofthisreversedpagethe
DECOMP BIG bit in this register must be
programmed to the same value used when this page
of data was compressed. Use of this feature has
virtually no effect on the compression ratio when
compared to compressing in forward order.
3.14 BLANK BANDS
Setting DBLANK in the Decompression
Control register causes the next record output from
the Decompressor to be comprised of a repeating 8-
bit pattern defined by the Pattern register.
DBLANK automatically clears at the end of the
next record. This command bit may be prearmed by
writing to the Decompression Control Prearm
register. When programming the device to generate
blank records the system must not send data to be
decompressed until the device has reached the end
of record for the blank record.
3.15 LOW POWER MODE
The AHA3431 is a data-driven system. When
nodatatransfersaretakingplace,onlytheclockand
on-chip RAMs including the FIFOs require power.
To reduce power consumption to its absolute
minimum, the user can stop the clock when it is
high. With the system clock stopped and at a high
level, the current consumption is due to leakage.
Control and Status registers are preserved in this
mode. Reinitialization of Control registers are not
necessary when switching from Low Power to
Normal operating mode.
3.16 TEST MODE
In order to facilitate board level testing, the
AHA3431providestheabilitytotristatealloutputs.
When the TEST0 pin is high, all outputs ofthe chip
aretristated.When TEST0islow,thechipreturnsto
normal operation.

PS3431-0500 Page 15 of 50
Advanced Hardware Architectures, Inc.
4.0 REGISTER DESCRIPTIONS
The microprocessor configures, controls and monitors IC operation through the use of the registers
defined in this section. The bits labeled “res”are reserved and must be set to zero when writing to registers
unless otherwise noted.
A summary of registers is listed below.
Table 5: Internal Registers
ADDRESS R/W DESCRIPTION FUNCTION DEFAULT AFTER
RSTN PREARM
0x00 R/W System Configuration 0 Big Endian vs. Little Endian,
32-bit vs. 16-bit, Reverse Byte Undefined No
0x01 R/W System Configuration 1 Data Strobe Condition, EOR Request Control, VDO Port
Enable, VDI Port Enable 0x00 No
0x02 R/W Input FIFO Thresholds Input FIFOs Empty
Threshold, Full Threshold Undefined No
0x03 R/W Output FIFO Thresholds Output FIFOs Empty
Threshold, Full Threshold Undefined No
0x04 R Compression Ports Status FIFO Status, Request Status,
EOR Status Undefined No
0x05 R Decompression Ports Status FIFO Status, Request Status,
EOR Status Undefined No
0x06 R/W Port Control Reset Individual FIFOs 0x0F No
0x07 R/W Interrupt Status/Control 1 EOR, Overflow, Underflow 0x00 No
0x09 R/W Interrupt Mask 1 Interrupt Mask bits 0xFF No
0x0A R Version Die Version Number 0x31 No
0x0C R/W Decompression Record
Length 0 Bytes Remaining, Byte 0 0xFF Yes
0x0D R/W Decompression Record
Length 1 Bytes Remaining, Byte 1 0xFF Yes
0x0E R/W Decompression Record
Length 2 Bytes Remaining, Byte 2 0xFF Yes
0x0F R/W Decompression Record
Length 3 Bytes Remaining, Byte 3 0xFF No
0x10 R/W Compression Record Length 0 LengthofUncompressedData
in Bytes, Byte 0 Undefined Yes
0x11 R/W Compression Record Length 1 " " , Byte 1 Undefined Yes
0x12 R/W Compression Record Length 2 " " , Byte 2 Undefined Yes
0x13 R/W Compression Record Length 3 " " , Byte 3 Undefined No
0x14 R/W Compression Control
Pause on Record Boundaries,
Enable Compression,
Compression Engine Empty
Status, Compression
Dictionary Reset, Select Pass-
Through Mode
0x04 Yes
0x15 R/W Compression Reserved Reserved 0x00 No
0x16 R/W Compression Line Length 0 Line Length Register Lower
8bits Undefined No
0x17 R/W Compression Line Length 1 Line Length Register Upper
3bits Undefined No