AHA StarLite AHA3431 User manual

PS3431-0500
2365 NE Hopkins Court
Pullman, WA 99163-5601
tel: [phone]
fax: [phone]
e-mail: [email protected]
www.aha.com
advancedhardwarearchitectures
Product Specification
AHA3431 StarLiteTM
40 MBytes/sec Simultaneous
Compressor/Decompressor IC, 3.3V

Advanced Hardware Architectures, Inc.
PS3431-0500 i
Table of Contents
1.0 Introduction . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. .1
1.1 Conventions, Notations and Definitions. . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . . .1
1.2 Features . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. .1
1.3 Functional Overview . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. .2
2.0 System Configuration . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .. . . . .3
2.1 Microprocessor Interface. . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . .3
3.0 Functional Description . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. .6
3.1 Data Ports . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . .6
3.2 DMA Mode. . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . . . . .. .6
3.3 Pad Word Handling in Burst Mode . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. .9
3.4 DMA Request Signals and Status. . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . .9
3.4.1 FIFO Thresholds. . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . .9
3.4.2 Request Duringan End-of-Record. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .10
3.4.3 Request StatusBits . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .10
3.5 Data Format. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .11
3.6 Odd Byte Handling . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .11
3.6.1 Compression Input and Pad Bytes. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .11
3.6.2 Compression Outputand Pad Bytes . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .11
3.6.3 DecompressionInput, PadBytes and Error Checking. . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .11
3.6.4 Decompression Outputand Pad Bytes . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .11
3.7 Video Interfaces.. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .12
3.7.1 Video Input. . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .12
3.7.2 Video Output. . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..12
3.8 Algorithm. . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .13
3.9 Compression Engine. . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..13
3.10 Decompression Engine. . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .13
3.11 Prearming . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .13
3.12 Interrupts. .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .14
3.13 DuplexPrinting . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .14
3.14 BlankBands . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . .14
3.15 Low Power Mode. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..14
3.16 Test Mode . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .14
4.0 Register Descriptions . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .. . . .15
4.1 System Configuration0, Address 0x00 - Read/Write . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .17
4.2 System Configuration1, Address 0x01 - Read/Write . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .17
4.3 Input FIFO Thresholds, Address 0x02 - Read/Write. . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .18
4.4 Output FIFO Thresholds, Address 0x03 - Read/Write. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .18
4.5 Compression Ports Status, Address 0x04 -Read Only. . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .18
4.6 DecompressionPorts Status, Address 0x05 - Read Only. . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .19
4.7 Port Control, Address 0x06 - Read/Write . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..20
4.8 Interrupt Status/Control 1, Address 0x07 - Read/Write. . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .20
4.9 Interrupt Mask 1, Address 0x09 - Read/Write. . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . .21
4.10 Version, Address 0x0A - Read Only . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . .21
4.11 Decompression Record Length, Address 0x0C, 0x0D, 0x0E, 0x0F - Read/Write. . . . . . .. . . . . . . .. . . . .22
4.12 Compression Record Length, Address 0x10, 0x11, 0x12, 0x13 - Read/Write . . . . .. . . . . . . .. . . . . . . ..22
4.13 Compression Control, Address 0x14 - Read/Write . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . ..23
4.14 Compression Reserved, Address 0x15 - Read/Write . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . .23
4.15 Compression Line Length, Address 0x16, 0x17 -Read/Write. . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .24
4.16 Decompression Control, Address 0x18 - Read/Write . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .24
4.17 Decompression Reserved, Address 0x1A- Read/Write . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .25

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4.18 Decompression Line Length,Address 0x1C, 0x1D - Read/Write . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .25
4.19 Compression Record Count, Address0x20, 0x21- Read/Write. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . .25
4.20 InterruptStatus/Control 2,Address 0x27- Read/Write. . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..25
4.21 InterruptMask 2, Address 0x29 - Read/Write. . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..26
4.22 Decompression Record Count, Address 0x2C, 0x2D - Read/Write . . . . . . . . . . . . .. . . . . . . .. . . . . . . . .26
4.23 Compression Byte Count, Address0x30, 0x31,0x32, 0x33 -Read/Write . . . . . . . .. . . . . . . .. . . . . . . . .26
4.24 Compression Control Prearm, Address 0x34 - Read/Write. . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .26
4.25 Pattern, Address 0x35 -Read/Write . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .27
4.26 Decompression Control Prearm, Address 0x38 - Read/Write. .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . .27
4.27 Decompression Reserved, Address 0x3A- Read/Write . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . .27
5.0 Signal Descriptions . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . .. . . . .27
5.1 Microprocessor Interface. . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .28
5.2 Data Interface . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..29
5.3 Video Interface . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..30
5.4 System Control . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .30
6.0 Pinout . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..31
7.0 DC Electrical Specifications . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .33
7.1 Operating Conditions. . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .33
7.2 Absolute Maximum Stress Ratings . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .33
8.0 AC Electrical Specifications . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .34
9.0 Package Specifications. . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .40
10.0 Ordering Information. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . ..41
10.1 AvailableParts. . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .41
10.2 Part Numbering. . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..41
11.0 Related Technical Publications . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .42
Appendix A:Additional Timing Diagrams for DMA Mode Transfers . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..43
Appendix B:Recommended Power Decoupling Capacitor Placement . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .50

Advanced Hardware Architectures, Inc.
PS3431-0500 iii
Figures
Figure 1: Functional Block Diagram . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. .2
Figure 2: Microprocessor PortWrite (PROCMODE[1:0]=“01”) . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . .4
Figure 3: Microprocessor PortRead (PROCMODE[1:0]=“01”). . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. .4
Figure 4: Microprocessor PortWrite (PROCMODE[1:0]=“11”) . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . .5
Figure 5: Microprocessor PortRead (PROCMODE[1:0]=“11”). . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. .5
Figure 6: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=100. . .. . . . . . . .. . . . . . . . . . . .. .7
Figure 7: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=100. . . . . . . . . . .. . . . . . . .. . . . . .7
Figure 8: DMA Mode Timing for Four WordBurst Write,One Wait State, Strobe Conditionof DSC=100. . . . . . . . .7
Figure 9: DMA Mode Timing for Four WordBurst Read, OneWait State,Strobe Condition of DSC=100. . . . . . .. .8
Figure 10: DMA Mode Timing for Eight Word Burst Write, ZeroWait State,Strobe Conditionof DSC=100 . . . . . . . .8
Figure 11: DMA Mode Timing for Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=100 . . . . . . . .8
Figure 12: FIFO ThresholdExample (IFT=4,DSC=2, 1 Word Already in FIFO). . . . . . . .. . . . . . . . . . . .. . . . . . . . .10
Figure 13: Request vs. End-of-Record, Strobe Condition of DSC=010 . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .10
Figure 14: Timing Diagram, VideoInput . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .12
Figure 15: Timing Diagram, VideoOutput. . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..12
Figure 16: Pinout. . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .32
Figure 17: Data InterfaceTiming. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..34
Figure 18: Request Deasserts at EOR, Strobe Conditionof DSC=0-3, 6-7;ERC=0 . . . . . . . . . . . .. . . . . . . .. . . . .34
Figure 19: Request Deasserts at EOR, Strobe Conditionof DSC=0-3, 6-7;ERC=1 . . . . . . . . . . . .. . . . . . . .. . . . .35
Figure 20: Request Deasserts at EOR, Strobe Conditionof DSC=4 or 5; ERC=0. . . . . . . . . .. . . . . . . . . . . .. . . . .35
Figure 21: Request Deasserts at EOR, Strobe Conditionof DSC=4 or 5; ERC=1. . . . . . . . . .. . . . . . . . . . . .. . . . .35
Figure 22: Output Enable Timing . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . ..36
Figure 23: Video Input Port Timing . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . .36
Figure 24: Video Output Port Timing. . . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..37
Figure 25: Microprocessor Interface Timing (PROCMODE[1]=0). . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .37
Figure 26: Microprocessor Interface Timing (PROCMODE[1]=1). . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .38
Figure 27: Interrupt Timing . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..39
Figure 28: Clock Timing . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .39
Figure 29: Power On Reset Timing. . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .39
Figure A1: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=000...............................................43
Figure A2: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=000...............................................43
Figure A3: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=000 ...............43
Figure A4: DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=000...............44
Figure A5: DMA Mode Timingfor Eight Word Burst Write, ZeroWait State, StrobeConditionof DSC=000..............44
Figure A6: DMA Mode Timingfor Eight Word Burst Read, Zero Wait State, Strobe Condition of DSC=000..............44
Figure A7: DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=010...............................................45
Figure A8: DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=010...............................................45
Figure A9: DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=010 ...............45
Figure A10:DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=010...............46
Figure A11:DMA Mode Timingfor Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=010..............46
Figure A12:DMA Mode Timing for Eight Word Burst Read,Zero Wait State, Strobe Condition of DSC=010..............46
Figure A13:DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=011...............................................47
Figure A14:DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=011...............................................47
Figure A15:DMA Mode Timing for Four Word Burst Write, One Wait State, Strobe Condition of DSC=011 ...............47
Figure A16:DMA Mode Timing for Four Word Burst Read, One Wait State, Strobe Condition of DSC=011...............48
Figure A17:DMA Mode Timingfor Eight Word Burst Write, Zero Wait State, Strobe Condition of DSC=011..............48
Figure A18:DMA Mode Timing for Eight Word Burst Read,Zero Wait State, Strobe Condition of DSC=011..............48
Figure A19:DMA Mode Timing for Single Word Writes, Strobe Condition of DSC=111...............................................49
Figure A20:DMA Mode Timing for Single Word Reads, Strobe Condition of DSC=111...............................................49

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Tables
Table 1: Data Bus and FIFO Sizes Supported by AHA3431 .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. .2
Table 2: AHA3431 Connection to Host Microprocessors. . . . . . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . .3
Table 3: Microprocessor PortConfiguration. .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . .4
Table 4: Internal StrobeConditions for DMA Mode. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. .6
Table 5: Internal Registers. . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . .15
Table 6: Data Port Timing Requirements. . . . . . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..34
Table 7: Request vs. EOR Timing . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .36
Table 8: Output Enable Timing Requirements. . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .36
Table 9: Video Input Port Timing Requirements . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . .36
Table 10: Video Output Port Timing Requirements. . . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . ..37
Table 11: Microprocessor Interface Timing Requirements . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . ..38
Table 12: Interrupt TimingRequirements.. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . .. . . . . . . . .39
Table 13: Clock Timing Requirements. . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . .. . . . . . . . . . . .. . . . . . . ..39
Table 14: Power On Reset Timing Requirements . .. . . . . . . . . . . .. . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . .. . . . .39

PS3431-0500 Page 1 of 50
Advanced Hardware Architectures, Inc.
1.0 INTRODUCTION
AHA3431 is a lossless compression
coprocessor IC for hardcopy systems on many
standard platforms. The device is targeted for high
throughput and high resolution hardcopy systems.
TheAHA3431isfunctionallybackwardcompatible
to the AHA3411.
Enhancements to this product over the
AHA3411 include improved I/O timings, higher
operating frequency and data rate, and lower power.
Blank band generation in real time and
prearming registers between records enable
advanced banding techniques. Bands may be in raw
uncompressed, compressed or blank format in the
frame buffer. The device processes all three formats
and outputs the raster data to the printer engine.
Appropriate registers are prearmed when switching
from one type to the next. Separate byte ordering
between the Compressor and the Decompressor
with bit order control into the compressor allow full
reversal of the image data for duplex printing
support.A system mayuse multiplerecordcounters
and End-of-Transfer interrupts to easily handle
pages partitioned into smaller records or bands.
This document contains functional description,
system configurations, register descriptions,
electrical characteristics and ordering information.
It is intended for system designers considering a
compression coprocessor in their embedded
applications.Softwaresimulationandananalysisof
the algorithm for printer and copier images of
various complexity are also available for
evaluation. A comprehensive Designer’s Guide
complements this document to assist with the
systemdesign.Section11.0 containsalistofrelated
technical publications.
1.1 CONVENTIONS, NOTATIONS AND
DEFINITIONS
–Active low signals have an “N”appended to the
end of the signal name. For example, CSN and
RDYN.
–A“bar”over asignal nameindicatesan inverseof
the signal. For example, SD indicates an inverse
of SD. This terminology is used only in logic
equations.
–“Signal assertion”means the output signal is
logically true.
–Hex values are represented with a prefix of “0x”,
such as Register “0x00”. Binary values do not
contain a prefix, for example, DSC=000.
–A range ofsignal names orregister bits is denoted
by a set of colons between the numbers. Most
significant bit is always shown first, followed by
least significant bit. For example, VOD[7:0]
indicates signal names VOD7 through VOD0.
–A logical “AND”function of two signals is
expressed with an “&”between variables.
–Mega Bytes per second is referred to as MBytes/
sec or MB/sec.
–In referencing microprocessors, an x, xx or xxx is
used as suffix to indicate more than one
processor. For example, Motorola 68xxx
processor family includes various 68000
processors from Motorola.
–Reserved bits in registers are referred as “res”.
–REQN or ACKN refer to eitherCI, DI, CO orDO
Request or Acknowledge signals, as applicable.
1.2 FEATURES
PERFORMANCE:
•40 MBytes/sec maximum sustained compression
and decompression rate
•160 MBytes/sec burst data rate over a 32-bit data
bus
•40 MBytes/sec synchronous 8-bit video in and
video out ports
•Maximum clock speeds up to 40 MHz
•Simultaneous compression and decompression at
full bandwidth
•Average 15 to 1 compression ratio for 1200 dpi
bitmap image data
•Advanced banding support: blank bands,
prearming
FLEXIBILITY:
•Big Endian or Little Endian; 32 or 16-bit bus
width and data bit/byte reordering for duplex
printing support
•Programmable Record Length, Record Count and
Scan Length Registers may be prearmed
•Scan line length up to 2K bytes
•Interfaces directly with various MIPS, Motorola
68xxx and Cold FIRE, and Intel i960 embedded
processors
•Pass-through mode passes raw data through
compression and decompression engines
•Counter checks errors in decompression
SYSTEM INTERFACE:
•Single chip compression/decompression solution
–no external SRAM required
•Four 16 ×32-bit FIFOs with programmable
threshold counters facilitate burst mode transfers
OTHERS:
•Low power modes
•Software emulation program available
•128 pin quad flat package
•3.3V operation
•Test pin tristates outputs
•Firmware, Register, Pinout and Functional
compatible with 5V, AHA3411

Page 2 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Figure 1: Functional Block Diagram
1.3 FUNCTIONAL OVERVIEW
The coprocessor device has three external high
speed synchronous data ports capable of
transferring once every clock cycle. These are a 32-
bit bidirectional data port,an 8-bit Video Input Data
(VID) port and a Video Output Data (VOD) port.
The 32-bit port is capable of transferring up to 4
bytes per clock. The VID and VOD are capable of
up to one byte per clock.
The device accepts uncompressed datathrough
the 8-bit VID port or the 32-bit data port into its
Compression In FIFO (CI FIFO). The 32-bit data
port may be configured for 16-bit transfers.
Compressed data is available through the 32-bit
data port via the Compressed Output FIFO (CO
FIFO). The sustained data rate through the
compression engine is one byte per clock.
Decompression data may be simultaneously
processed by the device. Decompression data is
accepted through the 32-bit data port, buffered in
the Decompression Input FIFO (DI FIFO) and
decompressed.Theoutputdataismadeavailableon
the 32-bit data port via the Decompression Output
FIFO (DO FIFO) or the 8-bit Video Output port.
The decompression engine is capable of processing
an uncompressed byte every clock.
The four FIFOs are organized as 16×32 each.
For data transfers through the three ports, the
“effective”FIFO sizes differ according to their data
bus widths. The table below shows the size of the
data port and the “effective”FIFO size for the
various configurations supported by the device.
Table 1: Data Bus and FIFO Sizes Supported by AHA3431
(From Scanner)
VIREQN
VID[7:0]
VIACKN
D[31:0]
DRIVEN
TEST CLK RSTN PROCMODE[1:0] PD[7:0]
PA[5:0]
CSN DIR RDYN INTRN
VOACKN
VOD[7:0]
VOREQN
VOEORN
VOEOTN
(To Printer)
COEORN
DOREQN COREQN DIREQN CIREQN SD DOACKN COACKN DIACKN CIACKN
VID
PORT
DATA
PORT
CI
FIFO
16x32
DI
FIFO
16x32
CLOCK
DATA PORT CONTROL
COMPRESSOR
DECOMPRESSOR
MICROPROCESSOR INTERFACE
CO
FIFO
16x32
DO
FIFO
16x32
VOD
PORT
AHA3431
StarLiteTM
8
8 8
888
32
32 32
6
8
COEOTN
OPERATION DATA BUS WIDTH PORT EFFECTIVE FIFO SIZE
Compression Data In 8 Video In 16 x 8
Compression Data In/Out 32 Data Port 16 x 32
Compression Data In/Out 16 Data Port 16 x 16
Decompression Data In/Out 32 Data Port 16 x 32
Decompression Data In/Out 16 Data Port 16 x 16
Decompressed Data Out 8 Video Out 16 x 8

PS3431-0500 Page 3 of 50
Advanced Hardware Architectures, Inc.
Table 2: AHA3431 Connection to Host Microprocessors
Movement of data for compression or
decompression is performed using synchronous
DMA over the 32-bit data port. The Video ports
support synchronous DMA mode transfers. The
DMA strobe conditions are configurable for the 32-
bit data port depending upon the system processor
and the available DMA controller.
Data transfer for compression or
decompression is synchronous over the three data
ports functioning as DMA masters. To initiate a
transfer into or out of the Video ports, the device
assertsVxREQN, the externaldevicerespondswith
VxACKN and begins to transfer data over the VID
or VOD busses on each succeeding rising edge of
the clock until VxREQN is deasserted. The 32-bit
port relies on the FIFO Threshold settings to
determine the transfer.
The sections below describe the various
configurations, programming and other special
considerations indeveloping a compression system
using AHA3431.
2.0 SYSTEM CONFIGURATION
This section provides information on
connecting AHA3431 to various microprocessors.
2.1 MICROPROCESSOR INTERFACE
The device is capable of interfacing directly to
various processors for embedded application. Table
2 and Table 3 show how AHA3431 should be
connected to various host microprocessors.
All register accesses to AHA3431 are
performed on the 8-bit PD bus. The PD bus is the
lowest byte of the 32-bit microprocessor bus.
During reads of the internal registers, the upper 24
bits are not driven. System designers should
terminate these lines with Pullup resistors.
AHA3431providesfourmodesofoperationfor
themicroprocessorport.Bothactivehighandactive
low write enable signals are allowed as well as two
modes for chip select. The mode of operation is set
by the PROCMODE[1:0] pins. The
PROCMODE[1] signal selects when CSN must be
active and also how long an access lasts.
When PROCMODE[1] is high, CSN
determines thelength ofthe access. CSN must be at
least 5 clocks in length. On a read, valid data is
driven onto PD[7:0] during the 5th clock. If CSN is
longer than 5 clocks, thenvalid data continuesto be
driven out onto PD[7:0]. When CSN goes inactive
(high), PD[7:0] goes tristate (asynchronously) and
RDYNisdrivenhighasynchronously.CSNmustbe
high forat leasttwo clocks. RDYN is always driven
(itisnottristatedwhenPROCMODE[1]ishigh).The
mode is typical of processors such as the Motorola
68xxx.
When PROCMODE[1] is low, accesses are
fixed at 5 clocks, PD[7:0] is only driven during the
fifth clock, and RDYN is driven high for the first 4
clocks and low during the fifth clock. RDYN is
tristated at all other times. Write data must be driven
the clock after CSN is sampled low. Accesses may
be back to back with no delays in between. This
mode istypical of RISC processors such as the i960.
PROCMODE[0] determines the polarity of the
DIR pin. If PROCMODE[0] is high, then the DIR
pinisanactivelowwriteenable.IfPROCMODE[0]
is low, then the DIR pin is an active high write
enable. Figure 2 through Figure 5 illustrate the
detailed timing diagrams for the microprocessor
interface.
For additional notes on interfacing to various
microprocessors, refer to AHA Application Note
(ANDC16),Designer’sGuideforStarLiteTM Family
Products. AHA Applications Engineering is
available to support with other processors not in the
Designer’s Guide.
PIN NAME i960Cx i960Kx IDT3081 Motorola
MCFS102(ColdFIRE)
PA A LAD Latched Address Latched Address
CSN CS CS System Dependent Decoded Chip Select
DIR W/R W/R WR R/W
PD D LAD A/D A/D[7:0]
SD WAIT READY System Dependent System Dependent
RDYN No Connect READY ACK TA
DRIVEN DEN System Dependent System Dependent System Dependent
CLOCK PCLK No Connect SYSCLK BCLOCK

Page 4 of 50 PS3431-0500
Advanced Hardware Architectures, Inc.
Table 3: Microprocessor Port Configuration
Figure 2: Microprocessor Port Write (PROCMODE[1:0]=“01”)
Figure 3: Microprocessor Port Read (PROCMODE[1:0]=“01”)
PROCMODE[1:0] DIR CYCLE LENGTH EXAMPLE PROCESSOR
00 Active high write fixed i960
01 Active low write fixed
10 Active high write variable
11 Active low write variable 68xxx, MIPS R3000
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0 D1
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
A2
D1

PS3431-0500 Page 5 of 50
Advanced Hardware Architectures, Inc.
Figure 4: Microprocessor Port Write (PROCMODE[1:0]=“11”)
Figure 5: Microprocessor Port Read (PROCMODE[1:0]=“11”)
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0
CLOCK
PA[5:0]
CSN
DIR
PD[7:0]
A0
RDYN
A1
D0