Epson S1C63454 User manual

MF1074-03
Technical Manual
CMOS 4-BIT SINGLE CHIP MICROCOMPUTER
S1C63454 Technical Hardware
S1C63454

NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any
liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or
circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such
as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there
is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright
infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic
products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
© SEIKO EPSON CORPORATION 2001, All rights reserved.

Revisions and Additions for this manual
Section
7.5 Page 103
111
Item
OSC1 crystal oscillation circuit
Appendix
Contents
The table was revised.
The Appendix was added.
Chapter
7
Appendix
S1C63454 Technical Manual

The information of the product number change
Configuration of product number
Devices
Comparison table between new and previous number
S1C63 Family processors
Starting April 1, 2001, the product number has been changed as listed below. Please use the new
product number when you place an order. For further information, please contact Epson sales
representative.
S1 C63158 F0A01
Packing specification
Specification
Package (D: die form; F: QFP)
Model number
Model name (C: microcomputer, digital products)
Product classification (S1: semiconductor)
Development tools
S5U1 C63000 A1 1
Packing specification
Version (1: Version 1 ∗2)
Tool type (A1: Assembler Package ∗1)
Corresponding model number
(63000: common to S1C63 Family)
Tool classification (C: microcomputer use)
Product classification
(S5U1: development tool for semiconductor products)
∗1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.)
∗2: Actual versions are not written in the manuals.
Previous No.
E0C63158
E0C63256
E0C63358
E0C63P366
E0C63404
E0C63406
E0C63408
E0C63F408
E0C63454
E0C63455
E0C63458
E0C63466
E0C63P466
New No.
S1C63158
S1C63256
S1C63358
S1C6P366
S1C63404
S1C63406
S1C63408
S1C6F408
S1C63454
S1C63455
S1C63458
S1C63466
S1C6P466
S1C63 Family peripheral products
Previous No.
E0C63467
E0C63557
E0C63558
E0C63567
E0C63F567
E0C63658
E0C63666
E0C63F666
E0C63A08
E0C63B07
E0C63B08
E0C63B58
New No.
S1C63467
S1C63557
S1C63558
S1C63567
S1C6F567
S1C63658
S1C63666
S1C6F666
S1C63A08
S1C63B07
S1C63B08
S1C63B58
Previous No.
E0C5250
E0C5251
New No.
S1C05250
S1C05251
Comparison table between new and previous number of development tools
Development tools for the S1C63 Family Development tools for the S1C63/88 Family
Previous No.
ADP63366
ADP63466
ASM63
GAM63001
ICE63
PRC63001
PRC63002
PRC63004
PRC63005
PRC63006
PRC63007
URS63366
New No.
S5U1C63366X
S5U1C63466X
S5U1C63000A
S5U1C63000G
S5U1C63000H1
S5U1C63001P
S5U1C63002P
S5U1C63004P
S5U1C63005P
S5U1C63006P
S5U1C63007P
S5U1C63366Y
Previous No.
ADS00002
GWH00002
URM00002
New No.
S5U1C88000X1
S5U1C88000W2
S5U1C88000W1
00
00

S1C63454 TECHNICAL MANUAL EPSON i
CONTENTS
CONTENTS
CHAPTER 1OUTLINE ________________________________________________ 1
1.1 Features.........................................................................................................1
1.2 Block Diagram ..............................................................................................2
1.3 Pin Layout Diagram .....................................................................................3
1.4 Pin Description .............................................................................................4
1.5 Mask Option.................................................................................................. 4
CHAPTER 2POWER SUPPLY AND INITIAL RESET ____________________________ 7
2.1 Power Supply ................................................................................................7
2.1.1 Voltage <VD1> for oscillation circuit and internal circuits ...................... 8
2.1.2 Voltage <VC1–VC5> for LCD driving ........................................................ 8
2.2 Initial Reset ...................................................................................................9
2.2.1 Reset terminal (RESET) ............................................................................. 9
2.2.2 Simultaneous low input to terminals K00–K03 ........................................ 10
2.2.3 Internal register at initial resetting........................................................... 10
2.2.4 Terminal settings at initial resetting ......................................................... 11
2.3 Test Terminal (TEST) ................................................................................... 11
CHAPTER 3 CPU, ROM, RAM________________________________________ 12
3.1 CPU..............................................................................................................12
3.2 Code ROM....................................................................................................12
3.3 RAM .............................................................................................................12
3.4 Data ROM ....................................................................................................13
CHAPTER 4PERIPHERAL CIRCUITS AND OPERATION__________________________ 14
4.1 Memory Map................................................................................................14
4.2 Watchdog Timer ........................................................................................... 19
4.2.1 Configuration of watchdog timer.............................................................. 19
4.2.2 Interrupt function ...................................................................................... 19
4.2.3 I/O memory of watchdog timer ................................................................. 20
4.2.4 Programming notes ................................................................................... 20
4.3 Oscillation Circuit ....................................................................................... 21
4.3.1 Configuration of oscillation circuit .......................................................... 21
4.3.2 OSC1 oscillation circuit............................................................................ 22
4.3.3 OSC3 oscillation circuit............................................................................ 23
4.3.4 Switching of operating voltage ................................................................. 24
4.3.5 Clock frequency and instruction execution time....................................... 24
4.3.6 I/O memory of oscillation circuit.............................................................. 25
4.3.7 Programming notes ................................................................................... 26
4.4 Input Ports (K00–K03) ................................................................................27
4.4.1 Configuration of input ports ..................................................................... 27
4.4.2 Interrupt function ...................................................................................... 27
4.4.3 Mask option ............................................................................................... 28
4.4.4 I/O memory of input ports......................................................................... 29
4.4.5 Programming notes ................................................................................... 30

ii EPSON S1C63454 TECHNICAL MANUAL
CONTENTS
4.5 Output Ports (R00–R03) .............................................................................. 31
4.5.1 Configuration of output ports ................................................................... 31
4.5.2 Mask option ............................................................................................... 31
4.5.3 High impedance control ............................................................................ 32
4.5.4 Special output ............................................................................................ 32
4.5.5 I/O memory of output ports....................................................................... 34
4.5.6 Programming notes ................................................................................... 35
4.6 I/O Ports (P00–P03 and P10–P13) .............................................................36
4.6.1 Configuration of I/O ports ........................................................................ 36
4.6.2 Mask option ............................................................................................... 37
4.6.3 I/O control registers and input/output mode ............................................ 37
4.6.4 Pull-up during input mode ........................................................................ 37
4.6.5 I/O memory of I/O ports............................................................................ 38
4.6.6 Programming note..................................................................................... 40
4.7 LCD Driver (COM0–COM16, SEG0–SEG39) ...........................................41
4.7.1 Configuration of LCD driver .................................................................... 41
4.7.2 Power supply for LCD driving.................................................................. 41
4.7.3 Mask option ............................................................................................... 42
4.7.4 LCD display control (ON/OFF) and switching of duty............................ 42
4.7.5 Display memory......................................................................................... 45
4.7.6 LCD contrast adjustment .......................................................................... 46
4.7.7 I/O memory of LCD driver........................................................................ 47
4.7.8 Programming notes ................................................................................... 49
4.8 Clock Timer .................................................................................................. 50
4.8.1 Configuration of clock timer ..................................................................... 50
4.8.2 Data reading and hold function ................................................................ 50
4.8.3 Interrupt function ...................................................................................... 51
4.8.4 I/O memory of clock timer ........................................................................ 52
4.8.5 Programming notes ................................................................................... 54
4.9 Stopwatch Timer...........................................................................................55
4.9.1 Configuration of stopwatch timer ............................................................. 55
4.9.2 Count-up pattern ....................................................................................... 55
4.9.3 Interrupt function ...................................................................................... 56
4.9.4 I/O memory of stopwatch timer ................................................................ 57
4.9.5 Programming notes ................................................................................... 58
4.10 Programmable Timer ...................................................................................59
4.10.1 Configuration of programmable timer.................................................... 59
4.10.2 Setting of initial value and counting down ............................................. 60
4.10.3 Setting of input clock in timer mode ....................................................... 61
4.10.4 Interrupt function .................................................................................... 61
4.10.5 Setting of TOUT output ........................................................................... 62
4.10.6 Transfer rate setting for serial interface ................................................ 63
4.10.7 I/O memory of programmable timer ....................................................... 64
4.10.8 Programming notes ................................................................................. 68
4.11 Serial Interface (SIN, SOUT, SCLK, SRDY)................................................69
4.11.1 Configuration of serial interface ............................................................ 69
4.11.2 Mask option ............................................................................................. 70
4.11.3 Master mode and slave mode of serial interface.................................... 70
4.11.4 Data input/output and interrupt function ............................................... 71
4.11.5 I/O memory of serial interface................................................................ 74
4.11.6 Programming notes ................................................................................. 77

S1C63454 TECHNICAL MANUAL EPSON iii
CONTENTS
4.12 Sound Generator.......................................................................................... 78
4.12.1 Configuration of sound generator .......................................................... 78
4.12.2 Mask option ............................................................................................. 78
4.12.3 Control of buzzer output.......................................................................... 79
4.12.4 Setting of buzzer frequency and sound level........................................... 79
4.12.5 Digital envelope ...................................................................................... 80
4.12.6 One-shot output ....................................................................................... 81
4.12.7 I/O memory of sound generator .............................................................. 82
4.12.8 Programming notes ................................................................................. 84
4.13 Interrupt and HALT .....................................................................................85
4.13.1 Interrupt factor........................................................................................ 87
4.13.2 Interrupt mask ......................................................................................... 88
4.13.3 Interrupt vector ....................................................................................... 88
4.13.4 I/O memory of interrupt .......................................................................... 89
4.13.5 Programming notes ................................................................................. 90
CHAPTER 5SUMMARY OF NOTES _______________________________________ 91
5.1 Notes for Low Current Consumption........................................................... 91
5.2 Summary of Notes by Function.................................................................... 92
5.3 Notes on Mounting.......................................................................................96
CHAPTER 6BASIC EXTERNAL WIRING DIAGRAM ____________________________ 98
CHAPTER 7ELECTRICAL CHARACTERISTICS ________________________________ 99
7.1 Absolute Maximum Rating........................................................................... 99
7.2 Recommended Operating Conditions.......................................................... 99
7.3 DC Characteristics .....................................................................................100
7.4 Analog Circuit Characteristics and Power Current Consumption ............101
7.5 Oscillation Characteristics......................................................................... 103
7.6 Serial Interface AC Characteristics ...........................................................105
7.7 Timing Chart ...............................................................................................106
CHAPTER 8PACKAGE _______________________________________________ 107
8.1 Plastic Package ...........................................................................................107
8.2 Ceramic Package for Test Samples............................................................. 108
CHAPTER 9PAD LAYOUT ____________________________________________ 109
9.1 Diagram of Pad Layout...............................................................................109
9.2 Pad Coordinates.......................................................................................... 110
APPENDIX S5U1C63000P MANUAL
(PERIPHERAL CIRCUIT BOARD FOR S1C63404/454/455/458/466/P466)__ 111
A.1 Names and Functions of Each Part ............................................................111
A.2 Connecting to the Target System ................................................................114
A.3 Usage Precautions ...................................................................................... 116
A.3.1 Operational precautions .......................................................................... 116
A.3.2 Differences with the actual IC ................................................................. 116

S1C63454 TECHNICAL MANUAL EPSON 1
CHAPTER 1: OUTLINE
CHAPTER 1OUTLINE
The S1C63454 is a microcomputer which has a high-performance 4-bit CPU S1C63000 as the core
CPU, ROM (4,096 words ×13 bits), RAM (1,024 words ×4 bits), serial interface, watchdog timer, program-
mable timer, time base counters (2 systems), a dot-matrix LCD driver that can drive a maximum 40
segments ×17 commons and sound generator built-in. The S1C63454 features high speed operation and
low current consumption in a wide operating voltage range (2.2 V to 6.4 V), this makes it suitable for
applications working with batteries. It is also suitable for portable MD players.
1.1 Features
OSC1 oscillation circuit ...................... 32.768 kHz (Typ.) crystal or 60 kHz (Typ.) CR oscillation circuit (∗1)
OSC3 oscillation circuit ...................... 1.8 MHz (Typ.) CR or 4 MHz (Max.) ceramic oscillation circuit (∗1)
Instruction set ..................................... Basic instruction: 46 types (411 instructions with all)
Addressing mode: 8 types
Instruction execution time ................... During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec
During operation at 60 kHz: 33 µsec 67 µsec 100 µsec
During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec
ROM capacity ..................................... Code ROM: 4,096 words ×13 bits
Data ROM: 2,048 words ×4 bits (= 8K bits)
RAM capacity...................................... Data memory: 1,024 words ×4 bits
Display memory: 680 bits (160 words ×4 bits + 40 ×1 bit)
Input port............................................. 4 bits (Pull-up resistors may be supplemented ∗1)
Output port .......................................... 4 bits (It is possible to switch the 2 bits to special output ∗2)
I/O port ................................................ 8 bits (It is possible to switch the 4 bits to serial I/F input/
output ∗2)
Serial interface .................................... 1 port (8-bit clock synchronous system)
LCD driver ........................................... 40 segments ×8, 16 or 17 commons (∗2)
Time base counter .............................. 2 systems (Clock timer, stopwatch timer)
Programmable timer ........................... Built-in, 2 inputs ×8 bits
Watchdog timer ................................... Built-in
Sound generator ................................. With envelope and 1-shot output functions
External interrupt ................................ Input port interrupt: 1 system
Internal interrupt ................................. Clock timer interrupt: 4 systems
Stopwatch timer interrupt: 2 systems
Programmable timer interrupt: 2 systems
Serial interface interrupt: 1 system
Power supply voltage .......................... 2.2 V to 6.4 V
(Min. 1.8 V when the OSC3 oscillation circuit is not used)
Operating temperature range ............. -20°C to 70°C
Current consumption (Typ.) ................ Single clock (OSC1: Crystal oscillation):
During HALT (32 kHz)
3.0 V (LCD power OFF) 1 µA
3.0 V (LCD power ON, VC1 standard) 6 µA
3.0 V (LCD power ON, VC2 standard) 4 µA
During operation (32 kHz)
3.0 V (LCD power ON, VC1 standard) 10 µA
Twin clock:
During operation (4 MHz)
3.0 V (LCD power ON, VC1 standard) 1,000 µA
Package .............................................. QFP15-100pin (plastic) or chip
∗1: Can be selected with mask option ∗2: Can be selected with software

2EPSON S1C63454 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.2 Block Diagram
OSC1
OSC2
OSC3
OSC4
COM0–16
SEG0–39
VDD
VC1–5
CA–CF
VD1
VSS
VREF
BZ
K00–K03
TEST
RESET
P00–P03
P10–P13
R00–R03
Core CPU S1C63000
ROM
4,096 words ×13 bits
System Reset
Control
Interrupt
Generator
OSC
RAM
1,024 words ×4 bits
Data ROM
2,048 words ×4 bits
LCD Driver
40 SEG ×17 COM
Power
Controller
Sound
Generator
Stopwatch
Timer
Clock
Timer
Programmable
Timer
Serial Interface
Input Port
I/O Port
Output Port
Fig. 1.2.1 Block diagram

S1C63454 TECHNICAL MANUAL EPSON 3
CHAPTER 1: OUTLINE
1.3 Pin Layout Diagram
Fig. 1.3.1 Pin layout diagram
5175
26
50
INDEX
251
100
76
S1C63454
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
No.
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
BZ
V
SS
OSC1
OSC2
V
D1
OSC3
OSC4
Name
V
DD
N.C.
N.C.
RESET
TEST
V
REF
R03
R02
R01
R00
P13
P12
P11
P10
P03
P02
P01
P00
K03
K02
K01
K00
N.C.
N.C.
N.C.
Name
V
C1
V C2
V C3
V C4
V C5
CF
CE
CD
CC
CB
CA
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
SEG39
SEG38
SEG37
SEG36
SEG35
Name
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
N.C. : No Connection

4EPSON S1C63454 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
1.4 Pin Description
Table 1.4.1 Pin description
Pin name
VDD
VSS
VD1
VC1–VC5
VREF
CA–CF
OSC1
OSC2
OSC3
OSC4
K00–K03
P00–P03
P10–P13
R00
R01
R02
R03
COM0–COM16
SEG0–SEG39
BZ
RESET
TEST
Pin No.
26
20
23
51–55
31
61–56
21
22
24
25
47–44
43–40
39–36
35
34
33
32
18–11, 62–70
10–1, 100–71
19
29
30
Function
Power (+) supply pin
Power (–) supply pin
Oscillation/internal logic system regulated voltage output pin
LCD system power supply pin
1/4 bias generated internally, 1/5 bias supplied externally
(selected by mask option)
LCD system power supply testing pin
LCD system boosting/reducing capacitor connecting pin
Crystal or CR oscillation input pin
(selected by mask option)
Crystal or CR oscillation output pin
(selected by mask option)
Ceramic or CR oscillation input pin
(selected by mask option)
Ceramic or CR oscillation output pin
(selected by mask option)
Input port
I/O port
I/O port
(switching to serial I/F input/output is possible by software)
Output port
Output port
Output port
(switching to TOUT signal output is possible by software)
Output port
(switching to FOUT signal output is possible by software)
LCD common output pin
(1/8, 1/16, 1/17 duty can be selected by software)
LCD segment output pin
Sound output pin
Initial reset input pin
Testing input pin
In/Out
–
–
–
–
O
–
I
O
I
O
I
I/O
I/O
O
O
O
O
O
O
O
I
I
1.5 Mask Option
Mask options shown below are provided for the S1C63454. Several hardware specifications are prepared
in each mask option, and one of them can be selected according to the application. The function option
generator winfog, that has been prepared as the development software tool of S1C63454, is used for this
selection. Mask pattern of the IC is finally generated based on the data created by the winfog. Refer to the
"S5U1C63000A Manual" for the winfog.
<Functions selectable with S1C63454 mask options>
(1) External reset by simultaneous LOW input to the input port (K00–K03)
This function resets the IC when several keys are pressed simultaneously. The mask option is used to
select whether this function is used or not. Further when the function is used, a combination of the
input ports (K00–K03), which are connected to the keys to be pressed simultaneously, can be selected.
Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.

S1C63454 TECHNICAL MANUAL EPSON 5
CHAPTER 1: OUTLINE
(2) Time authorize circuit for the simultaneous LOW input reset function
When using the external reset function (shown in 1 above), using the time authorize circuit or not can
be selected by the mask option. The reset function works only when the input time of simultaneous
LOW is more than the rule time if the time authorize circuit is being used.
Refer to Section 2.2.2, "Simultaneous low input to terminals K00–K03", for details.
(3) Input port pull-up resistor
The mask option is used to select whether the pull-up resistor is supplemented to the input ports or
not. It is possible to select for each bit of the input ports.
Refer to Section 4.4.3, "Mask option", for details.
(4) Output specification of the output port
Either complementary output or N-channel open drain output can be selected as the output specifica-
tion for the output ports R00–R03. The selection is done in 1-bit units.
Refer to Section 4.5.2, "Mask option", for details.
(5) Input specification / output specification / pull-up resistor of the I/O ports
For the output specification when the I/O ports (P00–P03, P10–P13) are in the output mode, either
complementary output or N-channel open drain output can be selected.
Further, whether or not the pull-up resistors working in the input mode are supplemented can be
selected. The selection is done in 4-bit units (P00–P03 and P10–P13).
When using the I/O port P10–P13 as the serial interface input/output terminals, the input specifica-
tion for the terminals that are used for the serial interface input can be selected from either "normal
input" or "with Schmitt trigger input". This option is applied to the serial interface input terminals,
and is fixed at "normal input" when the terminals are used for the I/O port P10–P13.
Refer to Section 4.6.2, "Mask option", for details.
(6) LCD drive bias
Either the internal power supply (1/4 bias) or an external power supply (1/5 bias) can be selected as
the LCD system power supply.
Refer to Section 4.7.3, "Mask option", for details.
(7) Synchronous clock polarity in the serial interface
The polarity of the synchronous clock SCLK and the SRDY signal in slave mode of the serial interface
is selected by the mask option. Either positive polarity or negative polarity can be selected.
Refer to Section 4.11.2, "Mask option", for details.
(8) Buzzer output specification of the sound generator
It is possible to select the polarity of the buzzer signal output from the BZ terminal. Select either
positive polarity or negative polarity according to the external drive transistor to be used.
Refer to Section 4.12.2, "Mask option", for details.
(9) OSC1 oscillation circuit
Either crystal oscillation circuit or CR oscillation circuit can be selected as the OSC1 oscillation circuit.
Refer to Section 4.3.2, "OSC1 oscillation circuit", for details.
(10)OSC3 oscillation circuit
Either CR oscillation circuit or ceramic oscillation circuit can be selected as the OSC3 oscillation circuit.
Refer to Section 4.3.3, "OSC3 oscillation circuit", for details.

6EPSON S1C63454 TECHNICAL MANUAL
CHAPTER 1: OUTLINE
<Mask option list>
The following is the option list for the S1C63454. Multiple selections are available in each option item as
indicated in the option list. Refer to Chapter 4, "Peripheral Circuits and Operation", to select the specifica-
tions that meet the application system. Be sure to select the specifications for unused functions too,
according to the instruction provided. Use winfog in the S5U1C63000A package for this selection. Refer to
the "S5U1C63000A Manual" for details.
1. OSC1 SYSTEM CLOCK
■■1. Crystal (32.768 kHz)
■■2. CR (60 kHz)
2. OSC3 SYSTEM CLOCK
■■1. Use <Ceramic (4 MHz)>
■■2. Use <CR (1.8 MHz)>
3. MULTIPLE KEY ENTRY RESET COMBINATION
■■1. Not Use
■■2. Use <K00, K01, K02, K03>
■■3. Use <K00, K01, K02>
■■4. Use <K00, K01>
4. MULTIPLE KEY ENTRY RESETTIME AUTHORIZE
■■1. Not Use
■■2. Use
5. INPUT PORT PULL UP RESISTOR
• K00 ...... ■■1. With Resistor ■■2. Gate Direct
• K01 ...... ■■1. With Resistor ■■2. Gate Direct
• K02 ...... ■■1. With Resistor ■■2. Gate Direct
• K03 ...... ■■1. With Resistor ■■2. Gate Direct
6. OUTPUT PORT OUTPUT SPECIFICATION
• R00....... ■■1. Complementary ■■2. Nch-OpenDrain
• R01....... ■■1. Complementary ■■2. Nch-OpenDrain
• R02....... ■■1. Complementary ■■2. Nch-OpenDrain
• R03....... ■■1. Complementary ■■2. Nch-OpenDrain
7. I/O PORT OUTPUT SPECIFICATION
• P0x ....... ■■1. Complementary ■■2. Nch-OpenDrain
• P1x ....... ■■1. Complementary ■■2. Nch-OpenDrain
8. I/O PORT PULL UP RESISTOR
• P0x ....... ■■1. With Resistor ■■2. Gate Direct
• P1x ....... ■■1. With Resistor ■■2. Gate Direct
9. I/O PORT INPUT SPECIFICATION
■■1. Normal CMOS Input
■■2. Schmitt Trigger Input
10. LCD DRIVING POWER
■■1. Internal
■■2. External
11. SERIAL PORT INTERFACE POLARITY
■■1. Positive
■■2. Negative
12. SOUND GENERATOR POLARITY FOR OUTPUT
■■1. Positive
■■2. Negative

S1C63454 TECHNICAL MANUAL EPSON 7
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
CHAPTER 2POWER SUPPLY AND INITIAL RESET
2.1 Power Supply
The S1C63454 operating power voltage is as follows:
Table 2.1.1 Operating power voltage
OSC1 oscillation circuit
Crystal oscillation
Crystal oscillation
CR oscillation
OSC3 oscillation circuit
Not use
Use
–
Operating power voltage
1.8 V–6.4 V
2.2 V–6.4 V
2.2 V–6.4 V
The S1C63454 operates by applying a single power supply within the above range between VDD and VSS.
The S1C63454 itself generates the voltage necessary for all the internal circuits by the built-in power
supply circuits shown in Table 2.1.2.
Table 2.1.2 Power supply circuits
Circuit
Oscillation and internal circuits
LCD driver
Power supply circuit
Oscillation system voltage regulator
LCD system voltage circuit
Output voltage
V
D1
V C1 –V C5
Note: • Do not drive external loads with the output voltage from the internal power supply circuits.
•V
C3 should be used only when the LCD drive voltage is supplied externally (1/5 bias); when
using the internal LCD system voltage circuit (1/4 bias), short between VC3 and VC2 terminals.
•See Chapter 7, "Electrical Characteristics", for voltage values and drive capability.
External
power
supply
Internal
circuits
Oscillation
circuit
LCD system
voltage circuit
Oscillation system
voltage regulator
V DD
V
V
C5
V
OSC1–4
COM0–16
SEG0–39
D1
D1
V
V
V
V
V
CA
CB
CC
CD
CE
CF
C1
C2
C3
C4
C5
LCD driver
V SS
+
V – C1
Fig. 2.1.1 Configuration of power supply

8EPSON S1C63454 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.1.1Voltage <VD1> for oscillation circuit and internal circuits
VD1 is a voltage for the oscillation circuit and the internal logic circuits, and is generated by the oscillation
system voltage regulator for stabilizing the oscillation.
The S1C63454 is designed with twin clock specification; it has two types of oscillation circuits OSC1 and
OSC3 built-in. Use OSC1 clock for normal operation, and switch it to OSC3 by the software when high-
speed operation is necessary. When switching the clock, the operating voltage VD1 must be switched by
the software to stabilize the operation of the oscillation circuit and internal circuits.
The oscillation system voltage regulator can output the following two types of VD1 voltage. It should be
set at the value according to the oscillation circuit and oscillation frequency by the software.
Single clock operation (OSC1 crystal oscillation): VD1 = 1.3 V
Single clock operation (OSC1 CR oscillation): VD1 = 2.2 V
Twin clock operation (OSC3, 4 MHz): VD1 = 2.2 V
Refer to Section 4.3, "Oscillation Circuit", for the VD1 switching procedure.
However, since the VD1 voltage value is fixed at 2.2 V when the CR oscillation circuit has been selected as
the OSC1 oscillation circuit by mask option, it is not necessary to switch VD1 by software.
2.1.2Voltage <VC1–VC5> for LCD driving
VC1–VC5 are the LCD drive voltages for which either the voltage generated by the LCD system voltage
circuit or voltage to be supplied from outside can be used. The built-in LCD system voltage circuit
generates four voltages (1/4 bias) VC1, VC2, VC4 and VC5 (excluding VC3). These four output voltages can
only be supplied to the externally expanded LCD driver.
When external voltages are supplied, 1/5 bias driving can be done by inputting drive voltage to the VC1–
VC5 terminals (including VC3).
Either the internal generated voltages or external voltages used for the LCD drive voltage can be selected
by a mask option.
The LCD system voltage circuit generates VC1 or VC2 with the voltage regulator built-in, and generates
three other voltages by boosting or reducing the voltage of VC1 or VC2. Table 2.1.2.1 shows the VC1, VC2,
VC4 and VC5 voltage values and boost/reduce status.
Table 2.1.2.1 LCD drive voltage when generated internally
LCD drive voltage
V C1 (0.975–1.2 V)
V C2 (1.950–2.4 V)
V
C4 (2.925–3.6 V)
V C5 (3.900–4.8 V)
V
DD = 1.8–6.4 V
V C1 (standard)
2 ×V C1
3 ×V C1
4 ×V C1
V DD = 2.6–6.4 V
1/2 ×V C2
V C2 (standard)
3/2 ×V
C2
2 ×V C2
Note: The LCD drive voltage can be adjusted by the software (see Section 4.7.6). Values in the above
table are typical values.
Either the VC1 or VC2 used for the standard is selected according to the supply voltage by the software.
The VC2 standard improves the display quality and reduces current consumption, however, the power
supply voltage VDD must be 2.6 V or more.
Refer to Section 4.7, "LCD Driver", for control of the LCD drive voltage.

S1C63454 TECHNICAL MANUAL EPSON 9
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2 Initial Reset
To initialize the S1C63454 circuits, initial reset must be executed. There are two ways of doing this.
(1) External initial reset by the RESET terminal
(2) External initial reset by simultaneous low input to terminals K00–K03 (mask option setting)
The circuits are initialized by either (1) or (2). When the power is turned on, be sure to initialize using the
reset function. It is not guaranteed that the circuits are initialized by only turning the power on.
Figure 2.2.1 shows the configuration of the initial reset circuit.
RESET
K00
K01
K02
K03
OSC2
OSC1
RQ
S
Internal
initial
reset
Divider
V DD
1 Hz
2 Hz
V DD
OSC1
oscillation
circuit
Noise
reject
circuit
Time
authorize
circuit
Mask option
Mask option
Fig. 2.2.1 Configuration of initial reset circuit
2.2.1 Reset terminal (RESET)
Initial reset can be executed externally by setting the reset terminal to a low level (VSS). After that the
initial reset is released by setting the reset terminal to a high level (VDD) and the CPU starts operation.
The reset input signal is maintained by the RS latch and becomes the internal initial reset signal. The RS
latch is designed to be released by a 2 Hz signal (high) that is divided by the OSC1 clock. Therefore in
normal operation, a maximum of 250 msec (when fOSC1 = 32.768 kHz) is needed until the internal initial
reset is released after the reset terminal goes to high level. Be sure to maintain a reset input of 0.1 msec or
more.
However, when turning the power on, the reset terminal should be set at a low level as in the timing
shown in Figure 2.2.1.1.
V DD
RESET
2.0 msec or more
1.8 (2.2) V
0.5•V
DD
0.1•V DD or less (low level)
Power on
Fig. 2.2.1.1 Initial reset at power on
The reset terminal should be set to 0.1•VDD or less (low level) until the supply voltage becomes 1.8 V or
more (until the supply voltage becomes 2.2 V or more when the CR oscillation circuit has been selected as
the OSC1 oscillation circuit by mask option).
After that, a level of 0.5•VDD or less should be maintained more than 2.0 msec.

10 EPSON S1C63454 TECHNICAL MANUAL
CHAPTER 2: POWER SUPPLY AND INITIAL RESET
2.2.2 Simultaneous low input to terminals K00–K03
Another way of executing initial reset externally is to input a low signal simultaneously to the input ports
(K00–K03) selected with the mask option.
Since this initial reset passes through the noise reject circuit, maintain the specified input port terminals at
low level for at least 1.5 msec (when the oscillation frequency fOSC1 is 32.768 kHz) during normal opera-
tion. The noise reject circuit does not operate immediately after turning the power on until the oscillation
circuit starts oscillating. Therefore, maintain the specified input port terminals at low level for at least 1.5
msec (when the oscillation frequency fOSC1 is 32.768 kHz) after oscillation starts.
Table 2.2.2.1 shows the combinations of input ports (K00–K03) that can be selected with the mask option.
Table 2.2.2.1 Combinations of input ports
Not use
K00∗K01∗K02∗K03
K00∗K01∗K02
K00∗K01
1
2
3
4
When, for instance, mask option 2 (K00∗K01∗K02∗K03) is selected, initial reset is executed when the
signals input to the four ports K00–K03 are all low at the same time. When 3 or 4 is selected, the initial
reset is done when a key entry including a combination of selected input ports is made.
Further, the time authorize circuit can be selected with the mask option. The time authorize circuit checks
the input time of the simultaneous low input and performs initial reset if that time is the defined time (1
to 2 sec) or more.
If using this function, make sure that the specified ports do not go low at the same time during ordinary
operation.
2.2.3 Internal register at initial resetting
Initial reset initializes the CPU as shown in Table 2.2.3.1.
The registers and flags which are not initialized by initial reset should be initialized in the program if
necessary.
In particular, the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including
NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software.
When data is written to the EXT register, the E flag is set and the following instruction will be executed in
the extended addressing mode. If an instruction which does not permit extended operation is used as the
following instruction, the operation is not guaranteed. Therefore, do not write data to the EXT register for
initialization only.
Refer to the "S1C63000 Core CPU Manual" for extended addressing and usable instructions.