AKM AK4588 User manual

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 1 -
GENERAL DESCRIPTION
The AK4588 is a single chip CODEC that includes two channels of ADC and eight channels of DAC. The
ADC outputs 24bit data and the DAC accepts up to 24bit input data. TheADC hasthe Enhanced Dual Bit
architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit
architecture, and achieves wider dynamic range and lower outband noise. The AK4588 has a dynamic
range of 102dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car
audio. The AK4588 also has the balance volume control corresponding to the Dolby Digital (AC-3)
system.
The also has digital audio receiver (DIR) and transmitter (DIT) compatible with 192kHz, 24bits. The DIR
has 8-channel input selector and can automatically detect a Non-PCM bit stream. The AK4588 provides
a fully compatibility of hardware and software with the AK4628 and the AK4114.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
ADC/DAC part
2ch 24bit ADC
- 64x Oversampling
- Sampling Rate up to 96kHz
- Linear Phase Digital Anti-Alias Filter
- Single-Ended Input
- S/(N+D): 92dB
- Dynamic Range, S/N: 102dB
- Digital HPF for offset cancellation
- Overflow flag
8ch 24bit DAC
- 128x Oversampling
- Sampling Rate up to 192kHz
- 24bit 8 times Digital Filter
- Single-Ended Outputs
- On-chip Switched-Capacitor Filter
- S/(N+D): 90dB
- Dynamic Range, S/N: 106dB
- Individual channel digital volume with 128 levels and 0.5dB step
- Soft mute
- Zero Detect Function
High Jitter Tolerance
Extenal Master Clock Input:
- 256fs, 384fs, 512fs (fs=32kHz ∼48kHz)
- 128fs, 192fs, 256fs (fs=64kHz ∼96kHz)
- 128fs (fs=120kHz ∼192kHz)
2/8-Channel Audio CODEC with DI
R
AK4588
= Preliminary =

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 2 -
DIR/DIT Part
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
Low jitter Analog PLL
PLL Lock Range : 32kHz to 192kHz
Clock Source: PLL or X'tal
8-channel Receiver input
2-channel Transmission output (Through output or DIT)
Auxiliary digital input
De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
Detection Functions
-Non-PCM Bit Stream Detection
-DTS-CD Bit Stream Detection
- Sampling Frequency Detection
(32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz)
- Unlock & Parity Error Detection
-Validity Flag Detection
Up to 24bit Audio Data Format
Audio I/F: Master or Slave Mode
40-bit Channel Status Buffer
Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream
Q-subcode Buffer for CD bit stream
Serial µP I/F
Two Master Clock Outputs: 64fs/128fs/256fs/512fs
TTL Level Digital I/F
4-wire Serial and I2C Bus µP I/F for mode setting
Operating Voltage: 4.5 to 5.5V with 5V tolerance
80pin LQFP Package

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 3 -
Block Diagram
In
p
ut
Selector
Clock
Recovery Clock
Generator
DAIF
Decoder
A
C-3/MPEG
Detect
DEM
µP I/F
A
udio
I/F
X'tal
Oscillator
PDN
INT0
LRCK2
BICK2
SDTO2
DAUX2
MCKO2
XTOXTI
RPVDDPVSS
CDTI
CDTO
CCLK
CSN
DVDD
DVSS
TVDD
MCKO1
I2C
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
DIT
TX0
Error &
Detect
STATUS
INT1
Q-subcode
buffe
r
TX1
B,C,U,
VOUT
8 to 3
VIN
Audio
I/F
LPF
LPF
LPF
LPF
LPF
LPF
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
DAC DATT
DEM
ADC HPF
ADC HPF
RIN
LIN
LRCK1
BICK1
SDTI1
SDTI2
SDTI3
DAUX1
MCLK
LRCK
BICK
SDOUT
SDIN1
SDIN2
SDIN3
MCLK
SDTO1
Format
Converter
SDTI4
SDIN4
LPF
LPF
LOUT4
ROUT4
DAC DATT
DEM
DAC DATT
DEM
DAC DATT
DEM
DAC DATT
DEM
DAC DATT
DEM
DAC DATT
DEM
DAC DATT
DEM
A
VDD
A
VSS

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 4 -
Ordering Guide
AK4588VQ -10 ∼+70°C 80pinLQFP(0.5mmpitch)
AKD4588 Evaluation Board for AK4588
Pin Layout
(Top View)
CCLK/SCL
CDTI/SDA
CSN
DAUX1
SDTI4 SDTI3 SDTI2 SDTI1
XTL1 XTL0
PDN
MASTER
DZF2 DZF1
LOUT4
NC
ROUT4
NC
LOUT3
NC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
INT1
BOUT
TVDD
DVDD
DVSS
XTO
XTI
TEST3
MCKO2
MCKO1
COUT
UOUT
VOUT
SDTO2
BICK2
LRCK2
SDTO1
BICK1
LRCK1
CDTO
TEST1
RX1
NC
RX0
AVSS
AVDD
VREFH
VCOM
RIN
LIN
NC
ROUT1
NC
LOUT1
NC
ROUT2
NC
LOUT2
NC
ROUT3
INT0 TX1 TX0 MCLK VIN DAUX2 I2C RX7 CAD1 RX6 CAD0 RX5 TEST2 RX4 PVDD R PVSS RX3 NC RX2

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 5 -
Compatibility with AK4628 + AK4114
Functions AK4628+ AK4114 AK4588
Parallel control mode Yes No
TDM0, DFS0, DZFE, SDOS,
SMUTE pins Available Not available
4 wire serial
(I2C=”L”) AK4628: Set by CAD1/0 pins
AK4114: Fixed to “00”
ADC/DAC part: Set byCAD1/0 pins
DIR/DIT part: Fixed to “00”
Chip
address(*)
I2C Bus
(I2C=”H”) AK4628: Set by CAD1/0 pins
AK4114: Set by CAD1/0 pins
ADC/DAC part: Set byCAD1/0 pins
DIR/DIT part: Fixed to “00”
(*) The AK4588 has two register maps including ADC/DAC part (compatible with the AK4588) and DIR/DIT part
(compatible with AK4114). Each register is selected by Chip Address.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 6 -
PIN/FUNCTION
No. Pin Name I/O Function
1 INT1 O Interrupt 1 Pin
2 BOUT O
Block-Start Output Pin for Receiver Input
“H” during first 40 flames.
3 TVDD - Output Buffer Power Supply Pin, 2.7V∼5.5V
4 DVDD - Digital Power Supply Pin, 3.3V
5 DVSS - Digital Ground Pin
6 XTO O X'tal Output Pin
7 XTI I X'tal Input Pin
8 TEST3 I Test 3 Pin
This pin should be connected to DVSS.
9 MCKO2 O Master Clock Output 2 Pin
10 MCKO1 O Master Clock Output 1 Pin
11 COUT O C-bit Output Pin for Receiver Input
12 UOUT O U-bit Output Pin for Receiver Input
13 VOUT O V-bit Output Pin for Receiver Input
14 SDTO2 O Audio Serial Data Output Pin (DIR/DIT part)
15 BICK2 I/O Audio Serial Data Clock Pin (DIR/DIT part)
16 LRCK2 I/O Channel Clock Pin (DIR/DIT part)
17 SDTO1 O Audio Serial Data Output Pin (ADC/DAC part)
18 BICK1 I/O Audio Serial Data Clock Pin (ADC/DAC part)
19 LRCK1 I/O Input Channel Clock Pin
20 CDTO O Control Data Output Pin in Serial Mode, I2C= “L”.
CCLK I Control Data Clock Pin in Serial Mode, I2C= “L”
21 SCL I Control Data Clock Pin in Serial Mode, I2C= “H”
CDTI I Control Data Input Pin in Serial Mode, I2C= “L”.
22 SDA I/O Control Data Pin in Serial Mode, I2C= “H”.
I Chip Select Pin in Serial Mode, I2C=”L”.
23 CSN I This pin should be connected to DVSS, I2C=”H”.
24 DAUX1 I AUX Audio Serial Data Input Pin (ADC/DAC part)
25 SDTI4 I DAC4 Audio Serial Data Input Pin
26 SDTI3 I DAC3 Audio Serial Data Input Pin
27 SDTI2 I DAC2 Audio Serial Data Input Pin
28 SDTI1 I DAC1 Audio Serial Data Input Pin
29 XTL1 I X’tal Frequency Select 0 Pin
30 XTL0 I X’tal Frequency Select 1 Pin

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 7 -
No. Pin Name I/O Function
31 PDN I Power-Down Mode Pin When “L”, the AK4588 is powered-down, all output pin goes “L”, all registers are
reset. When CAD1/0 pins are changed, the AK4588 should be reset by PDN pin.
32 MASTER I Master Mode Select Pin
“H”: Master mode, “L”: Slave mode
DZF2 O
ZeroInputDetect2Pin (Note1)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN bit is “0”, this pin
goes to “H”. It always is in “L” when P/S is “H”.
33
OVF O
Analog Input Overflow Detect Pin (Note 2)
This pin goes to “H” if the analog input of Lch or Rch overflows.
34 DZF1 O
ZeroInputDetect1Pin (Note1)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input
data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN bit is “0”, this pin
goes to “H”. Output is selected by setting DZFE pin when P/S is “H”.
35 LOUT4 O DAC4 Lch Analog Output Pin
36 NC - No Connect
No internal bonding.
37 ROUT4 O DAC4 Rch Analog Output Pin
38 NC - No Connect
No internal bonding.
39 LOUT3 O DAC3 Lch Analog Output Pin
40 NC - No Connect
No internal bonding.
41 ROUT3 O DAC3 Rch Analog Output Pin
42 NC - No Connect
No internal bonding.
43 LOUT2 O DAC2 Lch Analog Output Pin
44 NC - No Connect
No internal bonding.
45 ROUT2 O DAC2 Rch Analog Output Pin
46 NC - No Connect
No internal bonding.
47 LOUT1 O DAC1 Lch Analog Output Pin
48 NC - No Connect
No internal bonding.
49 ROUT1 O DAC1 Rch Analog Output Pin
50 NC - No Connect
No internal bonding.
51 LIN I Lch Analog Input Pin
52 RIN I Rch Analog Input Pin
53 VCOM - Common Voltage Output Pin
2.2µF capacitor should be connected to PVSS externally.
54 VREFH - Positive Voltage Reference Input Pin, AVDD
Notes:
1. The group 1 and 2 can be selected by DZFM2-0 bits.
2. This pin becomes OVFE bit if OVFE bit is set to 1.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 8 -
No. Pin Name I/O Function
55 AVDD - Analog Power Supply Pin, 4.5V∼5.5V
56 AVSS - Analog Ground Pin, 0V
57 RX0 I Receiver Channel 0 Pin (Internal biased pin)
This channel is default in serial mode.
58 NC - No Connect
This pin should be connected to PVSS.
59 RX1 I Receiver Channel 1 Pin (Internal biased pin)
60 TEST1 I Test 1 Pin
This pin should be connected to PVSS.
61 RX2 I Receiver Channel 2 Pin (Internal biased pin)
62 NC - No Connect
This pin should be connected to PVSS.
63 RX3 I Receiver Channel 3 Pin (Internal biased pin)
64 PVSS - PLL Ground pin
65 R - External Resistor Pin
12kΩ+/-1% resistor should be connected to PVSS externally.
66 PVDD - PLLPower supply pin, 5.0V
67 RX4 I Receiver Channel 4 Pin (Internal biased pin)
68 TEST2 I Test 2 Pin
This pin should be connected to PVSS.
69 RX5 I Receiver Channel 5 Pin (Internal biased pin)
70 CAD0 I Chip Address 0 Pin (ADC/DAC part)
71 RX6 I Receiver Channel 6 Pin (Internal biased pin)
72 CAD1 I Chip Address 1 Pin (ADC/DAC part)
73 RX7 I Receiver Channel 7 Pin (Internal biased pin)
74 I2C I Control Mode Select Pin.
“L”: 4-wire Serial, “H”: I2C Bus
75 DAUX2 I Auxiliary Audio Data Input Pin (DIR/DIT part)
76 VIN I V-bit Input Pin for Transmitter Output
77 MCLK I Master Clock Input Pin
78 TX0 O Transmit Channel (Through Data) Output 0 Pin
79 TX1 O Transmit Channel Output1 pin When TX bit = “0”, Transmit Channel (Through Data) Output 1 Pin.
When TX bit = “1”, Transmit Channel (DAUX2 Data) Output Pin (Default).
80 INT0 O Interrupt 0 Pin
Notes:
3. All input pins except internal biased pins and internal pull-down pin should not be left floating.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 9 -
BSOLUTE MAXIMUM RATINGS
(AVSS, DVSS, PVSS=0V; Note 4)
Parameter Symbol min max Units
Power Supplies Analog
Digital
PLL
Output buffer
|AVSS-DVSS| (Note 5)
|AVSS-PVSS| (Note 5)
AVDD
DVDD
PVDD
TVDD
∆GND1
∆GND2
-0.3
-0.3
-0.3
-0.3
-
-
6.0
6.0
6.0
6.0
0.3
0.3
V
V
V
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Analog Input Voltage
(LIN, RIN pins) VINA -0.3 AVDD+0.3 V
Digital Input Voltage
Except LRCK1-2, BICK1-2, RX0-7, CAD0-1,
TEST1-2 pins VIND1 -0.3 DVDD+0.3 V
LRCK1-2, BICK1-2 pins VIND2 -0.3 TVDD+0.3 V
RX0-7, CAD0-1, TEST1-2 VIND3 -0.3 PVDD+0.3 V
Ambient Temperature (power applied) Ta -10 70 °C
Storage Temperature Tstg -65 150 °C
Notes:
4. All voltages with respect to ground.
5.AVSS, DVSS and PVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normaloperationisnotguaranteedattheseextremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS, PVSS=0V; Note 6)
Parameter Symbol min typ max Units
Power Supplies
(Note 6) Analog Digital
PLL
Output buffer
AVDD
DVDD
PVDD
TVDD
4.5
4.5
4.5
2.7
5.0
5.0
5.0
5.0
5.5
AVDD
AVDD
DVDD
V
V
V
V
Notes:
6. All voltages with respect to ground.
7. The power up sequence between AVDD, DVDD, PVDD and TVDD is not critical. To save leak current in power
down mode, AVDD, DVDD, PVDD become the same voltage as much as possible.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 10 -
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs;
Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz;
20Hz~40kHz at fs=192kHz, unless otherwise specified)
Parameter min typ max Units
ADC Analog Input Characteristics
Resolution 24 Bits
S/(N+D) (-0.5dBFS) fs=48kHz
fs=96kHz 84 - 92 86 dB dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
96
102
dB dB
dB
S/N (Note8) fs=48kHz,A-weighted
fs=96kHz
fs=96kHz, A-weighted
94
88
93
102
96
102
dB dB
dB
Interchannel Isolation 90 110 DB
DC Accuracy
Interchannel Gain Mismatch 0.2 0.3 dB
Gain Drift 20 - ppm/°C
Input Voltage AIN=0.62xVREFH 2.90 3.10 3.30 Vpp
Input Resistance fs=48kHz
fs=96kHz 15 TBD 25 16 kΩ
kΩ
PowerSupplyRejection (Note9) 50 dB
DAC Analog Output Characteristics
Resolution 24 Bits
S/(N+D) fs=48kHz
fs=96kHz
fs=192kHz
80
78
-
90
88
TBD
dB dB
dB
DR (-60dBFS) fs=48kHz, A-weighted
fs=96kHz, A-weighted
fs=192kHz, A-weighted
95
94
-
106
106
TBD
dB
dB
dB
S/N (Note 10) fs=48kHz, A-weighted
fs=96kHz, A-weighted
fs=192kHz, A-weighted
95
94
-
106
106
TBD
dB
dB
dB
Interchannel Isolation 90 110 dB
DC Accuracy
Interchannel Gain Mismatch 0.2 0.5 dB
Gain Drift 20 -
ppm/°C
Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp
Load Resistance 5
kΩ
PowerSupplyRejection (Note9) 50 dB
Power Supplies
Power Supply Current
NormalOperation (PDN=“H”) (Note11)
AVDD fs=48kHz
fs=96kHz
PVDD
DVDD+TVDD fs=48kHz (Note 12)
fs=96kHz
fs=192kHz
Power-downmode(PDN=“L”) (Note13)
TBD
TBD
TBD
TBD
TBD
TBD
80
mA
mA
mA
mA
mA
mA
µA

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 11 -
Notes:
8. S/N measured by CCIR-ARM is 96dB(@fs=48kHz).
9. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage.
10. S/N measured by CCIR-ARM is 102dB(@fs=48kHz).
11. CL=20pF, X'tal=24.576MHz, CM1-0= “10”, OCKS= “10”.
12. TVDD=3mA(typ).
13. In the power-down mode. RX inputs are open and all digital input pins including clock pins (MCLK, BICK,
LRCK) are held DVSS.
FILTER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz)
Parameter Symbol min typ max Units
ADC Digital Filter (Decimation LPF):
Passband (Note15) ±0.1dB
-0.2dB
-3.0dB
PB 0
-
-
20.0
23.0
18.9
-
-
kHz
kHz
kHz
Stopband SB 29.4 kHz
Passband Ripple PR ±0.04 dB
Stopband Attenuation SA 65 dB
GroupDelay (Note15) GD 19.1 1/fs
Group Delay Distortion ∆GD 0 µs
ADC Digital Filter (HPF):
Frequency Response (Note 14) -3dB
-0.1dB FR 1.0 6.5 Hz Hz
DAC Digital Filter:
Passband (Note15) -0.1dB
-6.0dB PB 0 - 24.0 21.8 - kHz kHz
Stopband SB 26.2 kHz
Passband Ripple PR ±0.02 dB
Stopband Attenuation SA 54 dB
GroupDelay (Note15) GD 19.2 1/fs
DAC Digital Filter + Analog Filter:
Frequency Response: 0 ∼20.0kHz
40.0kHz (Note 16)
80.0kHz (Note 16)
FR
FR
FR
±0.2
±0.3
±1.0
dB
dB
dB
Notes:
14. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs. The reference frequency of these responses is 1kHz.
15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal
to setting the 24bit data of both channels to the output register for ADC.
For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog
signal.
16. 40kHz; fs=96kHz, 80kHz; fs=192kHz

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 12 -
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage (Except XTI pin)
(XTIpin)
Low-Level Input Voltage (Except XTI pin)
(XTIpin)
VIH
VIH
VIL
VIL
2.2
70%DVDD
-
-
-
-
-
-
-
-
0.8
30%DVDD
V
V
V
V
Input Voltage at AC Coupling (XTI pin) (Note17) VAC 40%DVDD - - Vpp
High-Level Output Voltage
(Except TX0-1, DZF pins : Iout=-400µA)
(TX0-1pin: Iout=-400µA)
(DZFpin: Iout=-400µA)
Low-Level Output Voltage (Iout=400µA)
VOH
VOH
VOH
VOL
TVDD-0.4
DVDD-0.4
AVDD-0.4
-
-
-
-
-
-
-
-
0.4
V
V
V
V
TX Output Voltage Levels (Figure 25) VOH 0.4 0.5 0.6 V
Input Leakage Current Iin - - ±10 µA
Notes:
17. In case of connecting capacitance to XTI pin (refer to Figure 4).
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V; TVDD=2.7~5.5V)
Parameter Symbol min typ max Units
Input Resistance Zin 10 kΩ
Input Voltage (internally biased at PVDD/2) VTH 200 mVpp
Input Hysteresis VHY - 50 mV
Input Sample Frequency fs 32 - 192 kHz

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 13 -
SWITCHING CHARACTERISTICS (ADC/DAC part)
(Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Master Clock
256fsn, 128fsd:
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd:
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
8.192
27
27
12.288
20
20
16.384
15
15
12.288
18.432
24.576
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
LRCK1 Timing (Slave Mode)
TDM0= “0”, TDM1= “0”
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
kHz
kHz
%
TDM0= “1”, TDM1= “0”
LRCK1 frequency
“H” time
“L” time
fsd
tLRH
tLRL
32
1/256fs
1/256fs
48 kHz
ns
ns
TDM0= “1”, TDM1= “1”
LRCK1 frequency
“H” time
“L” time
fsd
tLRH
tLRL
64
1/128fs
1/128fs
96 kHz
ns
ns
LRCK1 Timing (Master Mode)
TDM0= “0”, TDM1= “0”
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
120
50
48
96
192
kHz
kHz
kHz
%
TDM0= “1”, TDM1= “0”
LRCK1 frequency
“H”time (Note18)
fsn
tLRH
32
1/8fs
48 kHz
ns
TDM0= “1”, TDM1= “1”
LRCK1 frequency
“H”time (Note18)
fsd
tLRH
64
1/4fs
96 kHz
ns
Power-down & Reset Timing
PDNPulseWidth (Note19)
PDN “↑” to SDTO1 valid (Note 20)
tPD
tPDV
150
522
ns
1/fs
Notes:
18. “L” time at I2S format.
19. The AK4588 can be reset by bringing PDN “L” to “H” upon power-up.
20. These cycles are the number of LRCK rising from PDN rising.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 14 -
Parameter Symbol min typ max Units
Audio Interface Timing (Slave Mode)
TDM0= “0” , TDM1= “0”
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑” (Note 21)
BICK1 “↑” to LRCK1 Edge (Note 21)
LRCK1 to SDTO1(MSB)
BICK1 “↓” to SDTO1
SDTI1-4,DAUX1 Hold Time
SDTI1-4,DAUX1 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
32
20
20
20
20
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM0= “1” , TDM1= “1”
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑” (Note 21)
BICK1 “↑” to LRCK1 Edge (Note 21)
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDM0= “1” , TDM1= “1”
BICK1 Period
BICK1 Pulse Width Low
Pulse Width High
LRCK1 Edge to BICK1 “↑” (Note 21)
BICK1 “↑” to LRCK1 Edge (Note 21)
BICK1 “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
32
20
20
10
10
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Audio Interface Timing (Master Mode)
TDM0= “0” , TDM1= “0”
BICK1 Frequency
BICK1 Duty
BICK1 “↓” to LRCK1 Edge
BICK1“↓” to SDTO1
SDTI1-4,DAUX1 Hold Time
SDTI1-4,DAUX1 setup Time
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
-20
20
20
64fs
50
20
40
Hz
%
ns
ns
ns
ns
TDM0= “1”, TDM1= “0”
BICK1 Frequency
BICK1Duty (Note22)
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1 Hold Time
SDTI1 Setup Time
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
-12
10
10
256fs
50
12
20
Hz
%
ns
ns
ns
ns
TDM0= “1”, TDM1= “1”
BICK1 Frequency
BICK1Duty (Note23)
BICK1 “↓” to LRCK1 Edge
BICK1 “↓” to SDTO1
SDTI1-2 Hold Time
SDTI1-2 Setup Time
fBCK
dBCK
tMBLR
tBSD
tSDH
tSDS
-12
10
10
128fs
50
12
20
Hz
%
ns
ns
ns
ns
Notes:
21. BICK rising edge must not occur at the same time as LRCK edge.
22. When MCLK is 512fs dBCK is guaranteed. When 384fs and 256fs, dBCK can not be guaranteed.
23. When MCLK is 256fs dBCK is guaranteed. When 128fs, dBCK can not be guaranteed.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 15 -
Timing Diagram(ADC/DAC part) 1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fsn, 1/fsd
LRCK1 VIH
VIL
tBCK
tBCKL
VIH
tBCKH
BICK1 VIL
Clock Timing (TDM0 = “0”)
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
1/fs
LRCK1 VIH
VIL
tLRLtLRH
tBCK
tBCKL
VIH
tBCKH
BICK1 VIL
Clock Timing (TDM0 = “1”)

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 16 -
tLRB
LRCK1
VIH
BICK1 VIL
tLRS
SDTO1 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI VIH
VIL
tSDH
Audio Interface Timing (TDM0 = “0”)
tLRB
LRCK1
VIH
BICK1 VIL
SDTO1 50%TVDD
tBSD
VIH
VIL
tBLR
tSDS
SDTI VIH
VIL
tSDH
Audio Interface Timing (TDM0 = “1”)

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 17 -
LRCK1
BICK1
SDTO1
tBSD
tMBLR
50%DVDD
50%DVDD
50%DVDD
DAUX1
tDXHtDXS
VIH
VIL
Audio Interface timing (Master Mode)

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 18 -
SWITCHING CHARACTERISTICS (DIR/DIT part)
(Ta=25°C; DVDD, AVDD4.5~5.5V, TVDD=2.7~5.5V; CL=20pF)
Parameter Symbol min typ max Units
Master Clock Timing
Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz
External Clock Frequency
Duty fECLK dECLK 11.2896 40 50 24.576 60 MHz %
MCKO1 Output Frequency
Duty fMCK1 dMCK1 4.096 40 50 24.576 60 MHz %
MCKO2 Output Frequency
Duty fMCK2 dMCK2 2.048 40 50 24.576 60 MHz %
PLL Clock Recover Frequency (RX0-7) fpll 32 - 192 kHz
LRCK2 Frequency
Duty Cycle fs dLCK 32 45 192 55 kHz %
Audio Interface Timing
Slave Mode
BICK2 Period
BICK2Pulse Width Low
Pulse Width High
LRCK2 Edge to BICK2 “↑” (Note24)
BICK2 “↑” to LRCK2 Edge (Note 24)
LRCK2 to SDTO2 (MSB)
BICK2 “↓” to SDTO2
DAUX2 Hold Time
DAUX2 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRM
tBSD
tDXH
tDXS
80
30
30
20
20
20
20
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Master Mode
BICK2 Frequency
BICK2 Duty
BICK2 “↓” to LRCK2
BICK2 “↓” to SDTO2
DAUX2 Hold Time
DAUX2 Setup Time
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
-20
20
20
64fs
50
20
15
Hz
%
ns
ns
ns
ns
Notes;
24. BICK rising edge must not occur at the same time as LRCK edge.

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 19 -
Timing Diagram(DIR/DIT part)
1/fECLK
tECLKL
VIH
tECLKH
XTI VIL
dECLK = tECLKH x fECLK x 100
= tECLKL x fECLK x 100
1/fMCK1
50%DVDDMCKO1
tMCKL1tMCKH1 dMCK1 = tMCKH1 x fMCK1 x 100
= tMCKL1 x fMCK1 x 100
1/fMCK2
50%DVDDMCKO2
tMCKL2tMCKH2 dMCK2 = tMCKH2 x fMCK2 x 100
= tMCKL2 x fMCK2 x 100
1/fs
LRCK1 VIH
VIL
tLRLtLRH dLCK = tLRH x fs x 100
= tLRL x fs x 100
Clock Timing
tLRB
LRCK1
BICK1
SDTO1
tBSD
tBLR tBCKL tBCKH
tLRM
50%DVDD
DAUX1
tDXS tDXH
VIH
VIL
VIH
VIL
VIH
VIL
tBCK
Serial Interface Timing (Slave Mode)

ASAHI KASEI AKM CONFIDENTIAL [AK4588]
Rev0.9 2003/09
- 20 -
LRCK1
BICK1
SDTO1
tBSD
tMBLR
50%DVDD
50%DVDD
50%DVDD
DAUX1
tDXHtDXS
VIH
VIL
Serial Interface Timing (Master Mode)
tPW
PDN VIL
Power Down & Reset Timing