Microsemi IGLOO nano Starter Kit User manual

IGLOO nano Starter Kit
User’s Guide

IGLOO nano Starter Kit
Revision 3 2
Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
IGLOO nano Starter Kit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Board Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Kit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Web-Based Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1 Board Components and Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IGLOO nano Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Jumper and Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FPGA Description: AGLN250V2-VQG100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Operation of Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Flash*Freeze Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
I/O Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
USB-to-UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Low-Cost Programming Stick (LCPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Board Demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Powering Up the Board and Running the Demo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
B List Of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
C Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Regulatory and Compliance Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Revision 3 3
Introduction
IGLOO nano Starter Kit Description
The IGLOO®nano starter kit is a complete package that enables you to quickly evaluate IGLOO nano
family and prototype your design. The kit allows you to develop simple designs using switches and LEDs;
or by removing the jumpers to the switches and LEDs you can then use the board to integrate the nano
device into a full system, with all user I/Os available. In both modes you can then measure power to the
device and to each I/O bank to evaluate the power consumption of your design. When using the board in
conjunction with Libero®System-on-Chip (SoC) power analysis tools, you will have a clear picture of
application power consumption at each stage in your design. In addition, the tool suite now includes
power-driven layout (PDL), which can reduce the power consumption of designs up to 30 percent. Since
IGLOO nano devices are footprint-compatible with ProASIC®3 nano devices, this kit can also be used to
prototype designs for ProASIC3 nano FPGAs.
Key Features
• Powered by USB cable or by external power (not supplied)
• Test points for measuring current consumption of the AGLN250V2-VQG100
• USB-to-UART interface for HyperTerminal on PC connected to board
• All components used on the board are low power components (i.e., LEDs (2 mA), resets (A
range), and oscillator (2-3 mA))
Board Description
The IGLOO nano evaluation board (Figure 1) enables you to measure power consumption (dynamic,
static, and Flash*Freeze modes) with the core operating at either 1.2 V or 1.5 V. When using the board in
conjunction with Microsemi’s power analysis tools, you will have a clear picture of application power
consumption at each stage in your design.
Figure 1 • IGLOO nano Evaluation Board

Introduction
4 Revision 3
In addition, the Libero SoC tool suite now includes power-driven layout (PDL), which can reduce the
power consumption of designs up to 30 percent.
The evaluation board has a small form factor, measuring 3.2 inches by 4 inches, and supports an
AGLN250 IGLOO nano device in the 14 x 14 mm VQ100 package. The evaluation board consumes less
than 150 mW. All components used on the board, such as LEDs, reset (µA range), and oscillator, are
low-power components. Also included on the evaluation board is a USB-to-UART interface to allow for
HyperTerminal on a PC to communicate with the IGLOO nano device on the board.
The right hand side of the board has a programming connector that enables the low-cost programming
stick (LCPS) to be attached to the board to program the IGLOO nano AGLN250V2-VQG100 device. I/Os
from the FPGA have been wired to pads on the board for debug purposes.
Kit Contents
Table 1 lists the contents of the IGLOO nano Starter Kit.
Web-Based Resources
Listed below are the documents currently published on the Microsemi SoC Products Group website.
Additional documents and design examples may be added to the website in the future.
Users Guides and Tutorials
IGLOO nano Starter Kit User’s Guide
www.microsemi.com/soc/documents/IGLOO_nano_StarterKit_UG.pdf
IGLOO nano Starter Kit Quickstart Card
www.microsemi.com/soc/documents/AGLN_NANO_KIT_QS.pdf
IGLOO nano Starter Kit User’s Guide
www.microsemi.com/soc/documents/IGLOO_nano_StarterKit_UG.pdf
Libero IDE Quick Start Guide
www.microsemi.com/soc/documents/gettingstarted_ug.pdf
Libero SoC User’s Guide
www.microsemi.com/soc/documents/libero_ug.pdf
FlashPro User’s Guide
www.microsemi.com/soc/documents/flashpro_ug.pdf
Table 1 • IGLOO nano Starter Kit Contents
Quantity Description
1 IGLOO nano Evaluation Board with AGLN250V2-VQG100
1 FlashPro3-compatible low-cost programming stick (LCPS)
2 USB 2.0 high-speed cables
1 Quickstart card

IGLOO nano Starter Kit
Revision 3 5
Libero Quickstart Tutorial Design Files
IGLOO nano VHDL Design Files
www.microsemi.com/soc/documents/IGLOO_nanoz_tutorial_VHDL_Libero84sp2_revB.zip
IGLOO Icicle Verilog Design Files
www.microsemi.com/soc/documents/IGLOO_Icicle_tutorial_verilog_Libero84sp2_revA.zip
IGLOO Icicle VHDL Design Files
www.microsemi.com/soc/documents/IGLOO_Icicle_tutorial_VHDL_Libero84sp2_revA.zip
Board References
IGLOO nano Starter Kit Board – Allegro PCB file
www.microsemi.com/soc/documents/IGLOO_nano_StarterKit_PCB.zip
IGLOO nano Starter Kit Board – OrCAD Schematics (DSN)
www.microsemi.com/soc/documents/IGLOO_nano_StarterKit_DSN.zip
IGLOO nano Starter Kit Board – PDF Schematics
www.microsemi.com/soc/documents/IGLOO_nano_StarterKit_SS.pdf

Revision 3 7
1 – Board Components and Settings
This chapter describes the components and settings for the IGLOO nano Evaluation Board.
Block Diagram
The IGLOO nano board Evaluation Board is shown in Figure 1-1.
Figure 1-1 • IGLOO nano Evaluation Board

Board Components and Settings
8 Revision 3
IGLOO nano Board Stackup
The IGLOO nano board is built on a four-layer printed circuit board (PCB):
1. Top Signal (Figure 1-2)
2. Power
3. GND
4. Bottom Signal (Figure 1-3 on page 9)
Figure 1-2 • Top Silkscreen

IGLOO nano Starter Kit
Revision 3 9
Figure 1-3 • Bottom Silkscreen

Board Components and Settings
10 Revision 3
Jumper and Switch Settings
Recommended default jumper settings are defined in Table 1-1. The voltage selection jumpers are
highlighted in grey. Connect jumpers in the default settings described in Table 1-1 to enable the pre-
programmed demo design to function correctly.
Table 1-1 • Jumper Settings for Demo Design
Jumper Default Setting Comment
JP1 Pin 2-3 Main power supply. Connect Wall/USB input to VCC_IN.
JP2 Pin 2-3 VCC CORE voltage (1.2 / 1.5 V)
Pin 2-3 selects 1.2 V.
Pin 1-2 selects 1.5 V.
Jumper is on upper right area of board.
JP3 Pin 2-3 Current measurement header for Bank 0
JP4 Pin 2-3 Current measurement header for VCC_B2 (Bank 2)
JP5 Pin 1-2 Voltage selection for VCC B0 (Bank 0)
Pin 1-2 selects 3.3 V.
Pin 3-4 selects 2.5 V.
Pin 5-6 selects VCC_CORE.
JP6 Pin 2-3 Current measurement header for Bank 1
JP7 Pin 2-3 Current measurement header for VCC_B3 (Bank 3)
JP8 Pin 1-2 Voltage selection for VCC B1 (Bank 1)
Pin 1-2 selects 3.3 V.
Pin 3-4 selects 2.5 V.
Pin 5-6 selects VCC_CORE.
JP9 Pin 2-3 Current measurement header for JTAG supply.
JP10 Pin 2-3 Current measurement header for VCC (FPGA core supply).
JP11 Pin 1-2 Voltage selection for VCC JTAG (JTAG supply.
Pin 1-2 selects 3.3 V.
Pin 3-4 selects 2.5V.
Pin 5-6 selects VCC_CORE.
JP12 Pin 2-3 Current measurement header for VCC_PUMP (FPGA charge pump
supply)
JP13 Pin 1-2 Remove each short default jumper to disconnect any of the 8 LEDs from
the FPGA.
JP14 Pin 1-2 Remove each short default jumper to disconnect any of the 8 DIP switches
SW3.1 through SW3.8 from the FPGA.
By default, SW3.1 through SW3.8 should all be closed (set to the ON
settings).
The 8 DIP switches are connected to the 8 LEDs (LED1, LED2, … LED8).
JP15 Pin 1-2 Remove each short default jumper to disconnect any of the four push-
button switches, SW4 through SW7, from the FPGA.
SW1 OFF Flash*Freeze: To enable Flash*Freeze mode, slide SW1 toward FF_ON.
In Flash*Freeze mode, current consumption of the FPGA goes below
50 µA. Current can be measured by placing a current meter between [pin1
or pin 2] and [pin 3 or pin 4] of JP10 (VCC_CORE).

IGLOO nano Starter Kit
Revision 3 11
FPGA Description: AGLN250V2-VQG100
This IGLOO nano board is populated with an IGLOO nano AGLN250V2-VQG100 FPGA. An IGLOO
nano AGLN250 FPGA supports the enhanced nano features of Schmitt Trigger input, bus hold (holds
previous I/O state in Flash*Freeze mode), cold-sparing, hot-swap I/O capability, and 1.2 V programming.
In Designer, users can target their design to use either IGLOO AGL250 or IGLOO nano AGLN250. Some
features are listed in the "Key Features" section and Table 1-2. Refer to the IGLOO nano Datasheet for
additional features.
Key Features
• Ultra-low power in Flash*Freeze mode
• Enhanced commercial temperature
• Reprogrammable flash technology
• 1.2 V to 1.5 V single voltage operation
• Enhanced I/O features
• Selectable Schmitt trigger Inputs
• Clock conditioning circuits (CCCs) and integrated PLLs
• Embedded SRAM and nonvolatile memory (NVM)
• In-system programming (ISP) and security
For further information, refer to the IGLOO nano datasheet:
www.microsemi.com/soc/documents/IGLOO_nano_DS.pdf.
Table 1-2 • Features of AGLN250V2-VQG100
Component Specification
System Gates 250,000
Typical Equivalent Macrocells 2,048
VersaTiles (D-flip-flops) 6,144
Flash*Freeze Mode (Typical, µW) 24
RAM kbits (1,024 bits) 36
4,608-Bit Blocks 8
FlashROM (bits) 1,024
Secure (AES) ISP Yes
Integrated PLLs in CCCs 1
VersaNet Globals 18
I/O Standards Std. or Hot-Swap
I/O Banks 4
Speed Grades Std.
Temperature Grade C, I
Single-Ended I/Os 68

Board Components and Settings
12 Revision 3
AGLN250V2-VQG100 I/O Banks and Pins
Figure 1-4 shows the I/O banks for AGLN250V2-VQG100.
Figure 1-4 • AGLN250V2-VQG100 Banks 0–3 Schematic
agl_b0_p98
[8] agl_b0_p85 [8]
agl_b0_p97[8]
agl_b0_p95[8]
agl_b0_p96[8]
agl_b0_p93[8]
agl_b0_p91[8]
agl_b0_p92
[8]
agl_b0_p94[8]
agl_b0_p86
[8]
agl_b0_p90
[8]
agl_b0_p84 [8]
agl_b0_p83 [8]
agl_b0_p82 [8]
agl_b0_p80 [8]
agl_b0_p79 [8]
agl_b0_p78 [8]
agl_b0_p81 [8]
agl_b0_p76 [8]
agl_b0_p77 [8]
agl_b1_p57 [8]
agl_b1_p58 [8]
agl_b1_p59 [8]
agl_b1_p60 [8]
agl_b1_p61 [8]
agl_b1_p62 [8]
agl_b1_p63 [8]
agl_b1_p64[8]
agl_b1_p65[8]
agl_b1_p69[8]
agl_b1_p70[8]
agl_b1_p71[8]
agl_b1_p72[8]
agl_b1_p73[8]
agl_b2_p26 [6,8]
agl_b2_p27 [5,8]
agl_b2_p28 [6,8]
agl_b2_p29 [6,8]
agl_b2_p30 [6,8]
agl_b2_p31 [6,8]
agl_b2_p32 [6,8]
agl_b2_p33 [6,8]
agl_b2_p34[6,8]
agl_b2_p35[6,8]
agl_b2_p36[6,8]
agl_b2_p40[6,8]
agl_b2_p41[6,8]
agl_b2_p42
[6,8]
agl_b2_p43[6,8]
agl_b2_p44
[6,8]
agl_b2_p45
[6,8]
agl_b3_p2 [8]
agl_b3_p3 [8]
agl_b3_p4 [8]
agl_b3_p5 [8]
agl_b3_p6 [8]
agl_b3_p7 [8]
agl_b3_p8 [8]
agl_b3_p11[8]
agl_b3_p20
[6,8]
agl_b3_p21
[6,8]
agl_b3_p22[6,8]
agl_b3_p23
[6,8]
agl_txd[7]
agl_rxd[7]
agl_b3_p13
[8]
agl_reset_n [5]
agl_clk[5]
IO43RSB2 33
IO44RSB2 32
IO45RSB2 31
IO46RSB2 30
IO47RSB2 29
GEC2/IO48RSB2 28
FF/GEB2/IO49RSB2 27
GEA2/IO50RSB2 26
GDA2/IO34RSB2
45
GDB2/IO35RSB2
44
GDC2/IO36RSB2
43
IO37RSB2
42
IO38RSB2
41
IO39RSB2
40
IO40RSB2
36
IO41RSB2
35
IO42RSB2
34
IO BANK2
U5C
AGLN250V2-VQG100
IO BANK2
U5C
AGLN250V2-VQG100
GCA0/IO28RSB1 63
GCA1/IO27RSB1 62
GCB2/IO29RSB1 61
IO30RSB1 60
GDC1/IO31RSB1 59
GDC0/IO32RSB1 58
GDA1/IO33RSB1 57
GBA2/IO20RSB1
73
IO21RSB1
72
GBB2/IO22RSB1
71
GBC2/IO23RSB1
70
IO24RSB1
69
GCC1/IO25RSB1
65
GCC0/IO26RSB1
64
IO BANK1
U5B
AGLN250V2-VQG100
IO BANK1
U5B
AGLN250V2-VQG100
GFB1/IO60RSB3 10
IO61RSB3 8
IO62RSB3 7
GAC2/IO63RSB3 6
IO64RSB3 5
GAB2/IO65RSB3 4
IO66RSB3 3
GAA2/IO67RSB3 2
GEA0/IO51RSB3
23
GEA1/IO52RSB3
22
GEC0/IO53RSB3
21
GEC1/IO54RSB3
20
GFC2/IO55RSB3
19
GFA2/IO56RSB3
16
GFA1/IO58RSB3
15
GFA0/IO57RSB3
13
GFB0/IO59RSB3
11
IO BANK3
U5D
AGLN250V2-VQG100
IO BANK3
U5D
AGLN250V2-VQG100
IO10RSB0 85
IO11RSB0 84
IO12RSB0 83
IO13RSB0 82
GBC0/IO14RSB0 81
GBC1/IO15RSB0 80
GBB0/IO16RSB0 79
GBB1/IO17RSB0 78
GBA0/IO18RSB0 77
GBA1/IO19RSB0 76
GAA0/IO00RSB0
98
GAA1/IO01RSB0
97
GAB0/IO02RSB0
96
GAB1/IO03RSB0
95
GAC0/IO04RSB0
94
GAC1/IO05RSB0
93
IO06RSB0
92
IO07RSB0
91
IO08RSB0
90
IO09RSB0
86
IO BANK0
U5A
AGLN250V2-VQG100
IO BANK0
U5A
AGLN250V2-VQG100

IGLOO nano Starter Kit
Revision 3 13
This FPGA has advanced I/O features such as JTAG pins for the IEEE 1149.1 JTAG Boundary Scan Test
(Figure 1-5).
FPGA decoupling capacitors are placed close to the power pins (Figure 1-7).
Figure 1-5 • AGLN250V2-VQG100 JTAG Pins
Figure 1-6 • AGLN250V2-VQG100 Power and GND pins
Figure 1-7 • Decoupling Capacitors
agl_tdo [5]
agl_tms [5]
agl_tdi[5]
agl_tck[5]
agl_trst[2,5]
TDO 54
TMS 49
NC 53
TDI
48
TCK
47
TRST
55
JTAG & Special
U5E
AGLN250V2-VQG100
JTAG & Special
U5E
AGLN250V2-VQG100
R18 39R-0603R18 39R-0603
R19
1K-0603
R19
1K-0603
R20
1K-0603
R20
1K-0603
VCC_PUMP VCC_JTAGVCC
VCC_B0
VCC_B1
VCC_B2
VCC_B3
VCC VCC_PLF
Ferrite Bead
FB1
EBMS321611B190-1206
FB1
EBMS321611B190-1206
VPUMP 52
VJTAG 56
GND1 1
GND2 9
GND3 38
GND4 51
GND5 67
GND6 88
GNDQ1 25
GNDQ2 46
GNDQ3 75
GNDQ4 99
VCOMPLF 12
VCC1
17
VCC2
37
VCC3
68
VCC4
89
VCCIB0
87
VMV0
100
VCCIB1
66
VMV1
74
VCCIB2
39
VMV2
50
VCCIB3
18
VMV3
24
VCCPLF
14
SUPPLY
U5F
AGLN250V2-VQG100
SUPPLY
U5F
AGLN250V2-VQG100
C18
10u-TantA
C18
10u-TantA
VCC_B0 VCC_B1 VCC_B2 VCC_B3VCC VCC_PLF VCC_PUMP VCC_JTAG
FPGA Decoupling Capacitors - Place close to power pins
C2610n-0603 C2610n-0603 C23100n-0603 C23100n-0603 C29100n-0603 C29100n-0603 C21100n-0603 C21100n-0603 C3410n-0603 C3410n-0603 C25100n-0603 C25100n-0603 C2410n-0603 C2410n-0603 C3210n-0603 C3210n-0603 C3610n-0603 C3610n-0603 C27100n-0603 C27100n-0603 C3010n-0603 C3010n-0603 C2210n-0603 C2210n-0603 C33100n-0603 C33100n-0603 C2010n-0603 C2010n-0603 C35100n-0603 C35100n-0603 C2810n-0603 C2810n-0603 C31100n-0603 C31100n-0603 C19100n-0603 C19100n-0603

Revision 3 15
2 – Power
The IGLOO nano development board is powered through an external voltage power brick or USB. If both
the power brick and USB are plugged in, the development board will power through the power brick. If
the power brick is unplugged, the board will seamlessly switch to power through the USB. In the USB
option, in-rush current meets USB specifications. The power brick option is provided in cases when
100% of total I/Os are utilized.
The development board has an input of a 5 V supply from the power brick. Protection diodes are used to
protect against negative voltage. Three voltage rails (3.3 V, 2.5 V, and 1.5 V) are provided.
The regulator can be switched between the 1.5 V and 1.2 V rail because the FPGA core functions at
1.2 V, but is programmed at 1.5 V. A green LED will glow whenever the USB power is connected.
Table 2-1 gives the current ratings for each voltage rail.
Figure 2-1 shows the schematic for the power LED9.
Power Modes
In addition to the board, the IGLOO nano FPGA offers power advantages. Some key power advantages
of the IGLOO nano FPGAs are as follows:
• Flash*Freeze technology enables easy entry and exit from the static low power mode, whereas
IGLOO consumes as little as 5 µW while retaining the contents of the system memory and data
registers.
• Sleep and shutdown modes enable the IGLOO nano FPGA core power supply (or all power
supplies) to be powered down when functionality is not required, while the rest of the system
remains powered.
• The user low static ICC macro (ULSICC) reduces IGLOO nano FPGA dynamic and static power
consumption. The ULSICC macro, when enabled, disables the FlashROM, reducing the overall
power of the device.
Table 2-1 • Power Regulator Current Ratings
Regulator Current Rating
3.3 V 2A
2.5 V 1A
1.5 V 1A
Figure 2-1 • Power LED Schematic
VCC_vbus
USB Connected
R38
560R-0603
R38
560R-0603
12
LED9
GREEN SMD LED - 1206
LED9
GREEN SMD LED - 1206

Power
16 Revision 3
Table 2-2 gives a summary of the power modes available with IGLOO nano devices in general and is
extracted from the “Flash*Freeze Technology and Low Power Modes” chapter of the IGLOO nano FPGA
Fabric User’s Guide.
BatteryThe VIN (minimum output voltage) for the battery is 3 V. Potentially two Alkaline cells or button cells,
such as LIR2450, can be used to power the board. In order to power through the higher voltage from the
power brick or lower voltage from the battery, special regulators are used to meet the voltage
requirements. The 3.3 V regulator used is a buck-boost type instead of a regular LDO type.
No battery casing is provided on the board. A 2-pin jumper for VBAT and GND must be provided to the
input of the main regulator; you have the option of powering through a wall/USB or powering through
external batteries.
Table 2-2 • Power Modes
Mode VCC VCCI Core Clocks ULSICC Macro To Enter Mode To Resume Operation Trigger
Active On On On On N/A Initiate clock None –
Static Idle On On On Off N/A Stop clock Initiate clock External
Flash*Freeze
Type 1 On On On On* N/A Assert FF pin Deassert FF pin External
Flash*Freeze
Type 2 On On On On* Used to enter Flash*Freeze
mode
Assert FF pin
and LSICC Deassert FF pin External
Sleep On Off Off Off N/A Shut down VCC Turn on VCC External
Shutdown Off Off Off Off N/A ShutdownVCC
and VCCI
supplies
Turn on VCC
and VCCI
supplies
External
Note: *External clocks can be left toggling while the device is in Flash*Freeze mode. Clocks generated by the
embedded PLL will be turned off automatically.
Figure 2-2 • Battery Header and Power Input Schematics
VCC_BAT
Battery Header
1
2
J1
2x1 Header (M)
J1
2x1 Header (M)
VCC_in
VCC_BAT
Note:
Short Pins 2-1: Battery Power Input
Short Pins 2-3: Wall/USB Power Input
C1
10u-TantA
C1
10u-TantA
1
2
3
JP1
3x1 Header (M)
JP1
3x1 Header (M) C2
2u2-0603
C2
2u2-0603

IGLOO nano Starter Kit
Revision 3 17
Current Measurement
Once the IGLOO nano evaluation board is powered up, you can evaluate power usage by current
consumption, using the current measurement pins on the board. All banks are separated and two of the
banks have the option of powering through 3.3 V or 2.5 V.
Once the IGLOO nano evaluation board is powered up, you can evaluate power consumption using the
current measurement 4-pin headers on the board (Figure 2-3). Current measurement can be made
without powering down the board.
Set the multimeter to measure current and attach the
probes to pins 1 and 4 when the board is in normal
operation.
Remove jumper from pins 2-3 for current
measurement without powering down.
Figure 2-3 • Current Measurement 4-Pin Headers

Power
18 Revision 3
Figure 2-4 shows the schematic for the current measurement headers.
Figure 2-4 • Current Measurement Header Schematic
VCC_3_3 VCC_B2VCC_B0
VCC_B3VCC_B1
VCC_CORE VCC
VCC_3_3 VCC_PUMP
VCC_JTAG
VCC_3_3
VCC_3_3VCC_2_5VCC_CORE
VCC_3_3VCC_2_5VCC_CORE
VCC_3_3VCC_2_5VCC_CORE
Note:
Current Measurement Jumpers:
Short Pins 2-3 for normal operation.
Note:
Short Pins 1-2: +3.3V
Short Pins 3-4: +2.5V
Short Pins 5-6: VCC_CORE (+1.5V/+1.2V)
Note:
Short Pins 1-2: +3.3V
Short Pins 3-4: +2.5V
Short Pins 5-6: VCC_CORE (+1.5V/+1.2V)
Note:
Short Pins 1-2: +3.3V
Short Pins 3-4: +2.5V
Short Pins 5-6: VCC_CORE (+1.5V/+1.2V)
1 2
3 4
5 6
JP5
3x2 Header (M)
JP5
3x2 Header (M)
1 2
3 4
5 6
JP11
3x2 Header (M)
JP11
3x2 Header (M)
1 2 3 4
JP3
4x1 Header (M)
JP3
4x1 Header (M)
1 2
3 4
5 6
JP8
3x2 Header (M)
JP8
3x2 Header (M)
1 2 3 4
JP4
4x1 Header (M)
JP4
4x1 Header (M)
1 2 3 4
JP6
4x1 Header (M)
JP6
4x1 Header (M)
1 2 3 4
JP9
4x1 Header (M)
JP9
4x1 Header (M)
1 2 3 4
JP10
4x1 Header (M)
JP10
4x1 Header (M)
1 2 3 4
JP7
4x1 Header (M)
JP7
4x1 Header (M)
1 2 3 4
JP12
4x1 Header (M)
JP12
4x1 Header (M)

Revision 3 19
3 – Operation of Board Components
This chapter describes operation of the IGLOO nano Evaluation Board.
Clock Oscillator
One 20 MHz clock oscillator is provided on the board. The specifications are shown in Table 3-1. When
combined with the on-chip CCC/PLL block, a wide range of clock frequencies can be created to support
various design requirements.
Reference
Additional information on this clock oscillator is available at the IGLOO nano Starter Kit website:
www.microsemi.com/soc/products/hardware/devkits_boards/igloonano_starter.aspx.
Schematic
Figure 3-1 shows the schematic for the clock oscillator.
Table 3-1 • Clock Specifications
Feature Specification
Frequency 20 MHz
Package/Case SMD 3.2 mm x 2.5 mm
Supply Voltage 3.3 V
Current Supply 5 mA
Operating Temperature –20°C to 70°C
Frequency Stability ±100 ppm
RoHS Status RoHS compliant
Duty – CMOS level (1/2 VDD) 40–60%
Rise and Fall Time (0.2 VDD and 0.8 VDD) 10 ns (maximum)
Start-up Time 10 ms (maximum)
Figure 3-1 • Clock Oscillator Schematic
VCC_3_3
agl_clk [4]
20MHz SMD XTAL
C41100n-0603 C41100n-0603 C39100n-0603 C39100n-0603
SP9
CLK
SP9
CLK
VCC
4
GND
2
OUT 3
OE 1
Y1
CSX325FJC20.000M-UT
Y1
CSX325FJC20.000M-UT
C401n-0603 C401n-0603
L2
47n-0603
L2
47n-0603

Operation of Board Components
20 Revision 3
Reset A push-button reset switch with a Schmitt-triggered device (DS1818) is provided for the IGLOO nano
AGLN250 FPGA populated on the board. This Schmitt trigger device can be bypassed because an
AGLN250 FPGA supports additional I/O advanced features such as Schmitt trigger.
The DS1818 uses a precision temperature-compensated reference and comparator circuit to monitor the
status of the power supply (VCC). When an out-of-tolerance condition is detected, an internal power-fail
signal is generated which forces reset to the active state. When VCC returns to an in-tolerance condition,
the reset signal is kept in the active state for approximately 150 ms to allow the power supply and
processor to stabilize.
Reference
Additional information on this push-button reset switch is available at the IGLOO nano Starter Kit
website:
www.microsemi.com/soc/products/hardware/devkits_boards/igloonano_starter.aspx.
Schematic
Figure 3-2 shows the schematic for reset.
Figure 3-2 • Reset Schematic
VCC_3_3
VCC_3_3
agl_reset_n [4]
RESET Switch
Notes:
When Schmitt-triggered chip is used, keep the capacitor
NL (Default). When IGLOO's Schmitt trigger I/O is used,
keep DS1818 NL and populate the capacitor to implement
standard RC Reset Push-Button Switch.
R22 0R-0603R22 0R-0603
C38
NL-1u-0603
C38
NL-1u-0603
R21
10K-0603
R21
10K-0603
RST_n 1
VCC
2
GND
3
U6
DS1818R-20-U+-SOT23
U6
DS1818R-20-U+-SOT23
C37
100n-0603
C37
100n-0603 1
4
2
3
SW7
SW PUSHBUTTON-SPST-2
SW7
SW PUSHBUTTON-SPST-2