Alcatel-Lucent OmniPCX NDDI2-2 User manual

Alcatel-Lucent OmniPCX Enterprise
Communication Server
NDDI2-2 (LS/GS)

Legal notice:
Alcatel, Lucent, Alcatel-Lucent and the Alcatel-Lucent logo are trademarks of
Alcatel-Lucent. All other trademarks are the property of their respective
owners.
The information presented is subject to change without notice.
Alcatel-Lucent assumes no responsibility for inaccuracies contained herein.
Copyright © 2012 Alcatel-Lucent. All rights reserved.
The CE mark indicates that this product conforms to the following Council
Directives:
- 2004/108/EC (concerning electro-magnetic compatibility)
- 2006/95/EC (concerning electrical safety)
- 1999/5/EC (R&TTE)

Chapter 1
Hardware description
 Presentation .............................................................................................1.1
 Environment .............................................................................................1.1
 Functional blocks ...................................................................................1.2
 QLSLAC ........................................................................................................1.3
 Analog interfaces ...........................................................................................1.4
 DSP module ..................................................................................................1.4
 Common part .................................................................................................1.5
 Power supply .................................................................................................1.5
Chapter 2
Hardware configuration
 Reference ..................................................................................................2.1
 Overview ....................................................................................................2.1
 Assembling NDDI2–2 board ...............................................................2.2
 Assembling QATI–2 daughter board ...............................................2.4
 Jumpers on NDDI2–2 and QATI-2 boards .....................................2.5
 NDDI2–2 LED ............................................................................................2.6
 
  
  0-1

Chapter 3
External connections
 Connection ...............................................................................................3.1
 Output pins on NDDI2–2 board .........................................................3.2
Chapter 4
CLIPIA Daugtherboard - Operation
 Overview ....................................................................................................4.1
 CLIP function ...........................................................................................4.1
 Metering function ...................................................................................4.1
Chapter 5
CLIPIA Daughterboard - Configuration
 Reference ..................................................................................................5.1
 Board assembly ......................................................................................5.1
Chapter 6
Ground Start (GS) Daughterboard - Operation
 Overview ....................................................................................................6.1
 Operation ...................................................................................................6.1
 
0-2  

Chapter 7
Metering Detection Daughter Board
 Overview ....................................................................................................7.1
 
  0-3

 
0-4  

1.1 Presentation
The Loop Start / Ground Start (LS/GS) board is also called Non Direct Dialing In (NDDI2-2)
board. It is an analog board which allows the Private Automatic Branch eXchange (PABX) to
be connected to most public networks. Furthermore, this board allows the PABX to be
connected to a pager system according to the ESPA standard.
The NDDI2-2 board can connect up to eight 2-wire analog lines. Lines 1 to 4 are processed on
the mother board and lines 5 to 8 are processed on the QATI-2 daughter board.
The NDDI2-2 board can handle the following optional daughter boards :
- Calling Line Identification Protocol Interface Adaptor (CLIPIA) board:
This board allows the line impedance to be modified to identify the caller and to detect the
metering pulses.
For more information on the CLIPIA board, see NDDI2-2(LS/GS) - CLIPIA Daugtherboard -
Operation .
- Tax Metering board:
This board is used to detect 12/16 KHz metering pulses.
For more information on the Tax Metering board, see NDDI2-2(LS/GS) - Metering
Detection Daughter Board .
- Ground Start board:
This board is used to seize the line via the ground and to detect incoming calls via
grounding a line wire.
Note:
The Ground Start board is only available in the US market.
Each daughter board is dedicated to 4 network lines, i.e. 2 daughter boards are necessary to
handle 8 lines of an NDDI2-2 board.
For more information on the NDDI2-2 board configuration, see NDDI2-2(LS/GS) - Hardware
configuration .
For more information on the NDDI2-2 board connection, see NDDI2-2(LS/GS) - External
connections .
1.2 Environment
The following figure shows the front and back panel connections of the NDDI2-2 board.
___change-begin___

 
      ! "  #$!%$!  &!'()'* 1-1

___change-end___
Figure 1.1: Input/Output diagram - NDDI2–2 (LS/GS) board
1.3 Functional blocks
The NDDI2-2 board is made up of the following functional blocks:
- Quad Low voltage Subscriber Line Audio - processing Circuit (QLSLAC),
- Analog interfaces,
- Digital Signal Processing (DSP) module,
- Common part,
- Power supply.
The following figure shows how the functional blocks of the NDDI2-2 board are organized.
___change-begin___
Chapter 1#$!%$!  &!'()'*
1-2       ! "  #$!%$!  &!'()'*

___change-end___
Figure 1.2: Functional block diagram - NDDI2–2 (LS/GS) board
1.3.1 QLSLAC
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      ! "  #$!%$!  &!'()'* 1-3

A/D and D/A voice signal conversion is ensured by 2 QLSLAC circuits. Each Quad Low
voltage Subscriber Line Audio - processing Circuit (QLSLAC) contains 4 coders-decoders
(CODECS) and supports 4 analog interfaces.
One Time Division Multiplex (TDM) or TS allocation connects both QLSLAC to circuit C1.
The QLSLAC acts as:
- an interface between :
• the Pulse Code Modulation (PCM) bus (Time-Slot Assigner (TSA)) and the processor,
• the SLIC OET/CET management and 4 Signal Processing Channels (SPC),
- the programmable software for transmission features (input impedance, reception and
transmission gains, echo cancellation, µ or A laws coding, etc.).
1.3.2 Analog interfaces
Analog interfaces:
- control the signalling,
- transmit voice,
- receive messages to identify the caller (CLIP), if any.
Interfaces are made up of the following parts:
- protection circuits which consist of:
• overvoltage protection circuits to avoid damage in case of any short circuit,
• EMI filtering circuits to reduce the RFI effects on the telephone line-card.
- impedance for ringing signal:
A firmware command allows a low or high impedance to be connected. This command
allows, with a specific equipment (country dedicated daughter board), either a ringing
impedance or a spark quench circuit to be connected (loop protection circuit during
dialing).
- loop circuits which can be:
• on line loop, a high dynamic impedance circuit with DC current limitation (compatible
with TBR21),
• dialing loop (very low resistance).
- loop current detector.
- polarity detector:
Still used for paging, its use depends on the country for NDDI operation. The polarity can
be detected only if a DC current loop is present.
- interface for AC signalling at hang-up:
The interface allows the AC signalling received during the hang-up phase to be transmitted
from the line to the QLSLAC (to be detected by the DSP). This signaling can be ringing,
dual tone (DT-AS), DTMF, V23 or Bell202 type for line call identification messages (CLIP
function).
1.3.3 DSP module
The Digital Signal Processing (DSP) module has the following functions:
Chapter 1#$!%$!  &!'()'*
1-4       ! "  #$!%$!  &!'()'*

- Tone detection:
Eight channels are available for tone detection. The different paces are validated by the
firmware coupler, levels and frequencies are validated by the DSP software.
- External tone detection on the NDDI2-2 interfaces:
There are two types of tone:
• Dial tone,
• Busy tone.
- Ringing detection:
Eight ringing detection channels are necessary on the NDDI2-2 board. The different paces
are validated by the firmware coupler, levels and frequencies are validated by the DSP
software. The detector must handle frequencies ranging from 14.5 to 68 Hz.
- TAMIS Terminal equipment Alert Signaling (TAS) detection:
Eight TAS detection channels are necessary on the NDDI2-2 board. The TAS can be :
• Dual Tone Alert Signalling (DT-AS),
• Ringing Pulse Alert Signalling (RP-AS).
- Frequency Shift Keying (FSK) demodulation:
Eight FSK demodulation channels are necessary on the NDDI2-2 board (eight FSK carrier
detections are provided). FSK has the following features:
• bit duration: 833 µs,
• 0 logical frequency: 2200 ± 22 Hz (Bellecore) or 2100 ± 16 Hz (ETSI),
• 1 logical frequency: 1200 ± 12 Hz (Bellecore) or 1300 ± 16 Hz (ETSI),
• Signal level reception: -12 to 32.5 dBm (Bellecore) or -11 to -35 dBm (ETSI).
- Dual Tone Multi-Frequency (DTMF) detection:
In some countries, the messages can be transmitted using the 16 DTMF codes.
1.3.4 Common part
The common part is the interface between the NDDI2-2 board and the other ACT boards.
The Revision Code Number (RCN) register of the QLSLAC recognizes the NDDI2-2 board.
The MIC 0 link rated at 2.048 MHz transmits voice for 8 NDDI2-2 lines.
For more information on the common part, see Common Part - Common part.
1.3.5 Power supply
From -48V power supply, the CM8 converter supplies the NDDI2-2 board with +5V, -5V and
+12V.
3.3V regulators supply the QLSLAC and the DSP module.
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Chapter 1#$!%$!  &!'()'*
1-6       ! "  #$!%$!  &!'()'*

2.1 Reference
The NDDI2-2 reference is 3BA 23171 AB.
QATI-2 is the daughter board of the NDDI2-2 board. The QATI-2 reference is 3BA 23184 AB.
2.2 Overview
The following figure gives an overview of the NDDI2-2 (LS/GS) board, its daughter boards and
its jumpers.
___change-begin___

 
$     ()  !   #$!%$! *+',-!$)'* 2-1

___change-end___
Figure 2.1: NDDI2–2 (LS-GS) board with jumpers
2.3 Assembling NDDI2–2 board
Before assembling the NDDI2-2 board, you need to remove the QATI-2 daughter board.
The following figures show how the NDDI2-2 board is assembled and what the different jumper
positions are on the board.
___change-begin___
___change-end___
___change-begin___
___change-end___
___change-begin___
___change-end___
Note 1:
When the DC current loop jumper is removed, the current is limited to 28 mA.
___change-begin___
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2-2 $     ()  !   #$!%$! *+',-!$)'*

___change-end___
Caution:
Before positioning the input/output impedance jumpers, you are advised to contact
Alcatel-Lucent technical support because the positioning of these jumpers depends on the
country, specially countries with complex impedances.
___change-begin___
___change-end___
___change-begin___
___change-end___
Note 2:
The assemblies represented with grey background are the ex-factory assemblies.
For more information on the position of the jumpers on the boards and equipment number, see
Jumpers on NDDI2–2 and QATI-2 boards .
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The X904 assembly is not equipped with jumpers.
2.4 Assembling QATI–2 daughter board
After assembling the NDDI2-2 board, you can assemble the QATI-2 daughter board.
The following figure gives an overview of the QATI-2 daughter board and its jumpers.
___change-begin___
___change-end___
Figure 2.8: QATI-2 board with jumpers
The following figures show how the QATI-2 daughter board is assembled and what the
different jumper positions are on the board.
___change-begin___
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2-4 $     ()  !   #$!%$! *+',-!$)'*

___change-end___
Note 1:
When the DC current loop jumper is removed, the current is limited to 28 mA.
___change-begin___
___change-end___
Caution:
Before positioning the input/output impedance jumpers, you are advised to contact
Alcatel-Lucent technical support because the positioning of these jumpers depends on the
country, specially countries with complex impedances.
Note 2:
When the DC current loop jumper is removed, the current is limited to 28 mA.
For more information on the position of the jumpers on the boards and equipment number, see
Jumpers on NDDI2–2 and QATI-2 boards .
2.5 Jumpers on NDDI2–2 and QATI-2 boards
The following table gives the positioning of the jumpers on the NDDI2-2 (mother board) and
QATI-2 (daugther board) boards.
table 2.1: Jumpers on NDDI2–2 and QATI-2 boards
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Board name Equipment number
(Interface) DC current loop jumpers Input/Output impedance
jumpers
NDDI2-2 (mother
board) Equipment 1 X1011 X1111
Equipment 2 X1021 X1121
Equipment 3 X1031 X1131
Equipment 4 X1041 X1141
QATI-2 (daughter
board) Equipment 5 X1011 X1111
Equipment 6 X1021 X1121
Equipment 7 X1031 X1131
Equipment 8 X1041 X1141
Caution:
Before positioning the input/output impedance jumpers, you are advised to contact
Alcatel-Lucent technical support because the positioning of these jumpers depends on the
country, specially countries with complex impedances.
2.6 NDDI2–2 LED
The following figure shows the front panel of the NDDI2-2 board with its LED (Light Emitting
Diode).
___change-begin___
___change-end___
Figure 2.11: NDDI2–2 (LS/GS) board front panel LED
The following table gives the meaning of the NDDI2-2 LED.
table 2.2: Meaning of LED
LED Meaning
CPU (green LED) Processor activity indicator LED
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LED Meaning
BSY (orange LED) Activity indicator LED of at least one trunk
The following table gives the meaning of the different status of the CPU LED.
table 2.3: Meaning of CPU LED status
Status Meaning
Always ON Initializing
100 ms (ON) / 1 s (OFF) Loading in progress
10 ms (ON) / 10 ms (OFF) Boot flashing
300 ms (ON) / 300 ms (OFF) CPU waiting
8 x (900 ms (ON) / 600 ms (OFF)) / 1 s
(OFF) RAM test error
8 x (300 ms (ON) / 600 ms (OFF)) / 1 s
(OFF) Cheksum error
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