Alinx AC7010BB User manual

ZYNQ7000 FPGA
Core Board
AC7010BB/AC7020BB
User Manual

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Version Record
Revision
Date
Release By
Description
Rev 1.0
2022-09-07

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Table of Contents
Version Record .............................................................................................2
Part 1: Introduction ....................................................................................... 5
Part 2: Dimensional structure .......................................................................8
Part 3: Power Supply ....................................................................................8
Part 4: ZYNQ Chip ......................................................................................10
Part 4.1: JTAG Interface ..................................................................... 13
Part 4.2: FPGA Power System ........................................................... 13
Part 4.3: ZYNQ boot configuration ..................................................... 14
Part 5: Clock Configuration ........................................................................ 15
Part 5.1: PS system clock source .......................................................15
Part 5.2: PL system clock source ....................................................... 16
Part 6：ZYNQ Processor System (PS) peripherals ..................................16
Part 6.1: QSPI Flash ........................................................................... 17
Part 6.2: DDR3 DRAM ........................................................................ 18
Part 6.3: Gigabit Ethernet Interface ....................................................22
Part 6.4: USB2.0 Interface ..................................................................24
Part 6.5: USB to Serial Port ................................................................ 26
Part 6.6: SD Card Slot ........................................................................ 28
Part 6.7: User LEDs ............................................................................ 29
Part 6.8: Reset Key .............................................................................30
Part 7：ZYNQ PL Peripherals ................................................................... 30
Part 7.1: User LEDs ............................................................................ 30
Part 7.2: Expansion Port J10 ..............................................................31
Part 7.3: Expansion Port J11 .............................................................. 34
Part 7.4: Expansion Port J12 ..............................................................36

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The two core boards of the ALINX XILINX ZYNQ7000 development
platform were officially released in 2022, models: AC7010B and AC7020B
(industrial grade). Their development platform is the solution for XILINX's
Zynq7000 SOC chip. It uses ARM+FPGA SOC technology to integrate
dual-core ARM Cortex-A9 and FPGA programmable logic on a single chip. The
AC7010B core board uses Xilinx's Zynq7000 series XC7Z010-1CLG400C as
the core processor, and the AC7020B core board uses the industrial grade
XC7Z020-2CLG400I chip. Extensive peripheral interfaces such as Gigabit
Ethernet, USB2.0, serial port, SD card, etc. are extended on the ARM side. In
addition, the core board expands a large number of IOs to the outer three
connectors, including 94 IO ports of the PL (47 pairs of LVDS differential) and 8
MIO ports of the PS. For users who need a lot of IO, this core board will be a
good choice, and it is also very suitable for secondary development.
The design of the core board adheres to the design concept of “exquisite,
practical and concise”. It is not only suitable for the software verification of the
software staff, but also suitable for the hardware design of hardware
developers, that is, the system cooperation of software and hardware, and
accelerated the development process of the project.

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Part 1: Introduction
Here, a brief introduction to the ZYNQ7000 core board
AC7010B/AC7020B is provided.
The core board uses Xilinx's Zynq7000 series of chips, the AC7010B uses
the Zynq7000's XC7Z010-1CLG400C chip, and the AC7020B uses the
Zynq7000's XC7Z020-2CLG400I chip, both of which are 400-pin FBGA
packages. The ZYNQ7000 chip can be divided into a processor system part
processor system (PS) and a programmable logic part Programmable Logic

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(PL).
On the AC7010B/AC7020B core board, the PS part of the ZYNQ7000 is
equipped with a wealth of external interfaces and devices for user convenience
and function verification. The IO ports on the PL side are all led to the 2.54mm
connector on the board for user expansion. In addition, there is a 7 x 2 JTAG
connector on the core board that can be downloaded and debugged via the
ALINX Xilinx USB Cable Downloader. Figure 1-2 shows the structure of the
entire AC7010B/AC7020B system:
Figure 1-1: The Schematic Diagram of the AC7010B/AC7020B
Through this diagram, you can see the interfaces and functions that the
AC7010B/AC7020B FPGA Core Board contains:
DC5V power input, maximum current does not exceed 500mA
Xilinx ARM+FPGA chip Zynq-7000 XC7Z010-1CLG400C for AC7010B,
Zynq-7000 XC7Z020-2CLG400I for AC7020B
DDR3
Two large-capacity 2Gbit (A total of 4Gbit) high-speed DDR3 SDRAMs
can be used as a cache for ZYNQ chip data or as a memory for the

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operating system
QSPI FLASH
A 256Mbit QSPI FLASH memory chip can be used as a Uboot file for
ZYNQ chips, storage of system files and user data;
Gigabit Ethernet Interface
1-channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices.
USB2.0 HOST Interface
1-channel USB HOST interface, to connect with external USB slave
devices, such as connecting a mouse, keyboard, USB flash drive etc.
The USB interface uses a flat USB interface (USB Type A).
USB OTG Interface
1-channel high-speed USB2.0 OTG interface for OTG communication
with PC or USB devices
USB Uart Interface
1-channel USB Uart interface for serial communication with PC or
external devices
LED Light
2 LEDs, 1 PS control LED, 1 PL control LED.
Key
1 reset button for CPU reset
Clock
An on-board 33.333Mhz active crystal oscillator provides a stable clock
source for the PS system, a 50MHz active crystal oscillator that
provides additional clocking for the PL logic
3-way 40-pin expansion port (0.1inch Spacing)
3-way 40-pin 0.1inch spacing expansion port for extending the IOs of
ZYNQ PL and PL parts, and can be connect to various ALINX modules
(binocular camera, TFT LCD screen, high-speed AD module, etc.)

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14-pin JTAG Interface (0.08inch Spacing)
Used to debug and download the ZYNQ system
Micro SD card holder
1-channel Micro SD card holder, to insert SD card for stores operating
system images and file systems.
Part 2: Dimensional structure
The size of the development board is 2.95 inch x 2.52 inch, and the PCB is
designed with an 8-layer board. There are 4 screw positioning holes around the
board for fixing the development board. The holes diameter of the positioning
hole is 0.09 inch, and the dxf structure diagram is provided in the documents.
Figure 2-1: FPGA Size Dimension
Part 3: Power Supply
The power input voltage of the development board is DC5V, The
schematic diagram of the power supply design on the AX7010 FPGA
development board is shown in Figure 3-1
Power input: The core board supply voltage is DC5V. When the core board
works alone, connect the USB cable to the USB port of the computer to supply
power to the core board. When working with carrier board together, the core
board can also be powered through the carrier board. If the

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AC7010B/AC7020B core board is powered by the carrier board, remove the 0Ω
resistor (R161) on the board. Please do not use other specifications of the
power supply to avoid damage to the core board. The power supply design on
the core board is as follows:
Figure 3-1: Power Supply Schematic
The development board is powered by +5V, and is converted into +1.5V,
+1.8V, +1.0V three-way power supply through three DC/DC power supply chip
TLV62130RGT. Each output current can be up to 3A. The 3.3V, VCCIO34 and
VCCI35 power supplies are generated by the three LDOs “SPX3819M5-3-3”,
the VCCIO34 is powered by the BANK34 of ZYNQ, and the VCCIO35 is
powered by the BANK35 of ZYNQ. By replacing with other LDO chips, BANK34
and BANK35IO adapts to different voltage standards. +1.5V Generates VTT
and VREF voltages required by DDR3 via TI's TPS51200

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The functions of each power distribution are shown in the following table
below:
Power Supply
Function
+1.0V
ZYNQ Core Voltage
+1.5V
DDR3, ZYNQ Bank502
+1.8V
ZYNQ auxiliary voltage, ZYNQ PLL, ZYNQ BANK501, VCCIO,
Ethernet, USB 2.0
+3.3V
ZYNQ VCCIO, Gigabit Ethernet, Serial Port, HDMI, RTC,
FLASH,EEPROM SD Card
VREF, VTT
DDR3
VCCIO34
ZYNQ Bank34
VCCIO35
ZYNQ Bank35
Because the power supply of the PS and PL parts of ZYNQ has the
power-on sequence requirements, in the circuit design, we have designed
according to the power requirements of ZYQN. The power-on sequence is
+1.0V->+1.8V->+1.5 V-> (3.3V, VCCIO34, VCCIO35). Figure 3-2 shows the
circuit design of the power supply:
In the PCB design, an 8-layer PCB is used, and a separate power supply
layer and GND layer are reserved, so that the power supply of the entire
development board has very good stability.
Part 4: ZYNQ Chip
The Core development board uses Xilinx's Zynq7000 series chip,
AC7010B chip model is XC7Z010-1CLG400C (AC7020B chip model is
XC7Z020-2CLG400I). The chip's PS system integrates two ARM CortexTM-A9
processors, AMBA® interconnects, internal memory, external memory
interfaces and peripherals. These peripherals mainly include USB bus interface,
Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus interface,
UART interface, GPIO etc. The PS can operate independently and start up at
power up or reset. Figure 4-1 detailed the Overall Block Diagram of the
ZYNQ7000 Chip.

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Figure 4-1: Overall Block Diagram of the ZYNQ7000 Chip
The main parameters of the PS system part are as follows:
ARM dual-core CortexA9-based application processor, ARM-v7
architecture, up to 800MHz
32KB level 1 instruction and data cache per CPU, 512KB level 2 cache
2 CPU shares
On-chip boot ROM and 256KB on-chip RAM
External storage interface, support 16/32 bit DDR2, DDR3 interface
Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,
SGMII interface
Two USB2.0 OTG interfaces, each supporting up to 12 nodes
Two CAN2.0B bus interfaces
Two SD card, SDIO, MMC compatible controllers
2 SPIs, 2 UARTs, 2 I2C interfaces
4 sets of 32bit GPIO, 54 (32+22) as PS system IO, 64 connected to PL
High bandwidth connection within PS and PS to PL

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The main parameters of the PL logic part are as follows:
Logic Cells: 28K
Look-up-tables (LUTs): 17600
Flip-flops: 35200
18x25MACCs：80
 Block RAM： 240KB
Two AD converters for on-chip voltage, temperature sensing and up
to 17 external differential input channels, 1MBPS
XC7Z010-1CLG400C (or XC7Z020-2CLG400I) chip, package is BGA, 400
pins, the pin pitch is 0.024 inch. Again, let's talk about the BGA pin. When we
use the BGA package chip, the pin name becomes in the form of letters +
numbers, such as E3, G3, etc., Therefore, when we look at the schematic, we
see the form of the letter + number, which represents the pin of the BGA.
Figure 4-2 detailed the XC7Z010 chip on the Core Board AC7010B.
Figure 4-2: The XC7Z010 chip on the Core Board AC7010B

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Part 4.1: JTAG Interface
First, let's talk about the JTAG debug interface (J14) of the
AC7010B/AC7020B core board. Users can debug and download the ZYNQ
program by connecting the ALINX Xilinx USB Cable downloader. Figure 4-3
shows the schematic part of the JTAG port, which involves four signals, TCK,
TMS, TDO, and TDI. These four signals are connected to the JTAG pins of
BANK0 of the Zynq7010 (Zynq7020) chip (TCK_0, TMS_0, TDO_0 and TDI_0)
Figure 4-3: The JTAG port schematic
The JTAG interface uses a 14-pin 0.06 inch standard connector, and
Figure 4-4 detailed JTAG interface on the core board.
Figure 4-4: The JTAG on the FPGA Core Board
Part 4.2: FPGA Power System
The power supply of the ZYNQ chip is divided into the PS system part and
the PL logic part, and the two parts of the power supply work independently.

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The power supply of the PS system part and the power supply of the PL logic
part have a power-on sequence. The abnormal power-on sequence may cause
the ARM system and the FPGA system to not work properly.
The power supply for the PS section is VCCPINT, VCCPAUX, VCCPLL,
and PS VCCO. VCCPINT is the PS core power supply pin, connected to 1.0V;
VCCPAUX is the PS system auxiliary power supply pin, connected to 1.8V;
VCCPLL is the PS internal clock PLL power supply pin, also connected to 1.8V;
PS VCCO is BANK voltage, Including VCCO_MIO0, VCCO_MIO1 and
VCCO_DDR, depending on the connected peripherals, the connected power
supply will be different. On the AC7010B/AC7020B FPGA Core Board,
VCC_MIO0 is connected to 3.3V, VCCO_MIO1 is connected to 1.8V, and
VCCO_DDR is connected to 1.5V. The PS system requires that the power-up
sequence be VCCPINT first, then VCCPAUX and VCCPLL, and finally PS
VCCO. The order of power outages is reversed.
The power supply for the PL section is VCCINT, VCCBRAM, VCCAUX and
VCCO. VCCPINT is the FPGA core power supply pin, connected to 1.0V;
VCCBRAM is the power supply pin of the FPGA Block RAM, connected to 1.0V;
VCCAUX is the FPGA auxiliary power supply pin, connected to 1.8V; VCCO is
the voltage of each BANK of PL, including BANK13, BANK34, BANK35, on the
AC7010B/AC7020B FPGA Core board, the voltage of BANK is connected to
3.3V. The voltage of BANK34 and BANK35 can be adjusted by replacing the
LDO chip. The PL system requires that the power-up sequence be VCCINT
first, then VCCBRAM, then VCCAUX, and finally VCCO. If VCCINT and
VCCBRAM have the same voltage, they can be powered up at the same time.
The order of power outages is reversed.
Part 4.3: ZYNQ boot configuration
The AC7010B/AC7020B FPGA Core board supports three boot modes.
The three boot modes are JTAG debug mode, QSPI FLASH and SD card boot

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mode. After the ZYNQ7000 chip is powered up, it will detect the level of the
responding MIO port to determine which startup mode. Users can select
different startup modes through the J13 jumper on the FPGA development
board. The J13 startup mode configuration is shown in Table 4-1.
J13
Jump cap position
Start mode
Connect the left two pins
SD Card
Connect the middle two pins
QSPI FLASH
Two pins connected to the right
JTAG
Table 4-1: J13 startup mode configuration
Part 5: Clock Configuration
The AC7010B/AC7020B core board provides an active clock for the PS
system, and the clock of the PL logic part can be generated by the PLL of the
PS part. Alternatively, the 50Mhz crystal oscillator can be used to provide a
clock source to achieve separate operation of the PS system and PL logic.
Part 5.1: PS system clock source
The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X1 crystal on the FPGA core board. The input of the clock is connected to
the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic
diagram is shown in Figure 5-1:
Figure 5-1: Active crystal oscillator to the PS section

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PS Clock Pin Assignment
Signal Name
ZYNQ Pin
PS_CLK_500
E7
Part 5.2: PL system clock source
The AC7010B/AC7020B FPGA core board, The PL system clock on the
AC7010B/AC7020B core board is powered by a 50MHz active crystal. This
50Mhz clock can be used to drive user logic in the FPGA. The schematic
diagram of the clock source is shown in Figure 5-3.
Figure 5-3: PL system clock source
PL Clock pin assignment:
Signal Name
ZYNQ Pin
500_CLK
U18
Part 6：ZYNQ Processor System (PS) peripherals
ZYNQ is composed of the PS part of the ARM system and the PL part of
the FPGA logic. Some peripherals on the FPGA core board are connected to
the IO of the PS, and some peripherals are connected to the IO of the PL. First
introduce the peripherals connected to the PS part.

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Part 6.1: QSPI Flash
The AC7010B/AC7020B FPGA core board is equipped with a 256MBit
Quad-SPI FLASH chip, model W25Q256, which uses the 3.3V CMOS voltage
standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a
boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, and other user
data files. The specific models and related parameters of QSPI FLASH are
shown in Table 6-1.
Position
Model
Capacity
Factory
U6
W25Q256BV
32M Byte
Winbond
Table 6-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure 6-1
shows the QSPI Flash in the schematic.
Figure 6-1: QSPI Flash Connection Diagram

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Figure 6-2: QSPI Flash on AC7010B/AC7020B FPGA Core
Board
Configure chip pin assignments:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
QSPI_SCK
PS_MIO6_500
A5
QSPI_CS
PS_MIO1_500
A7
QSPI_D0
PS_MIO2_500
B8
QSPI_D1
PS_MIO3_500
D6
QSPI_D2
PS_MIO4_500
B7
QSPI_D3
PS_MIO5_500
A6
Part 6.2: DDR3 DRAM
The AC7010B FPGA core board is equipped with two SKHynix 2Gbit
DDR3 chips (total 4Gbit), model H5TQ2G63FFR-RDC (compatible with

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MT41J128M16HA-125). The AC7020B FPGA core board is equipped with two
SKHynix 4Gbit DDR3 chips (total 8Gbit), model H5TQ4G63AFR-PBI
(compatible with MT41J256M16RE-125).
The bus width of DDR is 32bits in total, and the maximum operating speed
of DDR3 SDRAM is 533MHz (data rate 1066Mbps). The DDR3 memory
system is directly connected to the memory interface of the BANK 502 of the
ZYNQ Processing System (PS). The specific configuration of DDR3 SDRAM is
shown in Table 6-2.
Core Board
Bit Number
Chip Model
Capacity
Factory
AC7010B
U8,U9
H5TQ2G63FFR-RDC
128M x 16bit
SKhynix
AC7020B
U8,U9
H5TQ4G63AFR-PBI
256M x 16bit
SKhynix
Table 6-2: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.

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Figure 6-2: The Schematic Part of DDR3 DRAM
Figure 6-3: Two DDR3 DRAMs on the FPGA Core Board
DDR3 Pin Assignment:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
DDR3_DQS0_P
PS_DDR_DQS_P0_502
C2
DDR3_DQS0_N
PS_DDR_DQS_N0_502
B2
DDR3_DQS1_P
PS_DDR_DQS_P1_502
G2
DDR3_DQS1_N
PS_DDR_DQS_N1_502
F2
DDR3_DQS2_P
PS_DDR_DQS_P2_502
R2
DDR3_DQS2_N
PS_DDR_DQS_N2_502
T2
DDR3_DQS3_P
PS_DDR_DQS_P3_502
W5
DDR3_DQS4_N
PS_DDR_DQS_N3_502
W4
DDR3_DQ[0]
PS_DDR_DQ0_502
C3
DDR3_DQ [1]
PS_DDR_DQ1_502
B3
DDR3_DQ [2]
PS_DDR_DQ2_502
A2
DDR3_DQ [3]
PS_DDR_DQ3_502
A4
DDR3_DQ [4]
PS_DDR_DQ4_502
D3