Alinx AC7A035 User manual

ARTIX-7 FPGA
Core Board
AC7A035
System on Module

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Version Record
Version
Date
Release By
Description
Rev 1.0
2020-06-28
Rachel Zhou
First Release

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Table of Contents
Version Record..........................................................................................2
Part 1: AC7A035 Core Board Introduction.................................................4
Part 2: FPGA Chip.....................................................................................6
Part 3: Active Differential Crystal...............................................................8
Part 3.1: 200Mhz Active Differential clock...........................................8
Part 3.2: 125MHz Active Differential Crystal........................................9
Part 4: DDR3 DRAM................................................................................10
Part 5: QSPI Flash...................................................................................13
Part 6: LED Light on Core Board.............................................................15
Part 7: JTAG Interface..............................................................................17
Part 8: Power Interface on the Core Board .............................................18
Part 9: Board to Board Connectors pin assignment ................................18
Part 10: Power Supply.............................................................................26
Part 11: Size Dimension ..........................................................................29

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Part 1: AC7A035 Core Board Introduction
AC7A035 (core board model, the same below) FPGA core board, it is
based on XILINX's ARTIX-7 series 35T XC7A35T-2FGG484I. It is a
high-performance core board with high speed, high bandwidth and high
capacity. It is suitable for high-speed data communication, video image
processing, high-speed data acquisition etc.
This AC7A200 core board uses two pieces of MICRON's
MT41J256M16HA-125 DDR3 chip, each DDR has a capacity of 4Gbit; two
DDR chips are combined into a 32-bit data bus width, and the read/write data
bandwidth between FPGA and DDR3 is up to 25Gb; such a configuration can
meet the needs of high bandwidth data processing.
The AC7A035 core board expands 146 standard IO ports of 3.3V level, 15
standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX
differential signals. For users who need a lot of IO, this core board will be a
good choice. Moreover, the routing between the FPGA chip and the interface is
equal length and differential processing, and the core board size is only 2.36
inch *2.36 inch, which is very suitable for secondary development.

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Figure 1-1: AC7A035 Core Board (Front View)
Figure 1-2: AC7A035 Core Board (Rear View)

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Part 2: FPGA Chip
As mentioned above, the FPGA model we use is XC7A35T-2FGG484I,
which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the
temperature grade is industry grade. This model is a FGG484 package with
484 pins. Xilinx ARTIX-7 FPGAchip naming rules as below
Figure 2-1: The Specific Chip Model Definition of ARTIX-7 Series
Figure 2-2: FPGA chip on board
The main parameters of the FPGA chip XC7A35T are as follows
Name
Specific parameters
Logic Cells
33,280
Slices
5,200

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CLB flip-flops
41,600
Block RAM（kb）
1,800
DSP Slices
90
PCIe Gen2
1
XADC
1 XADC, 12bit, 1Mbps AD
GTP Transceiver
4 GTP, 6.6Gb/s max
Speed Grade
-1
Temperature Grade
Industrial
FPGA power supply system
Artix-7 FPGA power supplies are VCCINT, VCCBRAM, VCCAUX, VCCO, VMGTAVCC and
VMGTAVTT. VCCINT is the FPGAcore power supply pin, which needs to be connected
to 1.0V; VCCBRAM is the power supply pin of FPGA Block RAM, connect to 1.0V;
VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of
each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On
AC7A035 FPGA core board, BANK34 and BANK35 need to be connected to
DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK
is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can be
changed by replacing the LDO chip. VMGTAVCC is the supply voltage of the FPGA
internal GTP transceiver, connected to 1.0V; VMGTAVTT is the termination voltage
of the GTP transceiver, connected to 1.2V.
The Artix-7 FPGA system requires that the power-up sequence be power
by VCCINT, then VCCBRAM, then VCCAUX, and finally VCCO. If VCCINT and VCCBRAM have the
same voltage, they can be powered up at the same time. The order of power
outages is reversed. The power-up sequence of the GTP transceiver is VCCINT,
then VMGTAVCC, then VMGTAVTT. If VCCINT and VMGTAVCC have the same voltage, they
can be powered up at the same time. The power-off sequence is just the
opposite of the power-on sequence.

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Part 3: Active Differential Crystal
The AC7A035 core board is equipped with two Sitime active differential
crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main
clock for FPGAand used to generate DDR3 control clock; the other is 125MHz,
model is SiT9102 -125MHz, reference clock input for GTP transceivers.
Part 3.1: 200Mhz Active Differential clock
G1 in Figure 3-1 is the 200M active differential crystal that provides the
development board system clock source. The crystal output is connected to the
BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz
differential clock can be used to drive the user logic in the FPGA. Users can
configure the PLLs and DCMs inside the FPGA to generate clocks of different
frequencies.
Figure 3-1: 200Mhz Active Differential Crystal Schematic
Figure 3-2: 200Mhz Active Differential Crystal on the Core Board

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200Mhz Differential Clock Pin Assignment
Signal Name
FPGA PIN
SYS_CLK_P
R4
SYS_CLK_N
T4
Part 3.2: 125MHz Active Differential Crystal
G2 in Figure 3-3 is the 125MHz active differential crystal, which is the
reference input clock provided to the GTP module inside the FPGA. The crystal
output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and
MGTREFCLK0N (E6) of the FPGA.
Figure 3-3: 125MHz Active Differential Crystal Schematic
Figure 3-4: 125MHz Active Differential Crystal on the Core Board

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125MHz Differential Clock Pin Assignment
Net Name
FPGA PIN
MGT_CLK0_P
F6
MGT_CLK0_N
E6
Part 4: DDR3 DRAM
The FPGA core board AC7A035 is equipped with two Micron 4Gbit
(512MB) DDR3 chips (8Gbit in totally), model is MT41J256M16HA-125
(compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum
operating speed of 400MHz (data rate 800Mbps). The DDR3 memory system
is directly connected to the memory interface of the BANK 34 and BANK35 of
the FPGA. The specific configuration of DDR3 SDRAM is shown in Table 4-1.
Bit Number
Chip Model
Capacity
Factory
U5,U6
MT41J256M16HA-125
256M x 16bit
Micron
Table 4-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3. Figure 4-1 details
the hardware connection of DDR3 DRAM