Alpha Data ADM-PCIE-8V3 User manual

ADM-PCIE-8V3
User Manual
Document Revision: 1.9
8th June 017

ADM-PCIE-8V3 User Manual
© 017 Copyright Alpha Data Parallel Systems Ltd.
All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of this
publication may be reproduced, in any shape or form, without prior written consent from Alpha
Data Parallel Systems Ltd.
Head Office
Address: 4 West Silvermills Lane,
Edinburgh, EH3 5B , UK
Telephone: [phone]
Fax: [phone]
email: [email protected]
website: http://www.alpha-data.com
US Office
611 Corporate Circle Suite H
Golden, CO 80401
[phone]
[phone] - toll free
[email protected]
http://www.alpha-data.com
All trademarks are the property of their respective owners.

ADM-PCIE-8V3 User Manual
Table Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 1
PCB Information ..............................................................................................................................
2.1 Physical Specifications .................................................................................................................. 2
2.2 Chassis Requirements ................................................................................................................... 2
2.2.1 PCI E press ............................................................................................................................... 2
2.2.2 Mechanical Requirements ......................................................................................................... 2
2.2.3 Power Requirements ................................................................................................................. 2
2.3 Thermal Performance .................................................................................................................... 3
2.4 Optional Blower ............................................................................................................................. 3
3 Functional Description .................................................................................................................... 5
3.1 Overview ........................................................................................................................................ 5
3.1.1 Switches .................................................................................................................................... 6
3.1.2 LEDs .......................................................................................................................................... 7
3.2 Clocking ......................................................................................................................................... 8
3.2.1 PCIe Reference Clocks ............................................................................................................. 8
3.2.2 Fabric Clock ............................................................................................................................... 8
3.2.3 Programming Clock (EMCCLK) ................................................................................................. 8
3.2.4 QSFP28 ..................................................................................................................................... 9
3.2.5 FireFly ........................................................................................................................................ 9
3.2.6 DDR4 SDRAM Reference Clocks .............................................................................................. 9
3.3 PCI E press ................................................................................................................................. 11
3.4 DDR4 SDRAM ............................................................................................................................. 11
3.5 QSFP28 ....................................................................................................................................... 12
3.6 FireFly .......................................................................................................................................... 13
3.7 System Monitor ............................................................................................................................ 15
3.7.1 System Monitor Status LEDs ................................................................................................... 15
3.8 SMA Timing Input ........................................................................................................................ 16
3.9 USB Front Panel Interface ........................................................................................................... 17
3.10 Configuration ............................................................................................................................... 17
3.10.1 Configuration From Flash Memory .......................................................................................... 17
3.10.1.1 Custom Flash Write Interface .............................................................................................. 18
3.10.1.2 Building and Programming Configuration Images ............................................................... 18
3.10.2 Configuration via JTAG ............................................................................................................ 18
3.11 GPIO Option ................................................................................................................................ 18
3.11.1 Direct Connect FPGA Signals .................................................................................................. 19
3.11.2 Low Speed Serial IO ................................................................................................................ 19
3.12 User EEPROM ............................................................................................................................. 19
Appendix A Complete Pinout Table .................................................................................................................. 1
List of Tables
Table 1 Mechanical imensions ..................................................................................................................... 2
Table 2 Available Power By Rail ..................................................................................................................... 2
Table 3 SW1 Switch Functions ....................................................................................................................... 6
Table 4 LE etails ........................................................................................................................................ 7
Table 5 PCIe Reference Clocks ..................................................................................................................... 8
Table 6 Fabric Clock ....................................................................................................................................... 8

ADM-PCIE-8V3 User Manual
Table 7 EMCCLK ............................................................................................................................................ 9
Table 8 QSFP28 Reference Clocks ................................................................................................................ 9
Table 9 QSFP28 Jitter Attenuated Reference Clocks ..................................................................................... 9
Table 10 FireFly Reference Clocks .................................................................................................................. 9
Table 11 Memory Reference Clocks .............................................................................................................. 10
Table 12 QSFP28 Part Numbers .................................................................................................................... 12
Table 13 FireFly Part Numbers ....................................................................................................................... 14
Table 14 Voltage, Current, and Temperature Monitors ................................................................................... 15
Table 15 Status LE efinitions ..................................................................................................................... 16
Table 16 Complete Pinout Table ..................................................................................................................... 21
List of Figures
Figure 1 A M-PCIE-8V3 Product Photo .......................................................................................................... 1
Figure 2 Thermal Performance ........................................................................................................................ 3
Figure 3 Optional Blower ................................................................................................................................. 4
Figure 4 A M-PCIE-8V3 Block iagram ......................................................................................................... 5
Figure 5 Switches ............................................................................................................................................ 6
Figure 6 LE s .................................................................................................................................................. 7
Figure 7 Clock Topology .................................................................................................................................. 8
Figure 8 QSFP Locations ............................................................................................................................... 12
Figure 9 FireFly Locations ............................................................................................................................. 13
Figure 10 FireFly Breakout to Front Panel ....................................................................................................... 13
Figure 11 Timing Input Schematic ................................................................................................................... 16
Figure 12 Flash Address Map .......................................................................................................................... 17
Figure 13 GPIO Connector .............................................................................................................................. 19

ADM-PCIE-8V3 User Manual
1 Introduction
The A M-PCIE-8V3 is a high-performance reconfigurable computing card intended for ata Center applications,
featuring a Xilinx Virtex UltraScale FPGA.
Figure 1 : ADM-PCIE-8V3 Product Photo
1.1 Key Features
Key Features
• PCIe Gen1/2/3 x1/2/4/8/16 capable (x16 requires bifurcation)
• Half-length, low-profile x16 PCIe form factor
• Two banks of R4 S RAM 72 bit wide memory (ECC), 16GB (8GB per bank) default rated at 2400MT/s,
32GB option rated at 1866MT/s.
• Two QSFP28/zQSFP+ sites capable of data rates up to 28 Gbps per channel (112 Gbps per cage)
• Two Samtec FireFly sites capable of data rates up to 28 Gbps per channel (112 Gbps per module). Can be
routed to front panel or adjacent card slots.
• Optional SMA/U.FL timing input
• Front Panel JTAG Access via USB port
• FPGA configurable over USB/JTAG and BPI configuration flash
• XCVU095-2FFVC1517E FPGA
• Voltage, current, and temperature monitoring
1. Order Code
A M-PCIE-8V3/VU095-2E (m)(q)(f)(g)
See http://www.alpha-data.com/pdfs/adm-pcie-8v3.pdf for complete ordering options.
Page 1Introduction
ad-ug-1308_v1_9.pdf

ADM-PCIE-8V3 User Manual
PCB Information
.1 Physical Specifications
The A M-PCIE-8V3 complies with PCI Express CEM revision 3.0.
escription Measure
Total y 68.9 mm
Total x (Inc. QSFP Cages) 174 mm
Total z 17.45 mm
Weight 230 grams
Table 1 : Mechanical Dimensions
. Chassis Requirements
. .1 PCI Express
The A M-PCIE-8V3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes, using the Xilinx Integrated Block for PCI
Express.
. . Mechanical Requirements
A 16-lane physical PCIe slot is required for mechanical compatibility.
Each A M-PCIE-8V3 is shipped with a full height PCIe card bracket installed by default. A half-height bracket is
shipped along with the product and can be easily changed out with a philips screw driver. If the application
requires a low-profile bracket and the order quantity is high, contact [email protected] to get the correct
bracket fitted before shipping.
. .3 Power Requirements
The PCIe Specification permits a standard low-profile, half-length PCIe card to dissipate up to 25 W of power,
drawn from the PCIe slot. The A M-PCIE-8V3 may consume more than 25 W of power for larger user FPGA
designs. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a power estimator tool
available from Alpha ata. Please contact [email protected] to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.95 VCC_INT + VCCINT_IO + VCC_BRAM 36A
1.8 VCCAUX + VCCAUX_IO + VCC_BRAM + VCCO_1.8V 6A
3.3 VCCO_3.3V 6A
1.2 VCCO_1.2V 9A
1.8 MGTVCCAUX 1A
1.0 MGTAVCC 9A
1.2 MGTAVTT 15A
Table : Available Power By Rail
Page PCB Information
ad-ug-1308_v1_9.pdf

ADM-PCIE-8V3 User Manual
.3 Thermal Performance
The A M-PCIE-8V3 comes with a heat sink to reduce the heat of the FPGA which is typically the hottest point on
the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will clear the
FPGA design to ensure the card does not overheat. To calculate the FPGA die temperature, take your application
power and multiply by Theta JA from the chart below, and add your systems internal ambient temperature. If you
are using the fan provided with the board, you will find Theta JA is approximately 1.27 degC/W for the board in
still air.
The power dissipation can be estimated by using the Alpha ata power estimator in conjuction with the Xilinx
Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. ownload
the UltraScale tool and set the evice to Virtex UltraScale, VU095, FFVC1516, -2, Extended. Set the ambient
temperature to your system ambient and select User Override for the Effective Theta JA and enter the figure
associated with your system LFM in the blank field. Proceed to enter all applicable design elements and
utilization in the following spreadsheet tabs. Next aquire the 8V3 power estimator from Alpha ata by contacting
[email protected]. You will then plug in the FPGA power figures along with R4 and QSFP/Firefly
usage to get an estimated board level power dissipation.
The graph below shows Theta JA of the board with two 3.5 watt QSFP loopback connectors inserted.
Figure : Thermal Performance
.4 Optional Blower
Because it is possible for generic PC chassis to not provide sufficient airflow to cool the FPGA, the
A M-PCIE-8V3 is shipped with an uninstalled blower. The blower is optional and can be easily installed with a
Philips screw driver at the discretion of the user. Ensure the opening is facing the heatsink fins. The blower
hangs off the back of the PCB outside of the PCIe card envelope. After screwing the blower into the heatsink,
plug in the small power connector into the connector in the corner of the board.
Page 3PCB Information
ad-ug-1308_v1_9.pdf

ADM-PCIE-8V3 User Manual
Figure 3 : Optional Blower
Page 4 PCB Information
ad-ug-1308_v1_9.pdf

ADM-PCIE-8V3 User Manual
3 Functional Description
3.1 Overview
The A M-PCIE-8V3 is a versatile reconfigurable computing platform with a Virtex UltraScale VU095-2E FPGA,
two Gen3x8 PCIe interface, two banks of R4 both 72 bits wide (for 64 bits with 8 bits ECC), two QSFP28
cages capable of 8x 28G or 2x 112G Serial IO of any Xilinx supported standard (Ethernet, SRIO, Infiniband,
etc.), two Samtec FireFly connectors also capable of 28G/channel, a U.FL input for a timing synchronization
input, a 12 pin header for general purpose use (clocking, control pins, debug, etc.) and low speed serial
communications, and a robust system monitor.
XCVU095-2
FFVC1517E
(0,4) (5,7) (8,11) (12,15)
x16 PCIe Gen3 Edge
QSFP28 C ge
(4x28 Gbps m x)
QSFP28 C ge
(4x28 Gbps m x) DDR4 B nk 1
DDR4-2400/1866, 8/16GB
DDR4 B nk 0
DDR4-2400/1866, 8/16GB
System
Monitor
MGT
MGT HPIO
HPIO
HRIO
BPI
Config
x72
x72
MGTMGT MGT
HRIO
USB JTAG 0
Auxili ry IO
(gpio, timing,
seri l coms, etc)
MGT
FireFly
(4x28Gbps m x)
MGT
FireFly
(4x28Gbps m x)
MGT
MAC ID
EEPROM
Figure 4 : ADM-PCIE-8V3 Block Diagram
Page 5Functional Description
ad-ug-1308_v1_9.pdf

ADM-PCIE-8V3 User Manual
3.1.1 Switches
The A M-PCIE-8V3 has a quad IP switch SW1, located on the rear side of the board. The function of each
switch in SW1 is detailed below:
Figure 5 : Switches
Switch Factory
efault Function OFF State ON State
SW1-1 OFF User
Switch Pin AV27 = '1' Pin AV27 = '0'
SW1-2 OFF Flash
Lockdown Flash block Lockdown enabled Flash block Lockdown disabled
SW1-3 OFF Service
Mode Regular Operation Firmware update service mode
SW1-4 OFF PCIe Edge
JTAG JTAG to FPGA from USB JTAG to FPGA from PCIe Edge
Table 3 : SW1 Switch Functions
Use IO Standard "LVCMOS18" when constraining the user switch pin.
Page 6 Functional Description
ad-ug-1308_v1_9.pdf