Alpha Data ADM-PCIE-8V3 User manual

ADM-PCIE-8V3
User Manual
Document Revision: 1.9
8th June 017

ADM-PCIE-8V3 User Manual
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ADM-PCIE-8V3 User Manual
Table Of Contents
1 Introduction ...................................................................................................................................... 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 1
PCB Information ..............................................................................................................................
2.1 Physical Specifications .................................................................................................................. 2
2.2 Chassis Requirements ................................................................................................................... 2
2.2.1 PCI E press ............................................................................................................................... 2
2.2.2 Mechanical Requirements ......................................................................................................... 2
2.2.3 Power Requirements ................................................................................................................. 2
2.3 Thermal Performance .................................................................................................................... 3
2.4 Optional Blower ............................................................................................................................. 3
3 Functional Description .................................................................................................................... 5
3.1 Overview ........................................................................................................................................ 5
3.1.1 Switches .................................................................................................................................... 6
3.1.2 LEDs .......................................................................................................................................... 7
3.2 Clocking ......................................................................................................................................... 8
3.2.1 PCIe Reference Clocks ............................................................................................................. 8
3.2.2 Fabric Clock ............................................................................................................................... 8
3.2.3 Programming Clock (EMCCLK) ................................................................................................. 8
3.2.4 QSFP28 ..................................................................................................................................... 9
3.2.5 FireFly ........................................................................................................................................ 9
3.2.6 DDR4 SDRAM Reference Clocks .............................................................................................. 9
3.3 PCI E press ................................................................................................................................. 11
3.4 DDR4 SDRAM ............................................................................................................................. 11
3.5 QSFP28 ....................................................................................................................................... 12
3.6 FireFly .......................................................................................................................................... 13
3.7 System Monitor ............................................................................................................................ 15
3.7.1 System Monitor Status LEDs ................................................................................................... 15
3.8 SMA Timing Input ........................................................................................................................ 16
3.9 USB Front Panel Interface ........................................................................................................... 17
3.10 Configuration ............................................................................................................................... 17
3.10.1 Configuration From Flash Memory .......................................................................................... 17
3.10.1.1 Custom Flash Write Interface .............................................................................................. 18
3.10.1.2 Building and Programming Configuration Images ............................................................... 18
3.10.2 Configuration via JTAG ............................................................................................................ 18
3.11 GPIO Option ................................................................................................................................ 18
3.11.1 Direct Connect FPGA Signals .................................................................................................. 19
3.11.2 Low Speed Serial IO ................................................................................................................ 19
3.12 User EEPROM ............................................................................................................................. 19
Appendix A Complete Pinout Table .................................................................................................................. 1
List of Tables
Table 1 Mechanical imensions ..................................................................................................................... 2
Table 2 Available Power By Rail ..................................................................................................................... 2
Table 3 SW1 Switch Functions ....................................................................................................................... 6
Table 4 LE etails ........................................................................................................................................ 7
Table 5 PCIe Reference Clocks ..................................................................................................................... 8
Table 6 Fabric Clock ....................................................................................................................................... 8

ADM-PCIE-8V3 User Manual
Table 7 EMCCLK ............................................................................................................................................ 9
Table 8 QSFP28 Reference Clocks ................................................................................................................ 9
Table 9 QSFP28 Jitter Attenuated Reference Clocks ..................................................................................... 9
Table 10 FireFly Reference Clocks .................................................................................................................. 9
Table 11 Memory Reference Clocks .............................................................................................................. 10
Table 12 QSFP28 Part Numbers .................................................................................................................... 12
Table 13 FireFly Part Numbers ....................................................................................................................... 14
Table 14 Voltage, Current, and Temperature Monitors ................................................................................... 15
Table 15 Status LE efinitions ..................................................................................................................... 16
Table 16 Complete Pinout Table ..................................................................................................................... 21
List of Figures
Figure 1 A M-PCIE-8V3 Product Photo .......................................................................................................... 1
Figure 2 Thermal Performance ........................................................................................................................ 3
Figure 3 Optional Blower ................................................................................................................................. 4
Figure 4 A M-PCIE-8V3 Block iagram ......................................................................................................... 5
Figure 5 Switches ............................................................................................................................................ 6
Figure 6 LE s .................................................................................................................................................. 7
Figure 7 Clock Topology .................................................................................................................................. 8
Figure 8 QSFP Locations ............................................................................................................................... 12
Figure 9 FireFly Locations ............................................................................................................................. 13
Figure 10 FireFly Breakout to Front Panel ....................................................................................................... 13
Figure 11 Timing Input Schematic ................................................................................................................... 16
Figure 12 Flash Address Map .......................................................................................................................... 17
Figure 13 GPIO Connector .............................................................................................................................. 19

ADM-PCIE-8V3 User Manual
1 Introduction
The A M-PCIE-8V3 is a high-performance reconfigurable computing card intended for ata Center applications,
featuring a Xilinx Virtex UltraScale FPGA.
Figure 1 : ADM-PCIE-8V3 Product Photo
1.1 Key Features
Key Features
• PCIe Gen1/2/3 x1/2/4/8/16 capable (x16 requires bifurcation)
• Half-length, low-profile x16 PCIe form factor
• Two banks of R4 S RAM 72 bit wide memory (ECC), 16GB (8GB per bank) default rated at 2400MT/s,
32GB option rated at 1866MT/s.
• Two QSFP28/zQSFP+ sites capable of data rates up to 28 Gbps per channel (112 Gbps per cage)
• Two Samtec FireFly sites capable of data rates up to 28 Gbps per channel (112 Gbps per module). Can be
routed to front panel or adjacent card slots.
• Optional SMA/U.FL timing input
• Front Panel JTAG Access via USB port
• FPGA configurable over USB/JTAG and BPI configuration flash
• XCVU095-2FFVC1517E FPGA
• Voltage, current, and temperature monitoring
1. Order Code
A M-PCIE-8V3/VU095-2E (m)(q)(f)(g)
See http://www.alpha-data.com/pdfs/adm-pcie-8v3.pdf for complete ordering options.
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PCB Information
.1 Physical Specifications
The A M-PCIE-8V3 complies with PCI Express CEM revision 3.0.
escription Measure
Total y 68.9 mm
Total x (Inc. QSFP Cages) 174 mm
Total z 17.45 mm
Weight 230 grams
Table 1 : Mechanical Dimensions
. Chassis Requirements
. .1 PCI Express
The A M-PCIE-8V3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes, using the Xilinx Integrated Block for PCI
Express.
. . Mechanical Requirements
A 16-lane physical PCIe slot is required for mechanical compatibility.
Each A M-PCIE-8V3 is shipped with a full height PCIe card bracket installed by default. A half-height bracket is
shipped along with the product and can be easily changed out with a philips screw driver. If the application
requires a low-profile bracket and the order quantity is high, contact [email protected] to get the correct
bracket fitted before shipping.
. .3 Power Requirements
The PCIe Specification permits a standard low-profile, half-length PCIe card to dissipate up to 25 W of power,
drawn from the PCIe slot. The A M-PCIE-8V3 may consume more than 25 W of power for larger user FPGA
designs. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a power estimator tool
available from Alpha ata. Please contact [email protected] to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.95 VCC_INT + VCCINT_IO + VCC_BRAM 36A
1.8 VCCAUX + VCCAUX_IO + VCC_BRAM + VCCO_1.8V 6A
3.3 VCCO_3.3V 6A
1.2 VCCO_1.2V 9A
1.8 MGTVCCAUX 1A
1.0 MGTAVCC 9A
1.2 MGTAVTT 15A
Table : Available Power By Rail
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ADM-PCIE-8V3 User Manual
.3 Thermal Performance
The A M-PCIE-8V3 comes with a heat sink to reduce the heat of the FPGA which is typically the hottest point on
the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will clear the
FPGA design to ensure the card does not overheat. To calculate the FPGA die temperature, take your application
power and multiply by Theta JA from the chart below, and add your systems internal ambient temperature. If you
are using the fan provided with the board, you will find Theta JA is approximately 1.27 degC/W for the board in
still air.
The power dissipation can be estimated by using the Alpha ata power estimator in conjuction with the Xilinx
Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. ownload
the UltraScale tool and set the evice to Virtex UltraScale, VU095, FFVC1516, -2, Extended. Set the ambient
temperature to your system ambient and select User Override for the Effective Theta JA and enter the figure
associated with your system LFM in the blank field. Proceed to enter all applicable design elements and
utilization in the following spreadsheet tabs. Next aquire the 8V3 power estimator from Alpha ata by contacting
[email protected]. You will then plug in the FPGA power figures along with R4 and QSFP/Firefly
usage to get an estimated board level power dissipation.
The graph below shows Theta JA of the board with two 3.5 watt QSFP loopback connectors inserted.
Figure : Thermal Performance
.4 Optional Blower
Because it is possible for generic PC chassis to not provide sufficient airflow to cool the FPGA, the
A M-PCIE-8V3 is shipped with an uninstalled blower. The blower is optional and can be easily installed with a
Philips screw driver at the discretion of the user. Ensure the opening is facing the heatsink fins. The blower
hangs off the back of the PCB outside of the PCIe card envelope. After screwing the blower into the heatsink,
plug in the small power connector into the connector in the corner of the board.
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Figure 3 : Optional Blower
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ADM-PCIE-8V3 User Manual
3 Functional Description
3.1 Overview
The A M-PCIE-8V3 is a versatile reconfigurable computing platform with a Virtex UltraScale VU095-2E FPGA,
two Gen3x8 PCIe interface, two banks of R4 both 72 bits wide (for 64 bits with 8 bits ECC), two QSFP28
cages capable of 8x 28G or 2x 112G Serial IO of any Xilinx supported standard (Ethernet, SRIO, Infiniband,
etc.), two Samtec FireFly connectors also capable of 28G/channel, a U.FL input for a timing synchronization
input, a 12 pin header for general purpose use (clocking, control pins, debug, etc.) and low speed serial
communications, and a robust system monitor.
XCVU095-2
FFVC1517E
(0,4) (5,7) (8,11) (12,15)
x16 PCIe Gen3 Edge
QSFP28 C ge
(4x28 Gbps m x)
QSFP28 C ge
(4x28 Gbps m x) DDR4 B nk 1
DDR4-2400/1866, 8/16GB
DDR4 B nk 0
DDR4-2400/1866, 8/16GB
System
Monitor
MGT
MGT HPIO
HPIO
HRIO
BPI
Config
x72
x72
MGTMGT MGT
HRIO
USB JTAG 0
Auxili ry IO
(gpio, timing,
seri l coms, etc)
MGT
FireFly
(4x28Gbps m x)
MGT
FireFly
(4x28Gbps m x)
MGT
MAC ID
EEPROM
Figure 4 : ADM-PCIE-8V3 Block Diagram
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ADM-PCIE-8V3 User Manual
3.1.1 Switches
The A M-PCIE-8V3 has a quad IP switch SW1, located on the rear side of the board. The function of each
switch in SW1 is detailed below:
Figure 5 : Switches
Switch Factory
efault Function OFF State ON State
SW1-1 OFF User
Switch Pin AV27 = '1' Pin AV27 = '0'
SW1-2 OFF Flash
Lockdown Flash block Lockdown enabled Flash block Lockdown disabled
SW1-3 OFF Service
Mode Regular Operation Firmware update service mode
SW1-4 OFF PCIe Edge
JTAG JTAG to FPGA from USB JTAG to FPGA from PCIe Edge
Table 3 : SW1 Switch Functions
Use IO Standard "LVCMOS18" when constraining the user switch pin.
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3.1. LEDs
There are 6 LE s on the A M-PCIE-8V3, 3 of which are general purpose and whose meaning can be defined by
the user. The other four have fixed functions described below:
USR_LED_G0
D2 D4 D5 D6 D7 D8
USER_LED_G1 USR_LED_R DONE STAT_0 STAT_1
Figure 6 : LEDs
Comp.
Ref. Function ON State OFF State
4 ONE FPGA is configured FPGA is not configured
8 USER_LE _G0 User defined '0' pin AT27 User defined '1' pin AT27
2 USER_LE _G1 User defined '0' pin AU27 User defined '1' pin AU27
7 USER_LE _R User defined '0' pin AU23 User defined '1' pin AU23
5 Status 0 See Status LE efinitions
6 Status 1 See Status LE efinitions
Table 4 : LED Details
Use IO Standard "LVCMOS18" when driving the user LE pins.
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3. Clocking
The A M-PCIE-8V3 provides reference clocks for the R4 S RAM banks and the I/O interfaces available to
the user. After a clock is programmed to a certain frequency, that frequency will become the default on power-up.
Any clock out of an Si5338 Clock Synthesizer is re-configurable over I2C. This allows the user to configure
almost any arbitrary clock frequencies during application run time. Please see the Alpha ata API functions for
examples of how this is done.
Note: use "set_property BITSTREAM.CONFIG.UNUSE PIN {Pullnone} [current_design]" to ensure the user
design does not interfere with the I2C interface to the reprogramable clock generator.
NB6L11S
Fanout QSFP28 161.1328125MHz Factory Default (M TREFCLK0_129)
QSFP28 161.1328125MHz Factory Default (M TREFCLK0_128)
FABRIC_CLK 300MHz (IO Bank 94)
PCIe Ref Clock (M TREFCLK0_226)
Card Edge PCIe Ref Clock (100MHz)
25MHz
30ppm
Source
Si5338
Clock
Synth
NB6L11S
Fanout FireFly 161.1328125MHz Factory Default (M TREFCLK0_126)
FireFly 161.1328125MHz Factory Default (M TREFCLK0_125)
NB6L11S
Fanout
Memory Interface Clock 300Mhz (IO Bank 44)
Memory Interface Clock 300Mhz (IO Bank 94)
Figure 7 : Clock Topology
3. .1 PCIe Reference Clocks
The 16 MGT lanes connected to the PCIe card edge use MGT tiles 224 through 227 and use the system 100
MHz clock (PCIE_REFCLK).
Signal Target FPGA Input I/O Standard "P" pin "N" pin
PCIE_REFCLK MGTREFCLK0_226 HCSL AA7 AA6
Table 5 : PCIe Reference Clocks
3. . Fabric Clock
The design offers a fabric clock called FABRIC_CLK which is permanently fixed at 300 MHz. This clock is
intended to be used for I ELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC)
pin.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
FABRIC_CLK IO_L12P_T1U_GC_94 IFF_HSTL_I_18 AP26 AP27
Table 6 : Fabric Clock
3. .3 Programming Clock (EMCCLK)
An 100MHz clock is fed into the EMCCLK pin to drive the BPI flash device during configuration of the FPGA.
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Signal Target FPGA Input I/O Standard pin
REFCLK100M IO_L24P_T3U_N10_EMCCLK_65 LVCMOS18 AJ28
Table 7 : EMCCLK
3. .4 QSFP 8
The QSFP28 cages are located in MGT tiles 129 and 128 and use a 161.1328125MHz default reference clock.
Note that this clock frequency can be changed to any arbitrary clock frequency up to 400MHz by re-programing
the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha ata API or
over USB with the appropriate Alpha ata Software tools.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
GTY_CLK_0B MGTREFCLK0_129 LV S N33 N34
GTY_CLK_0C MGTREFCLK0_128 LV S U33 U34
Table 8 : QSFP 8 Reference Clocks
The QSFP28 cages are also located such that they can be clocked from a Si5328 jitter attenuator clock
multiplier. If jitter attenuation is required please see the reference documentation for the Si5328. https://
www.silabs.com/Support%20 ocuments/Technical ocs/Si5328.pdf
The Si5328 is configured with a 114.285MHz oscilator on XA and XB, S A is at FPGA pin L29 (1.8V), SCL is at
FPGA pin L30 (1.8V) with external pull-ups included.
The Si5328 input clock comes from FPGA pins M29 and M30, and includes 100 Ohm AC coupled termination on
the 1.8V FPGA bank.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
SI5328_REFCLK_OUT0 MGTREFCLK1_129 LV S L33 L34
SI5328_REFCLK_OUT1 MGTREFCLK1_128 LV S R33 R34
Table 9 : QSFP 8 Jitter Attenuated Reference Clocks
3. .5 FireFly
The two FireFly sites are located in MGT tile 125 and 126 and use a 161.1328125MHz default reference clock.
Note that this clock frequency can be changed to any arbitrary clock frequency up to 400MHz by re-programing
the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the Alpha ata API or
over USB with the appropriate Alpha ata Software tools.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
GTY_CLK_1B MGTREFCLK0_126 LV S AE33 AE34
GTY_CLK_1C MGTREFCLK0_125 LV S AJ33 AJ34
Table 10 : FireFly Reference Clocks
3. .6 DDR4 SDRAM Reference Clocks
The two banks of R4 S RAM memory each require a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. The reference clocks for these interfaces are detailed below:
Both clocks are 300MHz by default.
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Signal Target FPGA Input I/O Standard "P" pin "N" pin
MEM_CLK_0 IO_L13_T2L_GC_44 LV S G31 G32
MEM_CLK_1 IO_L11_T2L_GC_94 IFF_HSTL_I_18 AN25 AN26
Table 11 : Memory Reference Clocks
IFF_TERM_A V = TRUE is required for LV S termination
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3.3 PCI Express
The A M-PCIE-8V3 is capable of PCIe Gen 1/2/3 with 1/2/4/8/16 lanes (where 16-lanes requires a two
bifurcated 8-lane interfaces). The FPGA drives these lanes directly using the Integrated PCI Express block from
Xilinx. Negotiation of PCIe link speed and number of lanes used is generally automatic and does not require user
intervention.
PCI Express reset (PERST#) connected to the FPGA at both pins AJ31 and AP33.
The other pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout
Table
Note:
ifferent motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha ata recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG239 for more details).
3.4 DDR4 SDRAM
Two banks of R4 S RAM memory are soldered down to the board. While the factory default is 8GB/per bank,
16GB/bank is also supported through a built variant. Please see Order Code for all order options. The memory
interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is 2400 MT/s for 16GB total and
1688MT/s with 32GB total.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) tool. An example memory
excersizer project is included in the A M-PCIE-8V3 S K. All constraint information is included in Complete
Pinout Table. Alpha ata has also provided a custom csv timing file for use with Xilinx MIG. This can be
downloaded from the A M-PCIE-8V3 product page.
8Gb components used (standard) are Micron MT40A1G8PM-083E
16Gb components used (build variant) are Micron MT40A2G8PM-093E
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3.5 QSFP 8
Two QSFP28 cages are available at the front panel. Both cages are capable of housing either active optical or
passive copper QSFP28 or QSFP compatible components. The communication interface can run at up to
28Gbps per channel. There are eight channels between the two QSFP28 cages (total maximum bandwidth of
224Gbps). These cages are ideally suited for 8x 25G or 2x 100G Ethernet or any other protocol supported by the
Xilinx GTY Transceivers. Please see Xilinx User Guide UG578 for more details on the capabilities of the
transceivers.
Both QSFP28 cages have control signals connected to the FPGA. Their connectivity is detailed in the Complete
Pinout Table at the end of this document. The notation used in the pin assignments is QSFP0 and QSFP1 with
locations clarified in the diagram below.
Use the QSFP*_SEL_1V8_L in conjunction with the OPTICAL_SCL_1V8 and OPTICAL_S A_1V8 pins as
detailed in Complete Pinout Table to communicate with QSFP28 register space.
Note:
The LP_MO E (Low Power Mode) to each QSFP28 cage is pulled up by default. For many high performance
optical transcievers to operate, this pin must be driven low by the FPGA.
Figure 8 : QSFP Locations
The order options for the A M-PCIE-8V3 include an option to fit the QSFP28 optical transceivers. The table
below shows the part number for the transceivers fitted with each option.
Order Code escription Part Number Manufacturer
Q10 40G (4x10) QSFP Optical Transceiver FTL410QE2C Finisar
Q14 56G (4x14) QSFP Optical Transceiver FTL414QB2C Finisar
Q25 100G (4x25) QSFP28 Optical Transceiver FTLC9551REPM Finisar
Table 1 : QSFP 8 Part Numbers
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3.6 FireFly
Two FireFly receptacles along the top of the board allow for additional 100G breakouts (with MPO) to the front
panel or for internal chassis ring connections. The FireFly connections have the same capabilities as the
QSFP28 cages. The A M-PCIE-8V3 only supports optical FireFly modules. More information on FireFly can be
found at https://www.samtec.com/optics/optical-cable/mid-board/firefly
Both FireFly sites have control signals connected to the FPGA. Their connectivity is detailed in the Complete
Pinout Table at the end of this document. The notation used in the pin assignments is FireFly0 and FireFly1 with
locations clarified in the diagram below.
Use the FIREFLY*_SEL_1V8_L in conjunction with the OPTICAL_SCL_1V8 and OPTICAL_S A_1V8 pins as
detailed in Complete Pinout Table to communicate with QSFP28 register space.
Figure 9 : FireFly Locations
The FireFly modules are broken out to the front panel as shown in the image below. The Samtec FireFly optical
module ties the PCB to the front panel where an industry standard MPO coupler is used for attachment to
external cabling.
Figure 10 : FireFly Breakout to Front Panel
The order options for the A M-PCIE-8V3 include an option to fit the FireFly optical transceivers. The table below
shows the part number for the transceivers fitted with each option.
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Order Code escription Part Number Manufacturer
F14 56G/40G (4x14/10) FireFly Optical Transceiver ECUO-B04-14-017-0-3-1-1-01 Samtec
F28 28G/25G (4x28/25) FireFly Optical Transceiver ECUO-B04-28-017-0-3-1-1-01 Samtec
Table 13 : FireFly Part Numbers
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3.7 System Monitor
The A M-PCIE-8V3 has the ability to monitor temperature, voltage, and current of the system to check on the
operation of the board. The monitoring is implemented using an Atmel AVR microcontroller.
If the core FPGA temperature exceeds 100 degrees Celsius, the FPGA will be cleared to prevent damage to the
card. This function was implemented on sn172 and newer. Older cards should be protected using the FPGA over
tempeature shutdown constraint.
Control algorithms within the microcontroller automatically check line voltages and on board temperatures and
shares makes the information available to the FPGA over a dedicated serial interface built into the Alpha ata
reference design package (sold separately). The information can also be accessed directly from the
microcontroller over the USB interface on the front panel or via the IPMI interface available at the PCIe card
edge.
Monitors Index Purpose/ escription
ETC ETC Elapsed time counter (seconds)
EC EC Event counter (power cycles)
12.0V A C00 Board Input Supply
3.3V A C01 Board Input Supply
3.3V A C02 Board Input Auxilary Power Supply
3.3V PSU0OK Internal logic voltage
2.5V A C03 Clock and RAM Voltage Supply
1.8V PSU0OK FPGA IO Voltage (VCCO)
1.8V A C04 Transceiver Power (AVCC_AUX)
1.2V A C05 R4 S RAM and FPGA memory I/O
1.2V A C06 Transceiver Power (AVTT)
0.9V A C07 Transceiver Power (AVCC)
0.85V A C08 FPGA Core Supply (VccINT)
0.6V A C09 R4 Termination Voltage
12V_I A C10 12V input current in amps
3.3V_I A C11 3.3V input current in amps
1.8V_MGT_I A C12 1.8V MGT supply current in amps
2.5V_ IG_I A C13 2.5V supply current in amps
uC_Temp TMP00 FPGA on-die temperature
Board0_Temp TMP01 Board temperature near front panel
Board1_Temp TMP02 Board temperature near back top corner
FPGA_Temp TMP03 FPGA on-die temperature
Table 14 : Voltage, Current, and Temperature Monitors
3.7.1 System Monitor Status LEDs
LE s 6 (Red) and 5 (Green) indicate the card health status.
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LEDs Status
Green Running and no alarms
Green + Red Standby (Powered off)
Flashing Green + Flashing Red
(together) Attention - critical alarm active
Flashing Green + Flashing Red
(alternating) Service Mode
Flashing Green + Red Attention - alarm active
Red Missing application firmware or
invalid firmware
Flashing Red FPGA configuration cleared to
protect board
Table 15 : Status LED Definitions
3.8 SMA Timing Input
All cards are fitted with a U.FL connector that can be utilized as a timing input. This connector can be accessed
with a U.FL cable internal to the chassis, or cabled to an SMA or similar connector at the frton panel. Contact
[email protected] for front panel connector options.
Input is on FPGA pin P30, IOSTAN AR LVCMOS18
The signal is isolated through a optical isolator part number ACPL-M61L with a 739 ohm of series resistance.
Figure 11 : Timing Input Schematic
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