Alpha Data ADM-XRC-II User manual

ADM-XRC-II
PCI Mezzanine Card
User Guide
Version 1.5

ADM-XRC-II User Manual
Copyright © 2002 Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of
this publication may be reproduced, in any shape or form, without prior written
consent from Alpha Data Parallel Systems Limited.
Alpha Data
58 Timber Bush
Edinburgh EH6 6QH
Scotland
UK
Phone: [phone]
Fax: [phone]
Email: [email protected]
Copyright © 2002 Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of
this publication may be reproduced, in any shape or form, without prior written
consent from Alpha Data Parallel Systems Limited.
ADM-XRC-II User Manual
Version 1.5

ADM-XRC-II User Manual
Table of Contents
1. Introduction...............................................................................................1
1.1. Specifications .................................................................................... 1
2. Installation................................................................................................. 2
2.1. Motherboard requirements ................................................................2
2.2. Handling instructions ......................................................................... 2
2.3. Installing the ADM-XRC-II onto a PMC motherboard ........................ 2
2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC ........................... 2
3. Board Overview ........................................................................................ 3
4. PCI Bus Interface...................................................................................... 4
5. ADM-XRC-II Local Bus Architecture .........................................................5
5.1. Characteristics of Address Spaces....................................................5
5.2. Local Control Registers ..................................................................... 6
5.2.1. FCON Register...........................................................................6
5.2.2. CCON Register...........................................................................7
5.2.3. ICON Registers ..........................................................................8
5.2.4. PSTAT Register..........................................................................8
5.2.5. MODE Register ..........................................................................9
5.2.6. Flash_Page Register .................................................................. 9
5.2.7. SelectMAP Register ...................................................................9
FPGA Operation ..............................................................................................9
5.3. Clock Distribution...............................................................................9
5.4. Input Clocks..................................................................................... 10
5.5. Output Clocks .................................................................................. 11
5.6. Local Bus......................................................................................... 12
5.7. Synchronous SRAM ........................................................................ 13
5.8. Clock pins ........................................................................................ 13
5.9. User I/O Configuration ..................................................................... 14
5.9.1. User I/O XRM IO34 Front Panel Variant................................... 14
5.9.2. User I/O XRM IO146 Panel Variant .......................................... 15
5.10. User I/O PMC Pn4 ....................................................................... 18
6. Configuring the FPGA............................................................................. 19
6.1. SelectMAP Operation ...................................................................... 19
6.2. Bitstream Issues .............................................................................. 19
7. Interrupts ................................................................................................ 20
8. Flash Memory ......................................................................................... 21
9. PLX PCI9656 Initialisation ...................................................................... 22
9.1. PCI Registers .................................................................................. 22
9.2. Local Configuration Registers.......................................................... 23
9.2.1. Mode/Arbitration Register......................................................... 23
9.2.2. Big/Little Endian Descriptor Register ........................................ 23
9.2.3. Region 0 Descriptor.................................................................. 23
9.2.4. Direct Master PCI Remap Register .......................................... 24
9.2.5. DM Config/IO Register ............................................................. 24
9.2.6. Region 1 Descriptor.................................................................. 24
9.2.7. Runtime Registers .................................................................... 24
9.2.8. Interrupt Control/Status Register .............................................. 24
9.2.9. EEPROM, PCI, User IO............................................................ 25
10. EEPROM Contents ............................................................................. 26
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11. FPGA Pin Locations............................................................................ 27
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1. Introduction
The ADM-XRC-II is a high performance PCI Mezzanine Card (PMC) format
device designed for supporting development of applications using the Virtex-II
series of FPGA’s from Xilinx.
PCI
Interface
PLX 9656
Target/
Initiator
(DMA)
A/D
PCI
Bus SSRAM
256K x 32/36
XC2V3000-10000
FF1152
Control
Programmable
Clocks
Flash
Memor
y
Select IO
Front Panel I/O
S
e
l
e
c
t
M
a
p
SSRAM
256K x 32/36
SSRAM
256K x 32/36
SSRAM
256K x 32/46
Pn4 I/O
SSRAM
256K x 32/46
SSRAM
256K x 32/46
1.1. Specifications
The ADM-XRC-II supports high performance PCI operation without the need
to integrate proprietary cores into the FPGA. A PLX PCI9656 provides a rich
set of PCI resources including two high-speed DMA.
 Physically conformant to IEEE P1386 Common Mezzanine
Card standard
 High performance PCI and DMA controllers
 Local bus speeds of up to 66MHz
 Six banks of 256k/512kx32/36 ZBT SSRAM
 User clock programmable between 0.5MHz and 100MHz
 User front panel adapter with up to 146 free IO signals
 User rear panel PMC connector with 64 free IO signals
 Supports 3.3V and 5V PCI signalling levels (VI/O)
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2. Installation
This chapter explains how to install the ADM-XRC-II onto a PMC
motherboard.
2.1. Motherboard requirements
The ADM-XRC-II is a Universal PCI device and supports both 3.3V and 5V
PCI signalling levels (VI/O).
The ADM-XRC-II must be installed in a PMC motherboard that supplies 3.3V
power to the PMC connectors. Ensure that the motherboard satisfies this
requirement before powering it up.
2.2. Handling instructions
Observe precautions for preventing damage to components by electrostatic
discharge. Personnel handling the board should take SSD precautions.
Avoid flexing the board.
2.3. Installing the ADM-XRC-II onto a PMC motherboard
Note: This operation should not be performed while the PMC
motherboard is powered up.
The ADM-XRC-II must be secured to the PMC motherboard using M2.5
screws in the four holes provided. The PMC bezel through which the I/O
connector protrudes should be flush with the front panel of the PMC
motherboard.
2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC
The ADM-XRC-II can be supplied for use in standard PC systems fitted to an
ADC-PMC carrier board. The ADC-PMC can support up to two ADC-PMC
cards whilst maintaining host PC PCI compatibility. If you are using a ADC-
PMC64 refer to the supplied documentation for information on jumper
settings. All that is required for installation is a 5V PCI slot that has enough
space to accommodate the full-length card.
It should be noted that the ADC-PMC uses a standard bridge to provide a
secondary PCI bus for the ADM-XRC-II and that some older BIOS code does
not set up these devices correctly. Please ensure you have the latest version
of BIOS appropriate for your machine. The ADC-PMC requires only 5V from
the host PC.
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3. Board Overview
The ADM-XRC-II PMC provides an easy way to achieve PCI performance
without the need to develop or incorporate PCI cores into the FPGA design.
The benefit provided by this architecture means faster development time and
reduced cost in evaluating and testing FPGA applications.
The XRC effectively connects the FPGA directly to the local bus of the
PCI9656 to enable two main modes of operation, slave and master. A
Complex Programmable Logic Device or CPLD also resides on the local bus
and manages access to resources such as flash, SelectMAP and the clock
generator.
In direct slave mode, the XRC is a target on the PCI bus for read and write
transactions and these are translated into local bus cycles initiated by the
PCI9656.
In direct master mode, the FPGA can request control over the local bus and
initiate transactions to the PLX. These transactions are translated by the PLX
into PCI master operations to read or write another PCI target.
In both master and slave modes of operation the FPGA can use burst
capability to boost performance and achieve very high data transfer rates. In
most PC systems, 240MB/s is achievable but this can vary depending on the
quality of the PC chipset and the ability of the BIOS to configure PCI devices
correctly.
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4. PCI Bus Interface
The PCI bus is implemented in a PLX PCI9656 and is configured with settings
as described later in this document to simplify the integration of user
applications in the FPGA.
The PCI configuration space of the ADM-XRC-II is shown below.
Config.
Offset 31 24 23 16 15 8 7 0
00 Device ID
(0042)
(9656)
Vendor ID
(4144)
(10B5)
04 Status Command
08 Class Code RevisionID
0C BIST HeaderType Lat. Timer Cache Line
10 PCI BAR0
(PLX Internal Registers/Memory)
14 PCI BAR1
(PLX Internal Registers/IO)
18 PCI BAR2
(Local Bus FPGA)
1C PCI BAR3
(Local Bus Control/Flash/SelectMap)
20 PCI BAR4
(Not used)
24 PCI BAR5
(Not used)
28 Card Bus CIS Pointer(Not used)
2C Subsystem ID Subsystem Vendor ID
30 PCI Base Address for Local Expansion ROM
34 Reserved
38 Reserved
3C Max Lat Min Gnt Int. Pin Int. Line
The PCI9656 uses the first two Bar’s to provide access to its internal registers
both via memory accesses and I/O accesses. Either BAR may be used by the
host.
BAR 2 provides access to a 4Mbyte space for use by the FPGA and must be
accessed only when a valid FPGA configuration is loaded that can respond
correctly to local bus access.
BAR 3 provides access to the local control registers and the flash memory.
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5. ADM-XRC-II Local Bus Architecture
It is useful to refer to the PLX PCI9656 user manual for information on the
operation of the local bus and how address spaces map to the BAR’s in PCI
configuration space. The first two BAR’s decode memory and I/O ranges for
the PCI9656 internal registers.
There are a further two BAR’s (at offsets 0x18 and 0x1C) that map the two
main local bus address spaces, S0 and S1. In the XRC, S0 is an 4Mbyte
memory address space, 32-bits wide and is available for the user to access
the FPGA . S1 maps in a 4Mbyte memory address space, 8 bits wide for
access to the control registers, flash and FPGA SelectMap port.
A00000
800000
SelectMap and
Control
registers
2M x 8 bit
Flash
2M x
8 bit
PCI9656
000000
HOST
4M byte
space
HOST
4M byte
space
FPGA
4MB
32 bit space
BAR3 – S1
BAR2 – S0
The PCI9656 can be programmed to support 8, 16 or 32 bit local bus widths
and this feature is used to match with the device widths fitted on the XRC.
Other than programming the BAR’s with values determined by the host
system, no other programming of the PCI9656 is required in order to access
the local bus registers and devices.
5.1. Characteristics of Address Spaces
The XRC maps two PCI BAR spaces to the local bus and are specified to
operate differently as shown below.
Space Size Width Burst Prefetch Burst Term Local Offset
S0 4MB 32 yes no yes 0x00000000
S1 4MB 8 yes no yes 0x00800000
From the PCI side of the PCI9656, transfers to either space may be 8, 16 or
32-bit in width and of any length. The PCI9656 breaks up transfers to suit the
address space on the local bus whilst respecting the characteristics outlined
above.
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5.2. Local Control Registers
The local bus control registers are implemented in a CPLD attached to the
PCI9656 local bus. The map of these registers is shown below.
S1+offset Write Read
0 FCON FSTAT
1 CCON CSTAT
2 IMSET IMSTAT
3 IMCLR IMSTAT
4 ICON ISTAT
5 PCON PSTAT
6 MODE MODE
7 FlashPage FlashPage
8-15 SelectMap SelectMap
Registers that are not implemented are marked Must Be Zero (MBZ) and
Read As Don’t Care (RAX). The same applies for bits within implemented
registers that are not used or reserved.
5.2.1. FCON Register
The FPGA can be configured by the host system using the SelectMap port on
the target device. Before this can be achieved, the FPGA must be initialised to
an erased state. Asserting PROG and then releasing it will start the
initialisation process. The INIT bit is only valid whilst the device is not
configured, indicated by a zero in DONE. After configuration, the INIT pin
becomes a user I/O pin and has no further function on the ADM-XRC-II. In
this case the place and route program sets the INIT pin to an input with a
weak pull down thus resulting in INIT appearing set.
7 6 5 4 3 2 1 0
FCON MBZ MBZ MBZ MBZ MBZ MBZ INIT PROG W
FSTAT RAX RAX RAX RAX RAX DONE INIT PROG R
FCON Function (W0/1 is write value, R is when read)
PROG W0 - Release PROGRAM to the FPGA
W1 - Asserts PROGRAM pin on the target FPGA
RX - Indicates state of FCON[PROG]
INIT W0 - Has no effect on FPGA INIT pin
W1 - Asserts INIT pin to FPGA to postpone configuration
R0 - FPGA has no error
R1 - FPGA has asserted INIT
DONE R0 - FPGA is not configured or is being configured
R1 - FPGA is successfully configured
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