Alpha Data ADM-XRC-II User manual

ADM-XRC-II
PCI Mezzanine Card
User Guide
Version 1.5

ADM-XRC-II User Manual
Copyright © 2002 Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of
this publication may be reproduced, in any shape or form, without prior written
consent from Alpha Data Parallel Systems Limited.
Alpha Data
58 Timber Bush
Edinburgh EH6 6QH
Scotland
UK
Phone: [phone]
Fax: [phone]
Email: [email protected]
Copyright © 2002 Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of
this publication may be reproduced, in any shape or form, without prior written
consent from Alpha Data Parallel Systems Limited.
ADM-XRC-II User Manual
Version 1.5

ADM-XRC-II User Manual
Table of Contents
1. Introduction...............................................................................................1
1.1. Specifications .................................................................................... 1
2. Installation................................................................................................. 2
2.1. Motherboard requirements ................................................................2
2.2. Handling instructions ......................................................................... 2
2.3. Installing the ADM-XRC-II onto a PMC motherboard ........................ 2
2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC ........................... 2
3. Board Overview ........................................................................................ 3
4. PCI Bus Interface...................................................................................... 4
5. ADM-XRC-II Local Bus Architecture .........................................................5
5.1. Characteristics of Address Spaces....................................................5
5.2. Local Control Registers ..................................................................... 6
5.2.1. FCON Register...........................................................................6
5.2.2. CCON Register...........................................................................7
5.2.3. ICON Registers ..........................................................................8
5.2.4. PSTAT Register..........................................................................8
5.2.5. MODE Register ..........................................................................9
5.2.6. Flash_Page Register .................................................................. 9
5.2.7. SelectMAP Register ...................................................................9
FPGA Operation ..............................................................................................9
5.3. Clock Distribution...............................................................................9
5.4. Input Clocks..................................................................................... 10
5.5. Output Clocks .................................................................................. 11
5.6. Local Bus......................................................................................... 12
5.7. Synchronous SRAM ........................................................................ 13
5.8. Clock pins ........................................................................................ 13
5.9. User I/O Configuration ..................................................................... 14
5.9.1. User I/O XRM IO34 Front Panel Variant................................... 14
5.9.2. User I/O XRM IO146 Panel Variant .......................................... 15
5.10. User I/O PMC Pn4 ....................................................................... 18
6. Configuring the FPGA............................................................................. 19
6.1. SelectMAP Operation ...................................................................... 19
6.2. Bitstream Issues .............................................................................. 19
7. Interrupts ................................................................................................ 20
8. Flash Memory ......................................................................................... 21
9. PLX PCI9656 Initialisation ...................................................................... 22
9.1. PCI Registers .................................................................................. 22
9.2. Local Configuration Registers.......................................................... 23
9.2.1. Mode/Arbitration Register......................................................... 23
9.2.2. Big/Little Endian Descriptor Register ........................................ 23
9.2.3. Region 0 Descriptor.................................................................. 23
9.2.4. Direct Master PCI Remap Register .......................................... 24
9.2.5. DM Config/IO Register ............................................................. 24
9.2.6. Region 1 Descriptor.................................................................. 24
9.2.7. Runtime Registers .................................................................... 24
9.2.8. Interrupt Control/Status Register .............................................. 24
9.2.9. EEPROM, PCI, User IO............................................................ 25
10. EEPROM Contents ............................................................................. 26
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11. FPGA Pin Locations............................................................................ 27
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1. Introduction
The ADM-XRC-II is a high performance PCI Mezzanine Card (PMC) format
device designed for supporting development of applications using the Virtex-II
series of FPGA’s from Xilinx.
PCI
Interface
PLX 9656
Target/
Initiator
(DMA)
A/D
PCI
Bus SSRAM
256K x 32/36
XC2V3000-10000
FF1152
Control
Programmable
Clocks
Flash
Memor
y
Select IO
Front Panel I/O
S
e
l
e
c
t
M
a
p
SSRAM
256K x 32/36
SSRAM
256K x 32/36
SSRAM
256K x 32/46
Pn4 I/O
SSRAM
256K x 32/46
SSRAM
256K x 32/46
1.1. Specifications
The ADM-XRC-II supports high performance PCI operation without the need
to integrate proprietary cores into the FPGA. A PLX PCI9656 provides a rich
set of PCI resources including two high-speed DMA.
 Physically conformant to IEEE P1386 Common Mezzanine
Card standard
 High performance PCI and DMA controllers
 Local bus speeds of up to 66MHz
 Six banks of 256k/512kx32/36 ZBT SSRAM
 User clock programmable between 0.5MHz and 100MHz
 User front panel adapter with up to 146 free IO signals
 User rear panel PMC connector with 64 free IO signals
 Supports 3.3V and 5V PCI signalling levels (VI/O)
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2. Installation
This chapter explains how to install the ADM-XRC-II onto a PMC
motherboard.
2.1. Motherboard requirements
The ADM-XRC-II is a Universal PCI device and supports both 3.3V and 5V
PCI signalling levels (VI/O).
The ADM-XRC-II must be installed in a PMC motherboard that supplies 3.3V
power to the PMC connectors. Ensure that the motherboard satisfies this
requirement before powering it up.
2.2. Handling instructions
Observe precautions for preventing damage to components by electrostatic
discharge. Personnel handling the board should take SSD precautions.
Avoid flexing the board.
2.3. Installing the ADM-XRC-II onto a PMC motherboard
Note: This operation should not be performed while the PMC
motherboard is powered up.
The ADM-XRC-II must be secured to the PMC motherboard using M2.5
screws in the four holes provided. The PMC bezel through which the I/O
connector protrudes should be flush with the front panel of the PMC
motherboard.
2.4. Installing the ADM-XRC-II if fitted to an ADC-PMC
The ADM-XRC-II can be supplied for use in standard PC systems fitted to an
ADC-PMC carrier board. The ADC-PMC can support up to two ADC-PMC
cards whilst maintaining host PC PCI compatibility. If you are using a ADC-
PMC64 refer to the supplied documentation for information on jumper
settings. All that is required for installation is a 5V PCI slot that has enough
space to accommodate the full-length card.
It should be noted that the ADC-PMC uses a standard bridge to provide a
secondary PCI bus for the ADM-XRC-II and that some older BIOS code does
not set up these devices correctly. Please ensure you have the latest version
of BIOS appropriate for your machine. The ADC-PMC requires only 5V from
the host PC.
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3. Board Overview
The ADM-XRC-II PMC provides an easy way to achieve PCI performance
without the need to develop or incorporate PCI cores into the FPGA design.
The benefit provided by this architecture means faster development time and
reduced cost in evaluating and testing FPGA applications.
The XRC effectively connects the FPGA directly to the local bus of the
PCI9656 to enable two main modes of operation, slave and master. A
Complex Programmable Logic Device or CPLD also resides on the local bus
and manages access to resources such as flash, SelectMAP and the clock
generator.
In direct slave mode, the XRC is a target on the PCI bus for read and write
transactions and these are translated into local bus cycles initiated by the
PCI9656.
In direct master mode, the FPGA can request control over the local bus and
initiate transactions to the PLX. These transactions are translated by the PLX
into PCI master operations to read or write another PCI target.
In both master and slave modes of operation the FPGA can use burst
capability to boost performance and achieve very high data transfer rates. In
most PC systems, 240MB/s is achievable but this can vary depending on the
quality of the PC chipset and the ability of the BIOS to configure PCI devices
correctly.
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4. PCI Bus Interface
The PCI bus is implemented in a PLX PCI9656 and is configured with settings
as described later in this document to simplify the integration of user
applications in the FPGA.
The PCI configuration space of the ADM-XRC-II is shown below.
Config.
Offset 31 24 23 16 15 8 7 0
00 Device ID
(0042)
(9656)
Vendor ID
(4144)
(10B5)
04 Status Command
08 Class Code RevisionID
0C BIST HeaderType Lat. Timer Cache Line
10 PCI BAR0
(PLX Internal Registers/Memory)
14 PCI BAR1
(PLX Internal Registers/IO)
18 PCI BAR2
(Local Bus FPGA)
1C PCI BAR3
(Local Bus Control/Flash/SelectMap)
20 PCI BAR4
(Not used)
24 PCI BAR5
(Not used)
28 Card Bus CIS Pointer(Not used)
2C Subsystem ID Subsystem Vendor ID
30 PCI Base Address for Local Expansion ROM
34 Reserved
38 Reserved
3C Max Lat Min Gnt Int. Pin Int. Line
The PCI9656 uses the first two Bar’s to provide access to its internal registers
both via memory accesses and I/O accesses. Either BAR may be used by the
host.
BAR 2 provides access to a 4Mbyte space for use by the FPGA and must be
accessed only when a valid FPGA configuration is loaded that can respond
correctly to local bus access.
BAR 3 provides access to the local control registers and the flash memory.
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5. ADM-XRC-II Local Bus Architecture
It is useful to refer to the PLX PCI9656 user manual for information on the
operation of the local bus and how address spaces map to the BAR’s in PCI
configuration space. The first two BAR’s decode memory and I/O ranges for
the PCI9656 internal registers.
There are a further two BAR’s (at offsets 0x18 and 0x1C) that map the two
main local bus address spaces, S0 and S1. In the XRC, S0 is an 4Mbyte
memory address space, 32-bits wide and is available for the user to access
the FPGA . S1 maps in a 4Mbyte memory address space, 8 bits wide for
access to the control registers, flash and FPGA SelectMap port.
A00000
800000
SelectMap and
Control
registers
2M x 8 bit
Flash
2M x
8 bit
PCI9656
000000
HOST
4M byte
space
HOST
4M byte
space
FPGA
4MB
32 bit space
BAR3 – S1
BAR2 – S0
The PCI9656 can be programmed to support 8, 16 or 32 bit local bus widths
and this feature is used to match with the device widths fitted on the XRC.
Other than programming the BAR’s with values determined by the host
system, no other programming of the PCI9656 is required in order to access
the local bus registers and devices.
5.1. Characteristics of Address Spaces
The XRC maps two PCI BAR spaces to the local bus and are specified to
operate differently as shown below.
Space Size Width Burst Prefetch Burst Term Local Offset
S0 4MB 32 yes no yes 0x00000000
S1 4MB 8 yes no yes 0x00800000
From the PCI side of the PCI9656, transfers to either space may be 8, 16 or
32-bit in width and of any length. The PCI9656 breaks up transfers to suit the
address space on the local bus whilst respecting the characteristics outlined
above.
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5.2. Local Control Registers
The local bus control registers are implemented in a CPLD attached to the
PCI9656 local bus. The map of these registers is shown below.
S1+offset Write Read
0 FCON FSTAT
1 CCON CSTAT
2 IMSET IMSTAT
3 IMCLR IMSTAT
4 ICON ISTAT
5 PCON PSTAT
6 MODE MODE
7 FlashPage FlashPage
8-15 SelectMap SelectMap
Registers that are not implemented are marked Must Be Zero (MBZ) and
Read As Don’t Care (RAX). The same applies for bits within implemented
registers that are not used or reserved.
5.2.1. FCON Register
The FPGA can be configured by the host system using the SelectMap port on
the target device. Before this can be achieved, the FPGA must be initialised to
an erased state. Asserting PROG and then releasing it will start the
initialisation process. The INIT bit is only valid whilst the device is not
configured, indicated by a zero in DONE. After configuration, the INIT pin
becomes a user I/O pin and has no further function on the ADM-XRC-II. In
this case the place and route program sets the INIT pin to an input with a
weak pull down thus resulting in INIT appearing set.
7 6 5 4 3 2 1 0
FCON MBZ MBZ MBZ MBZ MBZ MBZ INIT PROG W
FSTAT RAX RAX RAX RAX RAX DONE INIT PROG R
FCON Function (W0/1 is write value, R is when read)
PROG W0 - Release PROGRAM to the FPGA
W1 - Asserts PROGRAM pin on the target FPGA
RX - Indicates state of FCON[PROG]
INIT W0 - Has no effect on FPGA INIT pin
W1 - Asserts INIT pin to FPGA to postpone configuration
R0 - FPGA has no error
R1 - FPGA has asserted INIT
DONE R0 - FPGA is not configured or is being configured
R1 - FPGA is successfully configured
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5.2.2. CCON Register
The CCON register controls access to the ICS9161A clock generator. The
range of frequencies supported is between 25 and 66 MHz. Although the XRC
can operate at frequencies less than 25MHz, the CLKDLL circuits in the
FPGA will not. The maximum frequency of the PCI9656 local bus is 66MHZ.
Refer to the ICS9161A data sheet for further information on determining clock
generator settings.
7 6 5 4 3 2 1 0
CCON MBZ MBZ MBZ MBZ INTCLK FEATCLK DATA/S1 CLK/S0 W
CSTAT RAX RAX RAX SERERR INTCLK FEATCLK DATA/S1 CLK/S0 R
CLK Drives clock signal to ICS9161
Determines S0 when static
DATA Drives data signal to ICS9161
Determines S1 when static
FEATCLK Do not use
INTCLK Do not use
The ICS9161 is programmed using CLK and DATA bits to form manchester
encoded sequences. Each sequence consists of a 5 bit unlock preamble
followed by a 24 bit data word all of which must be programmed within 10ms
from the start of the first bit. If programming is not completed within this time,
the ICS9161 will assert SERERR and ignore the remainder of the sequence.
When the ICS9161 is not being programmed, S1 and S0 select the internal
VCLK programming register.
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5.2.3. ICON Registers
The ICON registers consist of a mask register and an interrupt status register.
The mask register can be set or cleared by writing to IMSET or IMCLR with a
bit mask. The XRC only supports one interrupt from the local bus and is
masked, set or cleared using bit 0. On reset the mask bits are set disabling
local bus interrupts.
7 6 5 4 3 2 1 0
IMSET MBZ MBZ MBZ MBZ MBZ MBZ MBZ FINTM W
IMCLR MBZ MBZ MBZ MBZ MBZ MBZ MBZ FINTM W
IMSTAT RAX RAX RAX RAX RAX RAX RAX FINTM R
The ICON register contains the status of the interrupt from the FPGA. This bit
can be read independently of the state of the FINTM mask bit.
The method used to clear FINT in the ISTAT register depends on the interrupt
mode selected by IMODE (MODE [0]).
• With edge-triggered interrupts, writing the FINT bit in ICON clears the
corresponding bit in ISTAT.
• For level sensitive interrupts, FINT can only be cleared by removing the
interrupting source in the FPGA.
7 6 5 4 3 2 1 0
ICON MBZ MBZ MBZ MBZ MBZ MBZ MBZ FINT W
ISTAT RAX RAX RAX RAX RAX RAX RAX FINT R
5.2.4. PSTAT Register
The PSTAT register presents information about the power supply to the Virtex
device. The XRC generates power for the FPGA core from 5V, using a switch
mode supply circuit that outputs two signals to indicate over-temperature and
accuracy.
7 6 5 4 3 2 1 0
PSTAT RAX RAX RAX RAX RAX RAX PTEMP PGOOD R
PGOOD 0 => PSU is out of range
1 => PSU is within +/- 10%
PTEMP 0 => PSU has shutdown (thermal detect)
1 => PSU is within operating range
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5.2.5. MODE Register
The MODE register contains fields that allow the additional functionality of
operations to be specified.
7 6 5 4 3 2 1 0
MODE MBZ MBZ MBZ MBZ MBZ MBZ BREV IMODE W
MODE RAX RAX RAX RAX RAX RAX BREV IMODE R
IMODE 0 => Edge triggered interrupt mode
1 => Level sensitive interrupt mode
BREV 0 => SelectMAP port LSB is DIN/D0
1 => SelectMAP port MSB is DIN/D0
5.2.6. Flash_Page Register
The Flash Page register is used to provide the upper flash address bits. The
flash page size is set at 2M bytes and the upper address bits are provided
from the register as follows :-
7 6 5 4 3 2 1 0
Flashpage Configuration Data Byte W
5.2.7. SelectMAP Register
The XRC supports only SelectMAP download of configuration data to the
Virtex FPGA. The SelectMAP register is a write only port (in the current XRC)
that is written with configuration information. The mapping of this port is
determined by the BREV bit in the MODE register.
7 6 5 4 3 2 1 0
SelectMap Configuration Data Byte W
NOTE. Do not write to the SelectMAP register whilst DONE is set.
FPGA Operation
The following sections describe the operation of the FPGA in terms of the
resources that are available. Where pin numbers are not mentioned, these
can be found in the constraints file for the various Virtex II devices, supplied
with the SDK. Please refer to the installation directory for examples of working
designs and guidelines.
5.3. Clock Distribution
The XRC uses the PLX PCI9656 local bus to provide a synchronous data
transfer interface and all devices attached to the PCI9656 run at the local bus
clock rate.
The MCLK output from the ICS9161 provides the local bus clock and by
default runs at 32.5MHz. The VCLK output can be determined by three
registers in the ICS9161, selected by the S1/S0 bits in the CCON register. It is
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recommended that alterations to VCLK use REG1 or REG2 to set the new
value so that on reset the VCLK output selects REG0 when S1/S0 are reset.
SRAM
Clocks
Host
Setting
VCLK
MCLK Virtex
FPGA
CPLD
Control
Logic
PCI9656
ICS
9161A
Osc
14.3181
MHz
5.4. Input Clocks
There are two primary clock inputs to the FPGA, both from the programmable
clock generator. The VCLK signal from the clock generator is used only by the
FPGA. It is therefore free for use by logic in the FPGA.
The MCLK signal from the clock generator is the local bus clock, used by the
FPGA, PLX PCI9656 and a support CPLD.
Both MCLK and VCLK can be programmed between 400kHz and 100MHz.
A restriction on MCLK is that it must not exceed 66MHz,the maximum
speed of the PCI9656, and should not be lower than 25MHz for reliable
CLKDLL operation.
MCLK is input to the FPGA on GCK7 (pin AG18) and should be used to drive
a Virtex CLKDLL circuit which aligns the internal FPGA clock to the local bus
clock. The circuit below demonstrates how to align the internal clock of the
FPGA to the local bus clock. The output of the BUFG is available to all flip-
flops in the design.
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VCLK is input to the FPGA on GCK1 (pin AF18) and can be used for any
purpose within the FPGA.
5.5. Output Clocks
The FPGA is responsible for providing clocks to the SRAM’s and also for
aligning its internal global clock with the local bus clock. To do this requires
the use of Virtex DCM’s that are specifically designed for the purpose of
minimising skew between external and internal clock domains.
The SRAM’s are split into two banks of three – each bank of three has its
own FPGA clock output and feedback pin to allow deskewing within the
FPGA. Further details of SRAM clocking are provided in section 5.8.
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5.6. Local Bus
The local bus of the ADM-XRC-II uses the PCI9656 to provide a non-
multiplexed address and data capability with synchronous speeds of up to
66MHz, independent of PCI operation. Whilst the local bus is capable of
achieving near PCI performance, it is much simpler to interface with than PCI.
The ADM-XRC-II routes most of the local bus signals to the FPGA and
devotes an entire address space to the FPGA.
The signals provided are :-
Signal Active Direction Purpose
LA[31:2] high IN Address
LBE[3:0} low IN Address/byte enables
LD[31:0] high BIDIR Data Bus
LWRITE high IN Write cycle when true, read when false
LBLASTL low IN End of burst
LADSL low IN Address / data start
LBTERML low OUT/TRI Burst terminate
LREADYIL low OUT/TRI Accepts/completes data transfer
LDREQL[1:0] low OUT Request DMA transfer
LDACKL[1:0] low IN DMA transfer acknowledge
LEOTL[1:0] low OUT Terminate current DMA transfer
LINTIL low OUT Interrupt (via CPLD)
FHOLD high OUT Reserved for future use
FHOLDA high IN Reserved for future use
LRESETOL low IN Reset from PLX and PCI
LCLKA high IN Local bus clock (VCLK from ICS9161)
The local bus provides 8Mbytes of address space for the FPGA to use for
whatever purpose is desired by the application. LA[23]=0 should be used to
determine when the FPGA is being accessed.
Example Verilog code demonstrates how to interface to the local bus and
provide access to the SSRAM’s for test purposes. User applications can
define how the address space allocated to the FPGA is mapped to the local
bus and may or may not provide access to the SRAM memory.
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5.7. Synchronous SRAM
The four banks of synchronous SRAM are identical in device type and FPGA
interface. The devices fitted as pipelined ZBT parts organised as 256Kx32/36
bits each.
The pins are allocated to support synchronous burst or ZBT SRAM and each
bank provides the following interface.
FPGA Pin Active Type Function
RDn[36:0] high Bidir Data Bus
RAn[19:0] high OUT Address Bus
RCn[3:0] low OUT Byte enables
RCn[4] low OUT Global write enable
RCn[5] low OUT Chip enable
RCn[6] low OUT ADV (advance) function
RCn[7] low OUT Output enable
RCn[8] low OUT CKE - clock enable
Where n= 0,1,2,3,4,5. Therefore, SRAM 0 is controlled by the three bus ports
RD0[36:0], RA0[19:0] and RC0[8:0] and these are names used to constrain
the pins in the user constraints file or UCF.
5.8. Clock pins
The six banks of SRAM are divided into two clock domains. Each SRAM clock
domain has its own pin routed from the FPGA.
ramclk[0] OUT Clock to SRAM 0, SRAM 1, SRAM 2
ramclk[1] OUT Clock to SRAM 3, SRAM 4, SRAM 5
ramclk_fb[0] INPUT Clock feedback for ramclk[0]
ramclk_fb[1] INPUT Clock feedback for ramclk[1]
Clock Domain 0
Clock Domain 1
Sram 0 Clk
Sram 1 Clk
Sram 2 Clk
Sram 3 Clk
Sram 4 Clk
Sram 5 Clk
IBufg
IBufg
OBuf
OBuf
ramclk[0]
ramclk[1]
ramclk_fb[0]
ramclk_fb[1]
to/from
Virtex DCM
to/from
Virtex DCM
Virtex II Device
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5.9. User I/O Configuration
The ADM-XRC-II is fitted with and IO adapter to provide user I/O capability
via the front panel. This allows many different IO connectors and standards to
be easily supported. Currently the following IO adapter cards are available
5.9.1. User I/O XRM IO34 Front Panel Variant
There are 34 I/O signals available on the front panel connector and these can
be used individually or in pairs. All of these signals are from one bank of the
FPGA and are provided with a VCCo supply voltage of 2.5V or 3.3V selected
by JP1. A link on pins 2-3 selects 2.5V whilst a link on pins 1-2 select 3.3V.
Each pair of I/O signals is routed as shown below.
FPGA IO CON
Rs
Rs
Rs
Rs
Rt
Rt
User[0]
User[1]
User[2]
User[3]
The default manufacturing option is Rs=0R and Rt not fitted. Other options are
available. Rs can be used to provide series damping in point to point
applications but for LVDS is 0R. Rt is required for LVDS inputs to provide the
termination voltage from the line current.
User I/O is presented on a 68 way miniature D connector (of SCSI-2 style)
with interleaved signal and ground pairs as shown below. All of the user pins
are routed in pairs to suit the differential assignments of the FPGA e.g.
user[1:0] are the first up to user[33:32].
1
34 68
35
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Signal Pin Pin Signal
1 35 USER[0]
2 36 USER[1]
3 37 USER[2]
4 38 USER[3]
5 39 USER[4]
6 40 USER[5]
7 41 USER[6]
8 42 USER[7]
9 42 USER[8]
10 44 USER[9]
11 45 USER[10]
12 46 USER[11]
13 47 USER[12]
14 48 USER[13]
15 49 USER[14]
16 50 USER[15]
17 51 USER[16]
18 52 USER[17]
19 53 USER[18]
20 54 USER[19]
21 55 USER[20]
22 56 USER[21]
23 57 USER[22]
24 58 USER[23]
25 59 USER[24]
26 60 USER[25]
27 61 USER[26]
28 62 USER[27]
29 63 USER[28]
30 64 USER[29]
31 65 USER[30]
32 66 USER[31]
33 67 USER[32] -CLK
All GND
34 68 USER[33] -CLK
5.9.2. User I/O XRM IO146 Panel Variant – Rev2.0
There are 146 I/O signals available on the front panel connector and these
can be used individually or in pairs. Each pair of I/O signals is routed as
shown below.
FPGA IO CON
Rs
Rs
Rs
Rs
Rt
Rt
User[0]
User[1]
User[2]
User[3]
The default manufacturing option is Rs=0R and Rt not fitted. Other options are
available. Rs can be used to provide series damping in point to point
applications but for LVDS is 0R. Rt is required for LVDS inputs to provide the
termination voltage from the line current.
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2
152151
1
Pin numbering looking into front of XRM IO146 connector
Pin Function UCF
name
Term
Res
V II Pin Pin Function UCF
name
Term
Res
V II Pin
1 Data[0] +ve User[0] R1 B3 2 Data[1] +ve User[2] R4 C9
3 Data[0] -ve User[1] - C2 4 Data[1] -ve User[3] - D9
5 Data[2] +ve User[4] R3 B5 5 Data[3] +ve User[6] R2 E9
7 Data[2] -ve User[5] - B4 6 Data[3] -ve User[7] - E8
9 Data[4] +ve User[8] R5 C6 10 Data[5] +ve User[10] R6 B10
11 Data[4] -ve User[9] - D6 12 Data[5] -ve User[11] - B9
13 Data[6] +ve User[12] R7 J10 14 Data[7] +ve User[14] R8 D11
15 Data[6] -ve User[13] - H11 16 Data[7] -ve User[15] - D10
17 Data[8] +ve User[16] R9 F8 18 Data[9] +ve User[18] R10 G11
19 Data[8] -ve User[17] - F9 20 Data[9] -ve User[19] - G10
21 Data[10]+ve User[20] R11 B7 22 Data[11] +ve User[22] R12 H9
23 Data[10] -ve User[21] - B6 24 Data[11] -ve User[23] - H10
25 Data[12]+ve User[24] R14 C8 26 Data[13] +ve User[26] R15 H12
27 Data[12] -ve User[25] - C7 28 Data[13] -ve User[27] - H13
29 Data[14]+ve User[28] R16 A5 30 Data[15] +ve User[30] R17 J11
31 Data[14] -ve User[29] - A4 32 Data[15] -ve User[31] - J12
33 Single 0 User[34] N/a A9 34 Clock[0] +ve User[32] R64 H16
35 Single 1 User[35] N/a F13 36 Clock[0] -ve User[33] - H17
37 +5V fused 38 Single 2 User[36] N/a C16
Pin Function UCF
name
Term
Res
V II Pin Pin Function UCF
name
Term
Res
V II Pin
39 Data[16] +ve User[40] R19 A7 40 Data[17] +ve User[42] R20 K12
41 Data[16] -ve User[41] - A6 42 Data[17] -ve User[43] - J13
43 Data[18] +ve User[44] R23 A12 44 Data[19] +ve User[46] R22 C12
45 Data[18] -ve User[45] - A11 46 Data[19] -ve User[47] - C11
47 Data[20] +ve User[48] R25 B12 48 Data[21] +ve User[50] R24 B14
49 Data[20] -ve User[49] - B11 50 Data[21] -ve User[51] - B13
51 Data[22] +ve User[52] R27 D13 52 Data[23] +ve User[54] R26 G13
53 Data[22] -ve User[53] - D12 54 Data[23] -ve User[55] - G12
55 Data[24] +ve User[56] R29 E14 56 Data[25] +ve User[58] R28 J14
57 Data[24] -ve User[57] - E13 58 Data[25] -ve User[59] - J15
59 Data[26] +ve User[60] R37 K13 60 Data[27] +ve User[62] R30 C14
61 Data[26] -ve User[61] - K14 62 Data[27] -ve User[63] - C13
63 Data[28] +ve User[64] R41 K15 64 Data[29] +ve User[66] R38 H14
65 Data[28] -ve User[65] - K16 66 Data[29] -ve User[67] - H15
67 Data[30] +ve User[68] R44 G17 68 Data[31] +ve User[70] R42 F17
69 Data[30] -ve User[69] - G16 70 Data[31] -ve User[71] - F16
71 Single 3 User[37] N/a G20 72 Clock[1] +ve User[72] R67 E16
73 Single 4 User[38] N/a A28 74 Clock[1] –ve User[73] - E17
75 +5V fused 76 Single 5 User[39] N/a G15
ADM-XRC-II User Manual
Version 1.5
Page 16