Alpha Data ADM-XRC-II Pro User manual

ADM-XR-IIPro User Manual
Page 1 of 29 Version 0.2
ADM-XRC-II Pro
(ADM-XP)
Hardware Manual

ADM-XR-IIPro User Manual
Page 2 of 29 Version 0.2
Alpha Data
4 West Silvermills Lane
Edinburgh EH3 5BD
UK
Phone: [phone]
Fax: [phone]
Email: [e-mail]
Alpha Data
226 Airport Parkway
Suite 470
San Jose
CA 95110
USA
Phone: [phone]
Fax: [phone]
Email: [e-mail]
Copyright © 2002, 2003, 2004 Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of this
publication may be reproduced, in any shape or form, without prior written consent from Alpha
Data Parallel Systems Limited.

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Revision History
Revision Date Comments
0.1 Jul-04 Initial
0.1+ DATA1, DATA8 DATA13 and DATA15 – polarity swapped
DATA38 pin nos swapped in Manual
Clock pins updated for XP pinouts (were XPL pinouts)
0.2 Nov-04 Removed XRM-Pro Debug Section – added XRM ETH

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Contents
1INTRODUCTION .......................................................................................................................................... 5
1.1 SPECIFICATIONS ...................................................................................................................................... 5
2INSTALLATION ........................................................................................................................................... 6
2.1 MOTHERBOARD REQUIREMENTS ............................................................................................................... 6
2.2 HANDLING INSTRUCTIONS ........................................................................................................................ 6
2.3 INSTALLING THE ADM-XP ONTO A PMC MOTHERBOARD ........................................................................... 6
2.4 INSTALLING THE ADM-XP IF FITTED TO AN ADC-PMC .............................................................................. 6
3HARDWARE OVERVIEW............................................................................................................................ 7
4LOCAL BUS ARCHITECTURE ................................................................................................................... 9
4.1 LOCAL BUS SIGNALS ................................................................................................................................9
4.2 LOCAL BUS TRANSFERS........................................................................................................................... 9
5TARGET FPGA.......................................................................................................................................... 10
5.1 CONFIGURATION.................................................................................................................................... 10
5.2 CLOCKS ................................................................................................................................................ 10
5.3 SDRAM DDR MEMORY ........................................................................................................................ 12
5.4 DDR2 SSRAM..................................................................................................................................... 13
5.5 FLASH MEMORY .................................................................................................................................... 14
5.6 POWER SUPPLY .................................................................................................................................... 14
6FRONT PANEL I/O .................................................................................................................................... 15
6.1 SAMTEC 180 CONNECTOR - U8 ............................................................................................................. 15
6.2 ROCKETIO MULTI-GIGABIT TRANSCEIVERS – U13 .................................................................................. 17
7USER IO – PMC PN4 (REAR PANEL)...................................................................................................... 18
8JTAG ACCESS .......................................................................................................................................... 19
8.1 JTAG HEADER (J6)............................................................................................................................... 19
9XRM-ETH ................................................................................................................................................... 20
9.1 INTRODUCTION ...................................................................................................................................... 20
9.2 GENERAL PURPOSE I/O ......................................................................................................................... 20
9.3 RS232 I/O............................................................................................................................................ 20
9.4 10/100 ETHERNET ................................................................................................................................21
9.5 INPUT AND OUTPUT ASSIGNMENTS (ADM-XP)........................................................................................ 22
9.5.1 Mictor I/O...................................................................................................................................... 22
9.5.2 DCI Terminations ......................................................................................................................... 22
9.5.3 Ethernet MAC............................................................................................................................... 23
9.5.4 RS232 .......................................................................................................................................... 23
10 USER I/O XRM IO146 FRONT PANEL VARIANT – REV2.0................................................................ 24
11 USER I/O XRM IO146 – ROCKET ......................................................................................................... 27

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1 Introduction
The ADM-XP (XP) is an advanced PCI Mezzanine card (PMC) supporting Xilinx Virtex-II PRO™ (V2PRO)
devices, the latest development in FPGA technology. The XP supports 2VP70, 2VP100 or 2VP125 devices
with two embedded PowerPC processors.
The XP utilises an FPGA PCI bridge developed by Alpha Data supporting 64 bit PCI at up to 66MHz. Future
enhancements will provide compatibility with PCI-X. A high speed multiplexed address and data bus connects
the bridge to the target FPGA.
Memory resources provided on-board include DDR SDRAM, DDR2 SSRAM and flash, all of which are
optimised for direct use by the FPGA using IP and toolkits provided by Xilinx.
Flexible I/O is the key to the ADM-XRC-II series of boards and the XP is compatible with a wide selection of
XRM modules that use the 180 pin Samtec interface.
1.1 Specifications
The ADM-XP supports high performance PCI operation without the need to integrate proprietary cores into the
FPGA.
• Physically conformant to IEEE P1386 Common Mezzanine Card standard
• High performance PCI and asynchronous local bus
• Local bus speeds of up to 80MHz
• Four banks of 256K * 32 bits of DDR2 SSRAM – option for 512K * 32 bits
• Two banks of 64MB DDR SDRAM – option for 128MB
• Two flash devices of 16MB each for bridge and target devices
• User clock programmable between 5MHz and 200MHz
• User front panel adapter with up to 146 free IO signals
• Supports 3.3V PCI or PCIX at 64 bits
• On board 125MHz LVPECL oscillator
• 8 x RocketIO Multi-Gigabit Transceiver Connections (optional) @ 2.5Gb/s

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2 Installation
This chapter explains how to install the ADM-XP onto a PMC motherboard.
2.1 Motherboard requirements
The XP is a 3.3V only PCI device and is not compatible with systems that use 5V signalling.
The XP must be installed in a PMC motherboard that supplies 3.3V power to the PMC connectors. Ensure that
the motherboard satisfies this requirement before powering it up.
2.2 Handling instructions
Observe precautions for preventing damage to components by electrostatic discharge. Personnel handling the
board should take SSD precautions.
Avoid flexing the board.
2.3 Installing the ADM-XP onto a PMC motherboard
Note: This operation should not be performed while the PMC motherboard is powered up.
The ADM-XP must be secured to the PMC motherboard using M2.5 screws in the four holes provided. The
PMC bezel through which the I/O connector protrudes should be flush with the front panel of the PMC
motherboard.
2.4 Installing the ADM-XP if fitted to an ADC-PMC
The ADM-XP can be supplied for use in standard PC systems fitted to an ADC-PMC carrier board. The ADC-
PMC can support up to two ADC-PMC cards whilst maintaining host PC PCI compatibility. If you are using a
ADC-PMC64 refer to the supplied documentation for information on jumper settings. With the ADC-PMC64 all
that is required for installation is a 5V or 3V PCI slot that has enough space to accommodate the full-length
card.
It should be noted that the ADC-PMC uses a standard bridge to provide a secondary PCI bus for the ADM-XP
and that some older BIOS code does not set up these devices correctly. Please ensure you have the latest
version of BIOS appropriate for your machine.

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3 Hardware Overview
The XP is based on the architecture of the ADM-XRC-II with changes to accommodate the enhanced
resources and needs of the Virtex-II PRO device.
The XP follows the architecture of the ADM-XRC series and decouples the “target” FPGA from the “bridge”
device to allow the entire target to be available for user applications. This ensures the user can be up and
running with the minimum of effort and without the complexity of PCI design.
The bridge includes local bus control and monitoring together with flexible configuration options for the bridge
and the target device.
The bridge is capable of 66MHz PCI or PCI-X operation with 64-bit or 32-bit operation. The local bus supports
64-bit at upto 80Mhz
The target FPGA is a Virtex-II-PRO device incorporating FPGA fabric, multi-gigabit transceivers and two
PowerPC cores.
DDR SDRAM, ZBT and flash memory connect to the target FPGA and are supported by Xilinx or third party IP.
IO functionality is provided using XRM modules connecting to the 180 pin SAMTEC QSE and 28 pin SAMTEC
QSE DP connectors.
Virtex II FG676
2V1500
Alpha Data PCI/
PCIX to Local Bus
Bridge
Virtex II Pro - FF1704
2VP70-2VP125
SSRAM
Target
Config
Flash
Clocks
Power
JTAG
Local Bus
SSRAM
64/66 PCI
PCIX 133
146 Bit
IO Bus
MGT Bus
IO Connector/
headers
PN4 IO
DDR2
SDRAM
Target
User
Flash
Bridge
Config
Flash
Config
Control
CPLD
SSRAM SSRAM
DDR2
SDRAM

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The physical layout is shown in the diagram below. The DDR DRAM and DDR2 SSRAM devices are
clam shelled and appear on both sides of the board.
J5 - Jtag Header
J
1
X
R
M
M
E
Z
Z
J
2
J
4
JP1 - VIO Selection
J
3
2V1500
Bridge
2VP70-2VP100
Target
ZBT ZBT
1
Flash
DDR DDR
Flash
M
G
T
Power
Clock
Gen
11
1-2 3.3V
2-3 2.5V
U8 - Samtec 180 Connector
(Select IO)
U13 - Samtec DP Connector
MGT's

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4 Local Bus Architecture
The XP implements a multi-master local bus between the bridge and the target FPGA using a 32 or 64
multiplexed address and data path. The bridge design is asynchronous and allows the local bus to be run
faster or slower than the PCI bus clock to suit the complexity of the user design.
4.1 Local Bus signals
2V1500 PCI
to
Local Bus Bridge
PCI BUS
Target FPGA
2VP70/2VP100
Bank 3
lad[0:63]
lbterm_l
lbe_l[0:7]
lads_l
lblast_l
lready_l
ldreq_l[1:0]
lreset_l
lwrite
ldack_l[1:0]
fhold
fholda
Signalling Virtex2Pro
default - 2.5V (fast)
LVCMOS/LVTTL
lclk AT21
AF1
AF2
AG12
AF7
AD10
AD9
AC10
AC9
Signal Type Purpose
lad[0:63] bidir Address and data bus.
lreset_l unidir Reset to target
lads_l bidir Indicates address phase
lblast_l bidir Indicates last word
lbterm_l bidir Indicates ready and requests new address phase
lready_l bidir Indicates that target accepts or presents new data
lclk unidir Clock to synchronise bridge and target
lbe_l[0:7] bidir Byte qualifiers
dreq_l[0:1] unidir DMA request from target to bridge
dack_l[0:1] unidir DMA acknowledge from bridge to target
fhold unidir Target bus request
fholda unidir Bridge bus acknowledge
4.2 Local Bus Transfers
Please refer to the ADM-XRC SDK Help for Windows supplied with the XP for information on local bus
transfers.

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5 Target FPGA
The target FPGA is a V2PRO 2VP70, 2VP100 or 2VP125 (when available) in an FF1704 package. On the XP,
all of the resources such as DDR, DDR2 SSRAM, IO and Flash are available no matter what device is fitted.
The V2PRO has 8 banks of I/O and banks 0 and 1 provide the User IO to the front panel . The VCCIO voltage
for banks 0 and 1 is selectable using JP1.
JP1 Link Posn VCCIO – Front IO
1-2 +3V3
2-3 +2V5
5.1 Configuration
The target FPGA can be configured using two primary mechanisms. In the first, JTAG from the J6 header can
be used to perform downloading of bit-streams as well as remote debug using tools such as GDB and
ChipScope / Pro. The drawback of using JTAG is that a download cable must be connected to the board.
The XP provides a SelectMAP port between the bridge and the target device mapped to the PCI bus. This
enables very rapid download of configuration data controlled by driver and API code in the host. The maximum
speed that can be achieved is 33 Mbytes per second.
5.2 Clocks
There are a number of clock sources in the XP as shown in the diagram below. Although the ICS307 is shown
connected to the bridge, which may appear differently from the block diagram in the previous section, the
purpose is to provide level translation between the 3.3V output of the clock generator and the 2.5V inputs of
the 2VP70.
ICS307
14.318MHz
OSC
CLKGEN_CLK1
CLKGEN_CLK2
2V1500
PCI
Bridge
2VP70
100/125
Virtex
PRO
LCLK
MCLK
OSC 125MHz
Differential
PCI 33/66 MHz
XRM
Interface
Bank1 Pair 0S/1P
Bank1 Pair 2S/3P
Bank0 Pair 4S/5P
3.3V signalling
2.5V signalling
Control
Bank0 Pair 6S/7P
The V2PRO has a dedicated clock for gigabit operation using the Epson 2121CA 125MHz device. This is input
on GCLK4S/5P in bank 5 and should be received in differential LVDS mode. Because of the routing limitations

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within the V2Pro device and the allocation of the MGT resources on the board the MGT’s are currently limited
to 2.5GBps operation using the REFCLK input to the transceivers.
The MCLK signal is input to the FPGA to provide a user clock of between 10 and 200MHz, single ended. The
local bus uses LCLK to synchronize transfers between the bridge and the target and is derived from MCLK by
a divide by 2 in the ICS307. Although the clocks are related, phase is not guaranteed.
A summary of the clock pins is shown in the table below.
Bank VCCO GCLK Pin Signal Description
0 JP1 select 7P K22 IO_74N_0/GCLK7P
0 JP1 select 6S J22 IO_74P_0/GCLK6S
0 JP1 select 5P F22 IO_75N_0/GCLK5P
0 JP1 select 4S G22 IO_75P_0/GCLK4S
1 JP1 select 0S K21 IO_74P_1/GCLK0S
1 JP1 select 1P J21 IO_74N_1/GCLK1P
1 JP1 select 2S F21 IO_75P_1/GCLK2S
1 JP1 select 3P G21 IO_75N_1/GCLK3P
User clocks to / from XRM
4 2.5V 0P AT21 LCLK Local Bus Clock :-
MCLK divided by 2
4 2.5V 1S AU21 MCLK User programmable up to
200MHz. Default is 66MHz
4 2.5V 2P AP21 DDR2_clk Clock feedback DDR DRAM 1
4 2.5V 3S AN21 DDR1_clk Clock feedback DDR DRAM 0
2 2.5V - AB12 DDR1_clk
2 2.5V - AA12 DDR1_clkb
2 2.5V - AA10 DDR2_clk
2 2.5V - AA9 DDR2_clkb
Used for clock forwarding of
DDR clock outputs
5 2.5V 6P AU22 MGT_clk
5 2.5V 7S AT22 MGT_clkb
Clock for the MGTs
5 2.5V 4P AN22 PN4 fpga_P3
5 2.5V 5S AP22 PN4 fpga_N3
PN4 IO clocks
If required, XRM related clocks should be terminated on the XRM itself. No terminations are provided on the
XP main board.

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5.3 SDRAM DDR Memory
The XP provides 2 independent banks of 64MB of DDR SDRAM with the option of 128MB when devices
become available. Two Micron MT46V16M16 devices are fitted and are organised as 4Mx16x4. These devices
can be operated at between 75MHz and 133MHz and depending on resource usage within the FPGA, a
2VP70 can easily achieve 100MHz (DDR200) operation. Both banks are driven from Bank2 of the V2Pro.
2VP70 / 2VP100
FF1704
DQ1[16:31]
DDR1_CLK
DDR1_CLKB
DQS1[2:3]
DQM1[2:3]
DQ1[0:15]
DQS1[0:1]
DQM1[0:1]
DDR1_AD/BA/CTL
DDR1_CLK_FB
Bank 2
VCCO=2.5V
DDR
SDRAM
DQ0[16:31]
DQS0[2:3]
DQM0[2:3]
DQ0[0:15]
DQS0[0:1]
DQM0[0:1]
DDR SDRAM
Bank 0
DDR SDRAM
Bank 1
DDR
SDRAM
DDR
SDRAM
DDR
SDRAM
DDR0_AD/BA/CTL
DDR0_CLK_FB
DDR0_CLK
DDR0_CLKB
The pins required for the SDRAM controller for each bank are listed below.
The DDR controller uses SSTL1 IOB’s for data and control and SSTL1 for address and clocks - Please refer to
the UCF for locations of the DDR pins. Please note that the FPGA requires the Vref pins to be connected for
correct data reception on bank 3 when using SSTL standard. Additionally, bank 4 Vref pins connect to board
Vref but are not required for user applications. These pins should not be configured with pull-up or pull-down
options otherwise the Vref level will be set incorrectly.
The XP is designed to support DDR interface cores supplied by Xilinx using 90 degree phase shifted clocks for
DQS during write operations. This requires DQS pins occupy IOB’s that do not share a clock signal with DQ
pins. In the XP, DQS[0:1] and DQS[2:3] occupy pairs of IOB’s sharing a common clock. Note A trace delay
has been incorporated on the DQS lines of approx 1.5ns to allow the use of local clocking within the FPGA
Name Type
DDR_ad[0:12] Output
DDR_dq[0:31] Bidir
DDR_dqs[0:3] Bidir
DDR_rasb Output
DDR_casb Output
DDR_web Output
DDR_ba[0:1] Output
DDR_clk Output
DDR_clkb Output
DDR_csb Output
DDR_cke Output
DDR_dm[0:1] Output
DDR_clk_fb Input

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5.4 DDR2 SSRAM
The XP supports four independent banks of CIO DDR2 SSRAM memory. The devices fitted are Samsung
512K *36 (K7I163684-FC16) parts or a functional equivalent. As an upgrade option 1Mx36 (K7I323684-FC16)
devices can also be fitted.
2VP70 / 2VP100
FF1704
Bank 6
VCCO=1.8V
DDR2
SSRAM
Add0[0:21]
Dq0[0:31]
DDR2 SSRAM Bank 0
Bank 7
VCCO=1.8V
Bwe0[0:3]
Cclk0/Cclkb0
Kclk0/Kclkb0
DDR2
SSRAM
Add0[0:21]
Dq0[0:31]
Bwe0[0:3]
Cclk0/Cclkb0
Kclk0/Kclkb0
DDR2
SSRAM
Add1[0:21]
Dq1[0:31]
Bwe1[0:3]
Cclk1/Cclkb1
Kclk1/Kclkb1
DDR2
SSRAM
Add0[0:21]
Dq0[0:31]
Bwe0[0:3]
Cclk0/Cclkb0
Kclk0/Kclkb0
DDR2 SSRAM Bank1
DDR2 SSRAM Bank 2
DDR2 SSRAM Bank 3
The pins required for each SSRAM controller bank are listed below.
Name FPGA Pin Type Description
ZBTx_ad[0:21] Output Address bus
ZBTx_dq[0:31] Bidir Data bus
ZBTx_rw Output Read(1) / Write(0)
ZBTx_bwe{0..3] Output Byte enables for writes
ZBTx_nld Output Initiates a transaction
ZBTx_Cclk/ZBTx_nCclk Output SSRAM Output Data Clock
ZBTx_Kclk/ZBTx_nKclk Output SSRAM Clock for Inputs
ZBTx_DOFF Output SSRAM DLL Enable
The SSRAM pins should be configured for HSTL_II_18 operation
The SSRAM clock Cclks and Kclks are intended to be used with clock-forwarding implemented in a DDR IOB
with a DCM used to adjust for SSRAM clock to output delays on the data input path to the FPGA.

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5.5 Flash Memory
The XP supports a flash device connected to the V2PRO for general purpose applications. Typically in
applications that use a PPC core the flash is used to hold bootstrap or application code.
The flash memory has its own set of pins located within banks 3 and 4 of the V2Pro and the IO voltage on the
Flash device is set at 2.5V. It is recommended that the LVCMOS_25 V2Pro IO standard be used for the Flash
Interface.
2VP70 / 2VP100
FF1704
dq[0:15]
RC28F256K3
Strataflash K3
Flash_rst_n
ad[0:23]
A0
Flash_oe_n
Flash_we_n
Flash_cs_n
VIO
Bank 3 & 4
VCCO= 2.5V
VCC
+2V5 +3V3
Flash_wp_n
Flash_adv_n
Flash_clk
Flash_sts
Flash_wait
5.6 Power Supply
The PMC connectors supply +5V and +3V3 to the XP and both of these rails are used with the card.
The +5V rail is used to provide FPGA VIO supplies of 2.5V @ 8A max and 1.8V at 6A max each.
The +3V3 rails is used to provide the FPGA VCC core of 1.5V @ 9A max. These are maximum values for the
individual supply circuits but consideration must be taken to the power envelope that the PMC card is being
deployed

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6 Front Panel I/O
The XP supports standard XRM’s used on the ADM-XRC-II and ADM-XPL cards and also has an additional
connector that brings 7 MGT channels upto the XRM Module site using a differential 28 pin Samtec QSE-DP
series connector to maintain signal integrity.
The XP supports the standard Samtec 180 pin connector but using either with 2.5V or 3.3V signalling which is
globally selected using JP1
JP1 Link Posn VCCIO – Front IO
1-2 +3V3
2-3 +2V5
6.1 Samtec 180 connector - U8
The table below details the I/O signals that are available on the Samtec 180 connector along with the FPGA
pin that each connects to.
FPGA
Pin
Signal Connector Pins Signal FPGA
Pin
D10 IO_8N_1 1 2 IO_35N_1 C13
E10 IO_8P_1 3 4 IO_35P_1 D13
F11 IO_19N_1 5 6 IO_30P_1 H13
E11 IO_19P_1 7 8 IO_30N_1 G13
J10 IO_6N_1 9 10 IO_58N_1 M19
H10 IO_6P_1 11 12 IO_58P_1 L19
G10 IO_7N_1 13 14 IO_54N_1 L18
F10 IO_7P_1 15 16 IO_54P_1 K18
G9 IO_1P_1 17 18 IO_34P_1 E13
H9 IO_1N_1 19 20 IO_34N_1 F13
J12 IO_25N_1 21 22 IO_2N_1 E9
H12 IO_25P_1 23 24 IO_2P_1 F9
M13 IO_28N_1 25 26 IO_29P_1 K13
L13 IO_28P_1 27 28 IO_29N_1 J13
L12 IO_21N_1 29 30 IO_20P_1 C11
K12 IO_21P_1 31 32 IO_20N_1 C10
G17 IO_49N_1 33 34 IO_26N_1 F12
F17 IO_49P_1 35 36 IO_26P_1 G12
D16 IO_50P_1 37 38 IO_75P_1 F21
+3V3 39 40 IO_75N_1 G21
+3V3 41 42 Serial_ID
+3V3 43 44 Nc
+5V 45 46 Vref1 Note 1
+5V 47 48 +2V5
Vbatt 49 50 +2V5
+12V 51 52 +2V5
+12V 53 54 -12V
Presence 55 56 TDI
TCK 57 58 TRST
TMS 59 60 TDO
Note 1. Vref1 can be provided by the XRM if required and is applied to banks 0 and 1 in common.
Note 2. TCK, TMS, TDI and TDO are connected to the Coolrunner and not the V2PRO.

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(Continued)
FPGA
Pin
Signal Connector Pins Signal FPGA
Pin
D20 IO_73N_1 61 62 IO_68N_1 H20
C20 IO_73P_1 63 64 IO_68P_1 J20
K17 IO_47N_1 65 66 IO_37N_1 F15
L17 IO_47P_1 67 68 IO_37P_1 E15
J17 IO_48N_1 69 70 IO_38N_1 C15
H17 IO_48P_1 71 72 IO_38P_1 C14
H18 IO_55N_1 73 74 IO_39P_1 L16
G18 IO_55P_1 75 76 IO_39N_1 M16
E17 IO_56P_1 77 78 IO_43N_1 K16
E18 IO_56N_1 79 80 IO_43P_1 J16
K19 IO_59N_1 81 82 IO_44P_1 H16
J19 IO_59P_1 83 84 IO_44N_1 G16
H19 IO_60N_1 85 86 IO_46N_1 M17
G19 IO_60P_1 87 88 IO_46P_1 M18
K21 IO_74P_1 89 90 IO_65N_1 C19
J21 IO_74N_1 91 92 IO_65P_1 D19
E19 IO_64P_1 93 94 IO_37N_0 E28
F19 IO_64N_1 95 96 IO_37P_0 F28
G22 IO_75P_0 97 98 IO_38N_0 C29
F22 IO_75N_0 99 100 IO_38P_0 C28
H27 IO_44N_0 101 102 IO_74P_0 J22
G27 IO_44P_0 103 104 IO_74N_0 K22
J27 IO_43N_0 105 106 IO_39N_0 L27
K27 IO_43P_0 107 108 IO_39P_0 M27
D29 IO_85N_0 109 110 IO_67N_1 L20
E29 IO_85P_0 111 112 IO_67P_1 K20
K29 IO_78N_0 113 114 IO_78N_1 L14
L29 IO_78P_0 115 116 IO_78P_1 K14
BB40 MGT_SYS_TXP23 **117 **118 MGT_SYS_RXP23 BB39
BB41 MGT_SYS_TXN23 **119 **120 MGT_SYS_RXN23 BB38
** - Additional MGT channel provided using these pins
FPGA
Pin
Signal Connector Pins Signal FPGA
Pin
K26 IO_47P_0 121 122 IO_35P_0 C30
L26 IO_47N_0 123 124 IO_35N_0 D30
L24 IO_58N_0 125 126 IO_46P_0 M26
M24 IO_58P_0 127 128 IO_46N_0 M25
E25 IO_56P_0 129 130 IO_48P_0 J26
E26 IO_56N_0 131 132 IO_48N_0 H26
H31 IO_25N_0 133 134 IO_59N_0 J24
J31 IO_25P_0 135 136 IO_59P_0 K24
G33 IO_7P_0 137 138 IO_73N_0 C23
F33 IO_7N_0 139 140 IO_73P_0 D23
E34 IO_2P_0 141 142 IO_60N_0 G24
F34 IO_2N_0 143 144 IO_60P_0 H24
H33 IO_6N_0 145 146 IO_29P_0 K30
J33 IO_6P_0 147 148 IO_29N_0 J30
C32 IO_20P_0 149 150 IO_54N_0 K25
C33 IO_20N_0 151 152 IO_54P_0 L25
H34 IO_1P_0 153 154 IO_64N_0 E24
G34 IO_1N_0 155 156 IO_64P_0 F24
E33 IO_8N_0 157 158 IO_67N_0 K23
D33 IO_8P_0 159 160 IO_67P_0 L23
C24 IO_65P_0 161 162 IO_30N_0 G30
D24 IO_65N_0 163 164 IO_30P_0 H30
E30 IO_34N_0 165 166 IO_55N_0 G25
F30 IO_34P_0 167 168 IO_55P_0 H25
K31 IO_21N_0 169 170 IO_26N_0 G31
L31 IO_21P_0 171 172 IO_26P_0 F31
F26 IO_49N_0 173 174 IO_28N_0 L30
G26 IO_49P_0 175 176 IO_28P_0 M30
E32 IO_19N_0 177 178 IO_68N_0 J23
F32 IO_19P_0 179 180 IO_68P_0 H23

ADM-XP User Manual
ADM-XR-IIPro User Manual
Page 17 of 29 Version 0.2
6.2 RocketIO Multi-Gigabit Transceivers – U13
The ADM-XP provides an additional connection upto the XRM module site which provides 7 MGT connection
from the Virtex II pro device. This enables customisable Mulit Gigabit IO capability using XRM modules
interfacing to the additional samtec QSE-DP connector.
Details of the connections to for the XRM MGT signalling is given below :-
FPGA
Pin
Signal Connector Pins Signal FPGA
Pin
A40 MGT_SYS_TXP2 1 2 MGT_SYS_RXP2 A39
A41 MGT_SYS_TXN2 3 4 MGT_SYS_RXN2 A38
A36 MGT_SYS_TXP3 5 6 MGT_SYS_RXP3 A35
A37 MGT_SYS_TXN3 7 8 MGT_SYS_RXN3 A34
BB4 MGT_SYS_TXP14 9 10 MGT_SYS_RXP14 BB3
BB5 MGT_SYS_TXN14 11 12 MGT_SYS_RXN14 BB2
BB8 MGT_SYS_TXP15 13 14 MGT_SYS_RXP15 BB7
BB9 MGT_SYS_TXN15 15 16 MGT_SYS_RXN15 BB6
A8 MGT_SYS_TXP10 17 18 MGT_SYS_RXP10 A7
A9 MGT_SYS_TXN10 19 20 MGT_SYS_RXN10 A6
A4 MGT_SYS_TXP11 21 22 MGT_SYS_RXP11 A3
A5 MGT_SYS_TXN11 23 24 MGT_SYS_RXN11 A2
BB36 MGT_SYS_TXP22 25 26 MGT_SYS_RXP22 BB35
BB37 MGT_SYS_TXN22 27 28 MGT_SYS_RXN22 BB34

ADM-XP User Manual
ADM-XR-IIPro User Manual
Page 18 of 29 Version 0.2
7 User IO – PMC PN4 (rear panel)
User I/O is presented on the User Connector Pn4 via a standard 64-way PMC connector. This should be
routed via a suitable CMC compliant motherboard to an external I/O adapter.
FPGA Pin Signal Pn4 Pin Pn4 Pin Signal FPGA Pin
AY23 REARIO[1] 1 2 REARIO[0] AW23
AP23 REARIO[3] 3 4 REARIO[2] AR23
AN22 (gclk) REARIO[5] 5 6 REARIO[4] AP22(gclk)
AW24 REARIO[7] 7 8 REARIO[6] AY24
AV24 REARIO[9] 9 10 REARIO[8] AU24
AT24 REARIO[11] 11 12 REARIO[10] AR24
AP24 REARIO[13] 13 14 REARIO[12] AN24
AM24 REARIO[15] 15 16 REARIO[14] AL24
AV26 REARIO[17] 17 18 REARIO[16] AV25
AT25 REARIO[19] 19 20 REARIO[18] AR25
AN25 REARIO[21] 21 22 REARIO[20] AM25
AU26 REARIO[23] 23 24 REARIO[22] AT26
AR26 REARIO[25] 25 26 REARIO[24] AP26
AM26 REARIO[27] 27 28 REARIO[26] AN26
AL25 REARIO[29] 29 30 REARIO[28] AL26
AR27 REARIO[31] 31 32 REARIO[30] AT27
AP27 REARIO[33] 33 34 REARIO[32] AN27
AM27 REARIO[35] 35 36 REARIO[34] AL27
AY29 REARIO[37] 37 38 REARIO[36] AY28
AV28 REARIO[39] 39 40 REARIO[38] AU28
AW30 REARIO[41] 41 42 REARIO[40] AY30
AV30 REARIO[43] 43 44 REARIO[42] AU30
AT30 REARIO[45] 45 46 REARIO[44] AR30
AP30 REARIO[47] 47 48 REARIO[46] AN30
AM30 REARIO[49] 49 50 REARIO[48] AL30
AT31 REARIO[51] 51 52 REARIO[50] AU31
AR31 REARIO[53] 53 54 REARIO[52] AP31
AN31 REARIO[55] 55 56 REARIO[54] AM31
AY33 REARIO[57] 57 58 REARIO[56] AY32
AV32 REARIO[59] 59 60 REARIO[58] AU32
AV33 REARIO[61] 61 62 REARIO[60] AW33
AR33 REARIO[63] 63 64 REARIO[62] AP33

ADM-XP User Manual
ADM-XR-IIPro User Manual
Page 19 of 29 Version 0.2
8 JTAG Access
The XP provides JTAG access for the fabric of the board through J6. This header will connect to Xilinx
download cables using 3V3 signalling levels and has the following devices present in the scan chain :-
hdr_TDI Bridge
2V1500
hdr_TMS
hdr_TCK
hdr_TDO
Target
2VP70/
2VP100
tck,tms
The standard XP is configured with the JTAG chain as shown in the table below.
TDI-> 2V1500
2VP70/100 -> TDO
8.1 JTAG Header (J6)
The table below shows the pin-out for J5, the primary JTAG connector.
Pin Function
1 +3V3
2 GND
3 nc
4 TCK
5 nc
6 TDO
7 TDI
8 POL
9 TMS

ADM-XP User Manual
ADM-XR-IIPro User Manual
Page 20 of 29 Version 0.2
9 XRM-ETH
9.1 Introduction
The XRM-ETH is a general-purpose adaptor for the ADM-XPL and ADM-XRC-II series of PMC modules. It
provides 10/100 Ethernet, RS-232 and general purpose I/O for use with a wide variety of IP.
The XRM-ETH is supplied with two cables to enable connections from the XRM-ETH to 15 way PC COM ports
and RJ45 Ethernet.
XRM-ETH-CAB01 for Ethernet
XRM-ETH-CAB02 for RS232
IMPORTANT. The XRM-ETH REV 1 requires the use of 2.5V signalling over the XRM connector and this
should be checked prior to power up.
PHY
PSU
+3V3 +2V5
Filter
Magnetics Infoport
15w
TX data
RX data
XRM Connector
Max
3388E RS232
2x5 hdr
LEDs
Mictor-38
LVDS I/O
25MHz
9.2 General Purpose I/O
The XRM-ETH provides 18 pairs of differential-capable I/O plus two single-ended signals on a 38 pin Mictor
connector. This connector is compatible with a wide range of Mictor connectors and is well suited to cabling
systems from Precision Interconnect.
The differential pairs are routed on the XRM-ETH with 100 Ohm impedance and are not terminated to enable
direct routing to the FPGA. The user has the choice of using Virtex DCI or DT termination schemes to provide
the correct termination for each signal pair. For DCI termination the resistor pairs R1/R2 and R4/R5 should be
set to the appropriate value for the desired termination value. By default these resistors are all 100Ohm. The
DT scheme can only be used with some Virtex-II PRO devices and provides a fixed 100R termination for
LVDS and LDT I/O standards without the power requirement of the DCI option.
9.3 RS232 I/O
The XRM-ETH provides two transmit and two receive RS232 signals that can be used for connection to other
XPLs or PC COM ports. The supplied cable connects TX0 and RX0 to a standard 15 pin connector suitable for
use with a PC. Baud rates up to 115K are supported.