Alpha Data ADM-XRC-II Pro User manual

ADM-XR-IIPro User Manual
Page 1 of 29 Version 0.2
ADM-XRC-II Pro
(ADM-XP)
Hardware Manual

ADM-XR-IIPro User Manual
Page 2 of 29 Version 0.2
Alpha Data
4 West Silvermills Lane
Edinburgh EH3 5BD
UK
Phone: [phone]
Fax: [phone]
Email: [e-mail]
Alpha Data
226 Airport Parkway
Suite 470
San Jose
CA 95110
USA
Phone: [phone]
Fax: [phone]
Email: [e-mail]
Copyright © 2002, 2003, 2004 Alpha Data Parallel Systems Ltd. All rights reserved.
This publication is protected by Copyright Law, with all rights reserved. No part of this
publication may be reproduced, in any shape or form, without prior written consent from Alpha
Data Parallel Systems Limited.

ADM-XR-IIPro User Manual
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Revision History
Revision Date Comments
0.1 Jul-04 Initial
0.1+ DATA1, DATA8 DATA13 and DATA15 – polarity swapped
DATA38 pin nos swapped in Manual
Clock pins updated for XP pinouts (were XPL pinouts)
0.2 Nov-04 Removed XRM-Pro Debug Section – added XRM ETH

ADM-XP User Manual
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Contents
1INTRODUCTION .......................................................................................................................................... 5
1.1 SPECIFICATIONS ...................................................................................................................................... 5
2INSTALLATION ........................................................................................................................................... 6
2.1 MOTHERBOARD REQUIREMENTS ............................................................................................................... 6
2.2 HANDLING INSTRUCTIONS ........................................................................................................................ 6
2.3 INSTALLING THE ADM-XP ONTO A PMC MOTHERBOARD ........................................................................... 6
2.4 INSTALLING THE ADM-XP IF FITTED TO AN ADC-PMC .............................................................................. 6
3HARDWARE OVERVIEW............................................................................................................................ 7
4LOCAL BUS ARCHITECTURE ................................................................................................................... 9
4.1 LOCAL BUS SIGNALS ................................................................................................................................9
4.2 LOCAL BUS TRANSFERS........................................................................................................................... 9
5TARGET FPGA.......................................................................................................................................... 10
5.1 CONFIGURATION.................................................................................................................................... 10
5.2 CLOCKS ................................................................................................................................................ 10
5.3 SDRAM DDR MEMORY ........................................................................................................................ 12
5.4 DDR2 SSRAM..................................................................................................................................... 13
5.5 FLASH MEMORY .................................................................................................................................... 14
5.6 POWER SUPPLY .................................................................................................................................... 14
6FRONT PANEL I/O .................................................................................................................................... 15
6.1 SAMTEC 180 CONNECTOR - U8 ............................................................................................................. 15
6.2 ROCKETIO MULTI-GIGABIT TRANSCEIVERS – U13 .................................................................................. 17
7USER IO – PMC PN4 (REAR PANEL)...................................................................................................... 18
8JTAG ACCESS .......................................................................................................................................... 19
8.1 JTAG HEADER (J6)............................................................................................................................... 19
9XRM-ETH ................................................................................................................................................... 20
9.1 INTRODUCTION ...................................................................................................................................... 20
9.2 GENERAL PURPOSE I/O ......................................................................................................................... 20
9.3 RS232 I/O............................................................................................................................................ 20
9.4 10/100 ETHERNET ................................................................................................................................21
9.5 INPUT AND OUTPUT ASSIGNMENTS (ADM-XP)........................................................................................ 22
9.5.1 Mictor I/O...................................................................................................................................... 22
9.5.2 DCI Terminations ......................................................................................................................... 22
9.5.3 Ethernet MAC............................................................................................................................... 23
9.5.4 RS232 .......................................................................................................................................... 23
10 USER I/O XRM IO146 FRONT PANEL VARIANT – REV2.0................................................................ 24
11 USER I/O XRM IO146 – ROCKET ......................................................................................................... 27

ADM-XP User Manual
ADM-XR-IIPro User Manual
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1 Introduction
The ADM-XP (XP) is an advanced PCI Mezzanine card (PMC) supporting Xilinx Virtex-II PRO™ (V2PRO)
devices, the latest development in FPGA technology. The XP supports 2VP70, 2VP100 or 2VP125 devices
with two embedded PowerPC processors.
The XP utilises an FPGA PCI bridge developed by Alpha Data supporting 64 bit PCI at up to 66MHz. Future
enhancements will provide compatibility with PCI-X. A high speed multiplexed address and data bus connects
the bridge to the target FPGA.
Memory resources provided on-board include DDR SDRAM, DDR2 SSRAM and flash, all of which are
optimised for direct use by the FPGA using IP and toolkits provided by Xilinx.
Flexible I/O is the key to the ADM-XRC-II series of boards and the XP is compatible with a wide selection of
XRM modules that use the 180 pin Samtec interface.
1.1 Specifications
The ADM-XP supports high performance PCI operation without the need to integrate proprietary cores into the
FPGA.
• Physically conformant to IEEE P1386 Common Mezzanine Card standard
• High performance PCI and asynchronous local bus
• Local bus speeds of up to 80MHz
• Four banks of 256K * 32 bits of DDR2 SSRAM – option for 512K * 32 bits
• Two banks of 64MB DDR SDRAM – option for 128MB
• Two flash devices of 16MB each for bridge and target devices
• User clock programmable between 5MHz and 200MHz
• User front panel adapter with up to 146 free IO signals
• Supports 3.3V PCI or PCIX at 64 bits
• On board 125MHz LVPECL oscillator
• 8 x RocketIO Multi-Gigabit Transceiver Connections (optional) @ 2.5Gb/s

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2 Installation
This chapter explains how to install the ADM-XP onto a PMC motherboard.
2.1 Motherboard requirements
The XP is a 3.3V only PCI device and is not compatible with systems that use 5V signalling.
The XP must be installed in a PMC motherboard that supplies 3.3V power to the PMC connectors. Ensure that
the motherboard satisfies this requirement before powering it up.
2.2 Handling instructions
Observe precautions for preventing damage to components by electrostatic discharge. Personnel handling the
board should take SSD precautions.
Avoid flexing the board.
2.3 Installing the ADM-XP onto a PMC motherboard
Note: This operation should not be performed while the PMC motherboard is powered up.
The ADM-XP must be secured to the PMC motherboard using M2.5 screws in the four holes provided. The
PMC bezel through which the I/O connector protrudes should be flush with the front panel of the PMC
motherboard.
2.4 Installing the ADM-XP if fitted to an ADC-PMC
The ADM-XP can be supplied for use in standard PC systems fitted to an ADC-PMC carrier board. The ADC-
PMC can support up to two ADC-PMC cards whilst maintaining host PC PCI compatibility. If you are using a
ADC-PMC64 refer to the supplied documentation for information on jumper settings. With the ADC-PMC64 all
that is required for installation is a 5V or 3V PCI slot that has enough space to accommodate the full-length
card.
It should be noted that the ADC-PMC uses a standard bridge to provide a secondary PCI bus for the ADM-XP
and that some older BIOS code does not set up these devices correctly. Please ensure you have the latest
version of BIOS appropriate for your machine.

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3 Hardware Overview
The XP is based on the architecture of the ADM-XRC-II with changes to accommodate the enhanced
resources and needs of the Virtex-II PRO device.
The XP follows the architecture of the ADM-XRC series and decouples the “target” FPGA from the “bridge”
device to allow the entire target to be available for user applications. This ensures the user can be up and
running with the minimum of effort and without the complexity of PCI design.
The bridge includes local bus control and monitoring together with flexible configuration options for the bridge
and the target device.
The bridge is capable of 66MHz PCI or PCI-X operation with 64-bit or 32-bit operation. The local bus supports
64-bit at upto 80Mhz
The target FPGA is a Virtex-II-PRO device incorporating FPGA fabric, multi-gigabit transceivers and two
PowerPC cores.
DDR SDRAM, ZBT and flash memory connect to the target FPGA and are supported by Xilinx or third party IP.
IO functionality is provided using XRM modules connecting to the 180 pin SAMTEC QSE and 28 pin SAMTEC
QSE DP connectors.
Virtex II FG676
2V1500
Alpha Data PCI/
PCIX to Local Bus
Bridge
Virtex II Pro - FF1704
2VP70-2VP125
SSRAM
Target
Config
Flash
Clocks
Power
JTAG
Local Bus
SSRAM
64/66 PCI
PCIX 133
146 Bit
IO Bus
MGT Bus
IO Connector/
headers
PN4 IO
DDR2
SDRAM
Target
User
Flash
Bridge
Config
Flash
Config
Control
CPLD
SSRAM SSRAM
DDR2
SDRAM

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The physical layout is shown in the diagram below. The DDR DRAM and DDR2 SSRAM devices are
clam shelled and appear on both sides of the board.
J5 - Jtag Header
J
1
X
R
M
M
E
Z
Z
J
2
J
4
JP1 - VIO Selection
J
3
2V1500
Bridge
2VP70-2VP100
Target
ZBT ZBT
1
Flash
DDR DDR
Flash
M
G
T
Power
Clock
Gen
11
1-2 3.3V
2-3 2.5V
U8 - Samtec 180 Connector
(Select IO)
U13 - Samtec DP Connector
MGT's

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4 Local Bus Architecture
The XP implements a multi-master local bus between the bridge and the target FPGA using a 32 or 64
multiplexed address and data path. The bridge design is asynchronous and allows the local bus to be run
faster or slower than the PCI bus clock to suit the complexity of the user design.
4.1 Local Bus signals
2V1500 PCI
to
Local Bus Bridge
PCI BUS
Target FPGA
2VP70/2VP100
Bank 3
lad[0:63]
lbterm_l
lbe_l[0:7]
lads_l
lblast_l
lready_l
ldreq_l[1:0]
lreset_l
lwrite
ldack_l[1:0]
fhold
fholda
Signalling Virtex2Pro
default - 2.5V (fast)
LVCMOS/LVTTL
lclk AT21
AF1
AF2
AG12
AF7
AD10
AD9
AC10
AC9
Signal Type Purpose
lad[0:63] bidir Address and data bus.
lreset_l unidir Reset to target
lads_l bidir Indicates address phase
lblast_l bidir Indicates last word
lbterm_l bidir Indicates ready and requests new address phase
lready_l bidir Indicates that target accepts or presents new data
lclk unidir Clock to synchronise bridge and target
lbe_l[0:7] bidir Byte qualifiers
dreq_l[0:1] unidir DMA request from target to bridge
dack_l[0:1] unidir DMA acknowledge from bridge to target
fhold unidir Target bus request
fholda unidir Bridge bus acknowledge
4.2 Local Bus Transfers
Please refer to the ADM-XRC SDK Help for Windows supplied with the XP for information on local bus
transfers.

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5 Target FPGA
The target FPGA is a V2PRO 2VP70, 2VP100 or 2VP125 (when available) in an FF1704 package. On the XP,
all of the resources such as DDR, DDR2 SSRAM, IO and Flash are available no matter what device is fitted.
The V2PRO has 8 banks of I/O and banks 0 and 1 provide the User IO to the front panel . The VCCIO voltage
for banks 0 and 1 is selectable using JP1.
JP1 Link Posn VCCIO – Front IO
1-2 +3V3
2-3 +2V5
5.1 Configuration
The target FPGA can be configured using two primary mechanisms. In the first, JTAG from the J6 header can
be used to perform downloading of bit-streams as well as remote debug using tools such as GDB and
ChipScope / Pro. The drawback of using JTAG is that a download cable must be connected to the board.
The XP provides a SelectMAP port between the bridge and the target device mapped to the PCI bus. This
enables very rapid download of configuration data controlled by driver and API code in the host. The maximum
speed that can be achieved is 33 Mbytes per second.
5.2 Clocks
There are a number of clock sources in the XP as shown in the diagram below. Although the ICS307 is shown
connected to the bridge, which may appear differently from the block diagram in the previous section, the
purpose is to provide level translation between the 3.3V output of the clock generator and the 2.5V inputs of
the 2VP70.
ICS307
14.318MHz
OSC
CLKGEN_CLK1
CLKGEN_CLK2
2V1500
PCI
Bridge
2VP70
100/125
Virtex
PRO
LCLK
MCLK
OSC 125MHz
Differential
PCI 33/66 MHz
XRM
Interface
Bank1 Pair 0S/1P
Bank1 Pair 2S/3P
Bank0 Pair 4S/5P
3.3V signalling
2.5V signalling
Control
Bank0 Pair 6S/7P
The V2PRO has a dedicated clock for gigabit operation using the Epson 2121CA 125MHz device. This is input
on GCLK4S/5P in bank 5 and should be received in differential LVDS mode. Because of the routing limitations