Alpha Data ADM-PCIE-8K5-FH User manual

ADM-PCIE-8K5-FH
User Manual
Document Revision: 1 0
16th Feb 2018

ADM-PCIE-8K5-FH User Manual
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ADM-PCIE-8K5-FH User Manual
Table Of Contents
1 Introduction 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 1
2 PCB Information 2
2.1 Physical Specifications ................................................................................................................. 2
2.2 Chassis Requirements ................................................................................................................... 2
2.2.1 PCI E press ............................................................................................................................... 2
2.2.2 Mechanical Requirements ......................................................................................................... 2
2.2.3 Power Requirements ................................................................................................................. 2
2.3 Thermal Performance .................................................................................................................... 3
2.4 Optional Blower ............................................................................................................................. 3
3 Functional Description 4
3.1 Overview ........................................................................................................................................ 4
3.1.1 Switches .................................................................................................................................... 5
3.1.2 LEDs .......................................................................................................................................... 6
3.2 Clocking ......................................................................................................................................... 7
3.2.1 PCIe Reference Clocks ............................................................................................................. 7
3.2.2 Fabric Clock ............................................................................................................................... 7
3.2.3 Programming Clock (EMCCLK) ................................................................................................. 8
3.2.4 SFP+ .......................................................................................................................................... 8
3.2.5 FireFly ........................................................................................................................................ 8
3.2.6 DDR4 SDRAM Reference Clocks .............................................................................................. 9
3.3 PCI E press ................................................................................................................................... 9
3.4 DDR4 SDRAM ............................................................................................................................. 10
3.4.1 MIG IP setup requirements rev2 + newer PCBs ...................................................................... 10
3.5 SFP+ ............................................................................................................................................ 11
3.6 FireFly .......................................................................................................................................... 12
3.7 System Monitor ............................................................................................................................ 13
3.7.1 Automatic Temperature Monitoring .......................................................................................... 13
3.7.2 System Monitor Status LEDs ................................................................................................... 14
3.8 SMA Timing Input ........................................................................................................................ 15
3.9 USB Front Panel Interface ........................................................................................................... 15
3.10 Configuration ............................................................................................................................... 16
3.10.1 Configuration From Flash Memory .......................................................................................... 16
3.10.1.1 Building and Programming Configuration Images ............................................................... 16
3.10.1.2 Custom Flash Write Interface .............................................................................................. 17
3.10.2 Configuration via JTAG ............................................................................................................ 17
3.11 GPIO Option ................................................................................................................................ 18
3.11.1 Direct Connect FPGA Signals .................................................................................................. 18
3.11.2 Low Speed Serial IO ................................................................................................................ 18
3.12 User EEPROM ............................................................................................................................. 19
Appendix A Complete Pinout Table 21
List of Tables
Table 1 Mechanical imensions ..................................................................................................................... 2
Table 2 Available Power By Rail ..................................................................................................................... 2
Table 3 SW1 Switch Functions ....................................................................................................................... 5
Table 4 LE etails ........................................................................................................................................ 6

ADM-PCIE-8K5-FH User Manual
Table 5 PCIe Reference Clocks ..................................................................................................................... 7
Table 6 Fabric Clock ....................................................................................................................................... 8
Table 7 EMCCLK ............................................................................................................................................ 8
Table 8 SFP+ Reference Clocks .................................................................................................................... 8
Table 9 FireFly Reference Clocks .................................................................................................................. 9
Table 10 Memory Reference Clocks ................................................................................................................ 9
Table 11 FireFly Part Numbers ....................................................................................................................... 12
Table 12 Voltage, Current, and Temperature Monitors ................................................................................... 13
Table 13 Status LE efinitions ..................................................................................................................... 14
Table 14 Complete Pinout Table ..................................................................................................................... 21
List of Figures
Figure 1 A M-PCIE-8K5-FH Product Photo .................................................................................................... 1
Figure 2 Thermal Performance ........................................................................................................................ 3
Figure 3 8K5-FH With Attached Optional Blower ............................................................................................. 4
Figure 4 A M-PCIE-8K5-FH Block iagram ................................................................................................... 4
Figure 5 Switches ............................................................................................................................................ 5
Figure 6 LE s .................................................................................................................................................. 6
Figure 7 Clock Topology .................................................................................................................................. 7
Figure 8 SFP Locations .................................................................................................................................. 11
Figure 9 FireFly Locations ............................................................................................................................. 12
Figure 10 Timing Input Schematic ................................................................................................................... 15
Figure 11 SFP Locations ................................................................................................................................. 15
Figure 12 Flash Address Map .......................................................................................................................... 16
Figure 13 GPIO Connector .............................................................................................................................. 18

ADM-PCIE-8K5-FH User Manual
1 Introduction
The A M-PCIE-8K5-FH is a high-performance reconfigurable computing card intended for ata Center
applications, featuring a Xilinx Kintex UltraScale FPGA.
Figure 1 : ADM-PCIE-8K5-FH Product Photo
1 1 Key Features
Key Features
• PCIe Gen1/2/3 x1/2/4/8 capable
• Half-length, full-height x8 PCIe form factor
• Two banks of R4 S RAM 72 bit wide memory (ECC), 16GB (8GB per bank) default rated at 2400MT/s,
32GB option rated at 1866MT/s.
• Four SFP+ sites capable of data rates up to 16.375 Gbps per channel
• Optional Samtec FireFly sites capable of data rates up to 16.375 Gbps per channel (65.5 Gbps per
module). Can be routed to front panel or adjacent card slots.
• Optional SMA/U.FL timing input
• Front Panel JTAG Access via USB port
• FPGA configurable over USB/JTAG and BPI configuration flash
• XCKU115-2FLVA1517I Or XCKU060-2FLVA1517I FPGA
• Voltage, current, and temperature monitoring
• All components rated for operation down to -40 egC
1 2 Order Code
A M-PCIE-8K5-FH(d)(m)(c)(a)(o)(f)(NF)
See http://www.alpha-data.com/pdfs/adm-pcie-8k5-fh.pdf for complete ordering options.
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2 PCB Information
2 1 Physical Specifications
The A M-PCIE-8K5-FH complies with PCI Express CEM revision 3.0.
escription Measure
Total y 111 mm
Total x (Inc. SFP+ Cages) 173 mm
Total z 17.5 mm
Weight 250g
Table 1 : Mechanical Dimensions
2 2 Chassis Requirements
2 2 1 PCI Express
The A M-PCIE-8K5-FH is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes, using the Xilinx Integrated Block for PCI
Express.
2 2 2 Mechanical Requirements
An 8-lane or 16-lane physical PCIe slot is required for mechanical compatibility.
Each A M-PCIE-8K5-FH is shipped with a full height PCIe card bracket installed by default.
2 2 3 Power Requirements
The PCIe Specification permits a standard full-height, half-length PCIe card to dissipate a maximum 75 W of
power, drawn from the PCIe slot. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a
power estimator tool available from Alpha ata. Please contact support@alpha-data com to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.95 VCC_INT + VCCINT_IO + VCC_BRAM 36A
1.8 VCCAUX + VCCAUX_IO VCCO_1.8V 3A
3.3 VCCO_3.3V 2A
1.2 VCCO_1.2V 20A
1.8 MGTVCCAUX 1A
1.0 MGTAVCC 5A
1.2 MGTAVTT 2A
Table 2 : Available Power By Rail
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2 3 Thermal Performance
The A M-PCIE-8K5-FH comes with a heat sink to reduce the heat of the FPGA which is typically the hottest
point on the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will
clear the FPGA design to ensure the card does not overheat. To calculate the FPGA die temperature, take your
application power and multiply by Theta JA from the table below, and add your systems internal ambient
temperature. If you are using the fan provided with the board, you will find Theta JA is approximately 1.6 degC/W
for the board.
The power dissipation can be estimated by using the Alpha ata power estimator in conjuction with the Xilinx
Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. ownload
the UltraScale tool and set the evice to Kintex UltraScale, KU115/KU060, FLVA1517, -2, Extended. Set the
ambient temperature to your system ambient and select User Override for the Effective theta JA and enter the
figure associated with your system LFM in the blank field. Proceed to enter all applicable design elements and
utilization in the following spreadsheet tabs. Next aquire the 8K5-FH power estimator from Alpha ata by
contacting [email protected]. You will then plug in the FPGA power figures along with R4 and SFP
usage to get an estimated board level power dissipation.
The graph below shows Theta JA of the board with two 3.5 watt QSFP loopback connectors inserted.
Figure 2 : Thermal Performance
2 4 Optional Blower
Because it is possible for generic PC chassis to not provide sufficient airflow to cool the FPGA, the
A M-PCIE-8K5-FH is shipped with an uninstalled blower. The blower is optional and can be easily installed with
a Philips screw driver at the discretion of the user. Before screwing in the blower, plug in the small power
connector into the right angle connector along the back edge of the board. The blower hangs off the back of the
PCB outside of the PCIe card envelope.
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Figure 3 : 8K5-FH With Attached Optional Blower
3 Functional Description
3 1 Overview
The A M-PCIE-8K5-FH is a versatile reconfigurable computing platform with a Kintex UltraScale KU115-2I or
KU060-2I FPGA, Gen3x8 PCIe interface, two banks of R4 both 72 bits wide (for 64 bits with 8 bits ECC), two
SFP+ cages capable of up to 16.375Gbps each and any Xilinx supported standard (Ethernet, SRIO, Infiniband,
S I, etc.), a U.FL input for a timing synchronization input, a 12 pin header for general purpose use (clocking,
control pins, debug, etc.) and low speed serial communications, and a robust system monitor. epending on
selected FPGA (XCKU115 only), two optional Samtec FireFly connectors may be fitted, capable of 16.375G/
channel (8 channels).
XCKU115-2
FLVA1517E
(0,4) (5,7)
x8 PCIe Gen3 Edge
SFP Cage
(16.375 Gbps)
SFP Cage
(16.375 Gbps) DDR4 Bank 1
DDR4-2400/1866, 8/16GB ECC
DDR4 Bank 0
DDR4-2400/1866, 8/16GB ECC
System
Monitor
MGT
MGT HPIO
HPIO
HRIO
BPI
Config
x72
x72
MGT
MGTHRIO
USB JTAG 0
Auxiliary IO
(timing, etc)
MAC ID
EEPROM
FireFly
(4x16Gbps)
MGT
FireFly
(4x16Gbps)
SFP Cage
(16.375 Gbps)
SFP Cage
(16.375 Gbps)
Figure 4 : ADM-PCIE-8K5-FH Block Diagram
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3 1 1 Switches
The A M-PCIE-8K5-FH has a quad IP switch SW1, located on the rear side of the board. The function of each
switch in SW1 is detailed below:
Figure 5 : Switches
Switch Factory
efault Function OFF State ON State
SW1-1 OFF User
Switch Pin AV18 = '1' Pin AV18 = '0'
SW1-2 OFF Flash
Lockdown Flash block Lockdown enabled Flash block Lockdown disabled
SW1-3 OFF Service
Mode Regular Operation Firmware update service mode
SW1-4 OFF PCIe Edge
JTAG JTAG to FPGA from USB JTAG to FPGA from PCIe Edge
Table 3 : SW1 Switch Functions
Use IO Standard "LVCMOS33" when constraining the user switch pin.
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3 1 2 LEDs
There are 6 LE s on the A M-PCIE-8K5-FH, 3 of which are general purpose and whose meaning can be
defined by the user. The other four have fixed functions described below:
Figure 6 : LEDs
Comp.
Ref. Function ON State OFF State
4 ONE FPGA is configured FPGA is not configured
2 USER_LE _G0 User defined '0' pin AT19 User defined '1' pin AT19
8 USER_LE _G1 User defined '0' pin AU19 User defined '1' pin AU19
7 USER_LE _R User defined '0' pin AU20 User defined '1' pin AU20
5 Status 0 See Status LE efinitions
6 Status 1 See Status LE efinitions
Table 4 : LED Details
Use IO Standard "LVCMOS33" when driving the user LE pins.
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3 2 Clocking
The A M-PCIE-8K5-FH provides reference clocks for the R4 S RAM banks and the I/O interfaces available
to the user. After a clock is programmed to a certain frequency, that frequency will become the default on
power-up. Any clock out of an Si5338 Clock Synthesizer is re-configurable over I2C. This allows the user to
configure almost any arbitrary clock frequencies during application run time. Please see the Alpha ata API
functions for examples of how this is done.
Note: use "set_property BITSTREAM.CONFIG.UNUSE PIN {Pullnone} [current_design]" to ensure the user
design does not interfere with the I2C interface to the reprogramable clock generator.
SFP0 156.25MHz Factory Default (MGTREFCL 0_127)
FireFly 156.25MHz Factory Default (MGTREFCL 0_232)
Card Edge PCIe
Ref Clock (100MHz)
25MHz
20ppm
Source
Si5338
Clock
Synth
SFP1 156.25MHz Factory Default (MGTREFCL 0_228)
NB6L11S
Fanout
Memory Interface Clock 300Mhz (IO Bank 66)
Memory Interface Clock 300Mhz (IO Bank 44)
FABRIC_CL 200MHz (IO Bank 64)
200MHz, 30ppm
Source
EMCCL 100MHz (IO Bank 65)
100MHz, 10ppm
Source
NB6L11S
Fanout
PCIe Ref Clock_1 (MGTREFCL 0_224)
PCIe Ref Clock_2 (MGTREFCL 1_231)
External Ref Clock Ext Ref Clock (MGTREFCL 1_232)
Figure 7 : Clock Topology
3 2 1 PCIe Reference Clocks
The 8 MGT lanes connected to the PCIe card edge use MGT tiles 224/225 and use the system 100 MHz clock
(PCIE_REFCLK).
A second PCIe reference clock is buffered up from the edge to the FireFly module MGT tiles (231/232).
Signal Target FPGA Input I/O Standard "P" pin "N" pin
PCIE_REFCLK_1 MGTREFCLK1_231 LV S H10 H9
PCIE_REFCLK_2 MGTREFCLK0_224 LV S AT10 AT9
Table 5 : PCIe Reference Clocks
3 2 2 Fabric Clock
The design offers a fabric clock called FABRIC_CLK which is permanently fixed at 200 MHz. This clock is
intended to be used for I ELAY elements in FPGA designs. The fabric clock is connected to a Global Clock (GC)
pin.
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Signal Target FPGA Input I/O Standard pin
FABRIC_CLK IO_L12P_T1U_GC_64 LVCMOS33 AM19
Table 6 : Fabric Clock
3 2 3 Programming Clock (EMCCLK)
An 100MHz clock is fed into the EMCCLK pin to drive the BPI flash device during configuration of the FPGA.
Signal Target FPGA Input I/O Standard pin
REFCLK100M IO_L24P_T3U_N10_EMCCLK_65 LVCMOS18 AJ28
Table 7 : EMCCLK
3 2 4 SFP+
This board houses two 2x1 SFP+ cages, allowing for four total connections. Connectors SFP0 and SFP1 are
located in MGT tile 227, while connectors SFP2 and SFP3 are located in MGT tile 228. See SFP+ for information
on connector locations. Each of the 2x1 SFP+ cages has its own unique clock source. Both clocks are initially set
to 156.25MHz. Note that these clock frequency can be changed to any arbitrary clock frequency up to 312.5MHz
by re-programing the Si5338 reprogrammable clock oscillator via system monitor. This can be done using the
Alpha ata API or over USB with the appropriate Alpha ata Software tools. Any changes made to the default
clock frequency are non-volatile and will be used moving forward.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
GTH_CLK_0 MGTREFCLK0_227 LV S AE8 AE7
GTH_CLK_1 MGTREFCLK0_228 LV S AA8 AA7
SI5328_REFCLK_OUT0 MGTREFCLK1_228 LV S W8 W7
Table 8 : SFP+ Reference Clocks
The SFP+ cages are also located such that they can be clocked from a Si5328 jitter attenuator clock multiplier. If
jitter attenuation is required please see the reference documentation for the Si5328. https://www.silabs.com/
Support%20 ocuments/Technical ocs/Si5328.pdf
The Si5328 is configured with a 114.285MHz oscilator on XA and XB, S A is at FPGA pin L29 (1.8V), SCL is at
FPGA pin L30 (1.8V) with external pull-ups included.
The Si5328 input clock comes from FPGA pins M29 and M30, and includes 100 Ohm AC coupled termination on
the 1.8V FPGA bank.
The Jitter Attenuator is not fitted by default and requires a custom bulid option. Contact [email protected]
for more details.
3 2 5 FireFly
The two optional FireFly sites are located in MGT tile 231 and 232 and can use a variety of reference clocks.
PCIE_REFCLK_1 is a buffered version of the PCIe edge clock. It is converted to LV S through a NB6L11S clock
buffer.
GTH_CLK_2 is default to 156.25MHz. Note that these clock frequency can be changed to any arbitrary clock
frequency up to 312.5MHz by re-programing the Si5338 reprogrammable clock oscillator via system monitor.
This can be done using the Alpha ata API or over USB with the appropriate Alpha ata Software tools. Any
changes made to the default clock frequency are non-volatile and will be used moving forward.
EXT_CLK comes from the GPIO header. The signal is fed directly to the GTH clock with only 10nF capacitors in
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series. Take care to supply a safe clock in on these signals. See Xilinx UG576 for more details acceptable on
GTH reference clocks.
SI5328_REFCLK_OUT1 comes from the onboard jitter attenuator which can feedback a recovered clock from
the GTH channel for particular standards. The Jitter Attenuator is not fitted by default and requires a custom bulid
option. Contact [email protected] for more details.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
SI5328_REFCLK_OUT1 MGTREFCLK0_231 LV S K10 K9
PCIE_REFCLK_1 MGTREFCLK1_231 LV S H10 H9
GTH_CLK_2 MGTREFCLK0_232 LV S F10 F9
EXT_CLK MGTREFCLK1_232 User 10 9
Table 9 : FireFly Reference Clocks
3 2 6 DDR4 SDRAM Reference Clocks
The two banks of R4 S RAM memory each require a separate reference clock, as per Xilinx UltraScale MIG
design guidelines. The reference clocks for these interfaces are detailed below:
Both clocks are 300MHz by default.
Signal Target FPGA Input I/O Standard "P" pin "N" pin
MEM_CLK_0 IO_L11_T1U_GC_66
IFF_HSTL_I_12
(or SSTL) G16 G15
MEM_CLK_1 IO_L11_T1U_GC_44
IFF_HSTL_I_12
(or SSTL) AM22 AN22
Table 10 : Memory Reference Clocks
3 3 PCI Express
The A M-PCIE-8K5-FH is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes. The FPGA drives these lanes directly
using the Integrated PCI Express block from Xilinx. Negotiation of PCIe link speed and number of lanes used is
generally automatic and does not require user intervention.
PCI Express reset (PERST#) connected to the FPGA at both pins AE15 and AM15.
The other pin assignments for the high speed lanes are provided in the pinout attached to the Complete Pinout
Table
Note:
ifferent motherboards/backplanes will benefit from different RX equalization schemes within the PCIe IP core
provided by Xilinx. Alpha ata recommends using the following setting if a user experiences link errors or
training issues with their system: within the IP core generator, change the mode to "Advanced" and open the
"GT Settings" tab, change the "form factor driven insertion loss adjustment" from "Add-in Card" to
"Chip-to-Chip" (See Xilinx PG239 for more details).
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3 4 DDR4 SDRAM
Two banks of R4 S RAM memory are soldered down to the board. While the factory default is 8GB/per bank,
16GB/bank is also supported through a build variant. Please see Order Code for all order options. The memory
interface is 72-bit wide data (64 data + 8 ECC). Maximum signaling rate is 2400 MT/s for 16GB total and
1688MT/s with 32GB total.
Memory solutions are available from the Xilinx Memory Interface Generator (MIG) and must use Vivado 2016.1
or later. An example project with traffic generator is available with purchase of the A M-PCIE-8K5 S K.
However, all the information required to generate a complete MIG IP core is available within this user guide.
3 4 1 MIG IP setup requirements rev2 + newer PCBs
8GB per bank, rev2 and newer PCB
• Vivado 2016.3 IP Catalog: R4 S RAM (MIG)
• Memory evice Interface Speed (ps): 937
• Reference Input Clock speed (ps): 3332
• Custom Parts ata File: Checked, use 'adm-pcie-'8k5_custom_parts_2400.csv' downloaded from
www.alpha-data.com/8k5
• Configuration: Components
• Memory Part: CUSTOM_ BI_MT40A1G8PM-083E
• ata Mask and BI: NO M BI WR R
• IO locations found in appendix
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3 5 SFP+
Four SFP+ cages are available at the front panel. All cages are capable of housing either active optical or
passive copper SFP compatible components. The communication interface can run at up to 16.375Gbps per
channel. These cages are ideally suited for 10 Gigabit Ethernet or any other protocol supported by the Xilinx
GTH Transceivers. Please see Xilinx User Guide UG576 for more details on the capabilities of the transceivers.
Both SFP+ cages have control signals connected to the FPGA. Their connectivity is detailed in the Complete
Pinout Table at the end of this document. The notation used in the pin assignments is SFP0 through SFP3 with
locations clarified in the diagram below.
Figure 8 : SFP Locations
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3 6 FireFly
If the 8K5-FH is ordered with the XCKU115 FPGA, two optional FireFly receptacles near the front of the board
allow for additional 16.375G lanes. The FireFly connections have the same capabilities as the SFP+ cages, with
much greater lane width. There are 4 lanes per FireFly, adding up to 8 lanes at 16.375Gps resulting in 131Gbps
total bandwidth. This can be configured in a ring orientation as depicted in the image below, or allow for MPO
style breakouts at the front panel (full-height panel only).The A M-PCIE-8K5-FH support both copper and optical
FireFly modules. More information on FireFly can be found at https://www.samtec.com/optics/optical-cable/
mid-board/firefly
Both FireFly sites have control signals connected to the FPGA. Their connectivity is detailed in the Complete
Pinout Table at the end of this document. The notation used in the pin assignments is FireFly0 and FireFly1 with
locations clarified in the diagram below.
Figure 9 : FireFly Locations
The FireFly sites can fit a number of standard cables. Below is a list of supported part numbers. Contact Alpha
ata or your local Samtec representative for more details.
escription Part Number Manufacturer
56G/40G (4x14/10) FireFly Optical Transceiver ECUO B04 14 017 0 2 1 1 01 Samtec
65.5G (4x16.375) FireFly Copper Cable ECUE 08 020 T2 FF B4 1 1 Samtec
Table 11 : FireFly Part Numbers
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3 7 System Monitor
The A M-PCIE-8K5-FH monitors temperature, voltage, and current of the board to check on the operation of the
board. The monitoring is implemented using an Atmel AVR microcontroller. All readings and measurements are
available to the FPGA, enabling detailed power consumption reporting.
Control algorithms within the microcontroller automatically check line voltages and on board temperatures and
shares makes the information available to the FPGA over a dedicated serial interface built into the Alpha ata
reference design package (sold separately). The information can also be accessed directly from the
microcontroller over the USB interface on the upper USB port on the front panel or via the IPMI interface
available at the PCIe card edge.
Index Monitors Purpose/ escription
A C00 12.0V Board Input Supply
A C01 3.3V Board Input Supply
A C02 3.3V Board Input Auxilary Power Supply
A C03 3.3V Internally generated supply
A C04 2.5V Clock Voltage Supply
A C05 1.8V FPGA IO Voltage (VCCO)
A C06 1.8V Transceiver Power (AVCC_AUX)
A C07 1.2V R4 S RAM and FPGA memory I/O
A C08 1.2V Transceiver Power (AVTT)
A C09 1.0V Transceiver Power (AVCC)
A C10 0.95V FPGA Core Supply (VccINT)
A C11 0.6V R4 Termination Voltage
A C12 12V_I 12V input current in amps
A C13 3.3V_I 3.3V input current in amps
TMP00 uC Micro-controller on-die temperature
TMP01 Board temperature sensor on PCB
TMP02 NC Not Connected
TMP03 FPGA FPGA on-die temperature
Table 12 : Voltage, Current, and Temperature Monitors
3 7 1 Automatic Temperature Monitoring
Automatic over-temperature shutdown was added as a function external to the FPGA from sn409 and onwards.
The over-temperature shutdown function will clear the FPGA program if the die temperature exceeds 100
degrees Celsius.
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3 7 2 System Monitor Status LEDs
LE s 6 (Red) and 5 (Green) indicate the card health status.
LEDs Status
Green Running and no alarms
Green + Red Standby (Powered off)
Flashing Green + Flashing Red
(together) Attention - critical alarm active
Flashing Green + Flashing Red
(alternating) Service Mode
Flashing Green + Red Attention - alarm active
Red Missing application firmware or
invalid firmware
Flashing Red FPGA configuration cleared to
protect board
Table 13 : Status LED Definitions
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3 8 SMA Timing Input
All cards are fitted with a U.FL connector that can be utilized as a timing input. This connector can be accessed
with a U.FL cable internal to the chassis, or cabled to an SMA or similar connector at the front panel. Contact
[email protected] for front panel connector options.
Input is on FPGA pin AL30, IOSTAN AR LVCMOS18
The signal is isolated through a optical isolator part number ACPL-M61L with a 739 ohm of series resistance.
Figure 10 : Timing Input Schematic
3 9 USB Front Panel Interface
The A M-PCIE-8K5-FH houses two USB ports. The upper connector connects to the system monitor system,
while the lower connector allows programming of the FPGA.
For convenience the FPGA can be configured directly from the lower USB connection on the front panel. The
A M-PCIE-8K5-FH utilizes the igilent USB-JTAG converter box which is supported by the Xilinx software tool
suite. Simply connect a micro-USB AB type cable between the upper A M-PCIE-8K5-FH USB port and a host
computer with Vivado installed. Vivado Hardware Manager will automatically recognize the FPGA and allow you
to configure the FPGA and the BPI configuration PROM.
The upper USB connector is used to directly access the system monitor system. All voltages, currents,
temperatures, and non-volatile clock configuration settings can be accessed using Alpha ata's avr2util software
at this interface.
The location of the upper (J11) and lower (J15) ports are clarified in the diagram below.
Figure 11 : SFP Locations
Avr2util is downloadable here:
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ADM-PCIE-8K5-FH User Manual
ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/archive/avr2util-win-2.5.0.zip
The USB driver install file is downloadable here:
ftp://ftp.alpha-data.com/pub/firmware/utilities/windows/archive/avr2_usb_inf.zip
Use "avr2util.exe /?" to see all options.
For example "avr2util.exe /usbcom com4 display-sensors" will display all sensor values.
3 10 Configuration
There are two main ways of configuring the FPGA on the A M-PCIE-8K5-FH:
• From Flash memory, at power-on, as described in Section 3.10.1
• Using USB cable connected at the lower USB port found on the front panel. This process is described in
Section 3.10.2
3 10 1 Configuration From Flash Memory
The FPGA can be automatically configured at power-on from a 1 Gbit BPI flash memory device (Micron part
number MT28GU01GAAA1EGC-0SIT). This Flash device is divided into two regions of 64 MiByte each, where
each region is sufficiently large to hold an uncompressed bitstream for a KU115 FPGA.
The A M-PCIE-8K5-FH is shipped with a bitstream, corresponding to the "dma_demo" FPGA design from the
A M-PCIE-8K5-FH S K, programmed into region 1 and "reg_access" programmed into region 0. This permits
basic confidence and performance testing to be performed on a board without needing to program anything into
the Flash memory. Alpha ata recommends that region 0 is used as a fallback image; this permits relatively
simple recovery, without requiring direct programming of the FPGA over the front panel USB connection, in the
event of programming a "bad" bitstream into region 1.
The flash address map is as detailed below:
Data Region
Region 0
Failsafe
(64 MiB)
Region 1
Default
(64 MiB)
Start Address (Bytes)
0x000_0000
0x400_0000
Figure 12 : Flash Address Map
At power-on, the FPGA attempts to configure itself automatically in BPI mode from region 1 unless the
configuration header on the bitstream ultilizes multi-boot. Multibook and ICAP can be used to selected between
the two configuration regions to be loaded into the FPGA. See Xilinx UG570 MultiBoot for details.
The Lockdown function of the Flash device is controlled via switch SW1-2. When SW1-2 is OFF, any blocks in
the Flash whose Lockdown flag is set are write-protected. The factory default for the Lockdown flag of all Flash
blocks is clear, so that any block in the Flash can be written.
3 10 1 1 Building and Programming Configuration Images
Generate a bitfile with these constraints (see XAPP587):
• set_property BITSTREAM.GENERAL.COMPRESS {TRUE} [ current_design ]
• set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN { IV-1} [current_design]
• set_property BITSTREAM.CONFIG.BPI_SYNC_MO E {TYPE1} [current_design]
• set_property BITSTREAM.CONFIG.UNUSE PIN {Pullnone} [current_design]
• set_property BITSTREAM.CONFIG.OVERTEMPSHUT OWN Enable [current_design]
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