Alpha Data ADM-PCIE-8K5-FH User manual

ADM-PCIE-8K5-FH
User Manual
Document Revision: 1 0
16th Feb 2018

ADM-PCIE-8K5-FH User Manual
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ADM-PCIE-8K5-FH User Manual
Table Of Contents
1 Introduction 1
1.1 Key Features ................................................................................................................................. 1
1.2 Order Code .................................................................................................................................... 1
2 PCB Information 2
2.1 Physical Specifications ................................................................................................................. 2
2.2 Chassis Requirements ................................................................................................................... 2
2.2.1 PCI E press ............................................................................................................................... 2
2.2.2 Mechanical Requirements ......................................................................................................... 2
2.2.3 Power Requirements ................................................................................................................. 2
2.3 Thermal Performance .................................................................................................................... 3
2.4 Optional Blower ............................................................................................................................. 3
3 Functional Description 4
3.1 Overview ........................................................................................................................................ 4
3.1.1 Switches .................................................................................................................................... 5
3.1.2 LEDs .......................................................................................................................................... 6
3.2 Clocking ......................................................................................................................................... 7
3.2.1 PCIe Reference Clocks ............................................................................................................. 7
3.2.2 Fabric Clock ............................................................................................................................... 7
3.2.3 Programming Clock (EMCCLK) ................................................................................................. 8
3.2.4 SFP+ .......................................................................................................................................... 8
3.2.5 FireFly ........................................................................................................................................ 8
3.2.6 DDR4 SDRAM Reference Clocks .............................................................................................. 9
3.3 PCI E press ................................................................................................................................... 9
3.4 DDR4 SDRAM ............................................................................................................................. 10
3.4.1 MIG IP setup requirements rev2 + newer PCBs ...................................................................... 10
3.5 SFP+ ............................................................................................................................................ 11
3.6 FireFly .......................................................................................................................................... 12
3.7 System Monitor ............................................................................................................................ 13
3.7.1 Automatic Temperature Monitoring .......................................................................................... 13
3.7.2 System Monitor Status LEDs ................................................................................................... 14
3.8 SMA Timing Input ........................................................................................................................ 15
3.9 USB Front Panel Interface ........................................................................................................... 15
3.10 Configuration ............................................................................................................................... 16
3.10.1 Configuration From Flash Memory .......................................................................................... 16
3.10.1.1 Building and Programming Configuration Images ............................................................... 16
3.10.1.2 Custom Flash Write Interface .............................................................................................. 17
3.10.2 Configuration via JTAG ............................................................................................................ 17
3.11 GPIO Option ................................................................................................................................ 18
3.11.1 Direct Connect FPGA Signals .................................................................................................. 18
3.11.2 Low Speed Serial IO ................................................................................................................ 18
3.12 User EEPROM ............................................................................................................................. 19
Appendix A Complete Pinout Table 21
List of Tables
Table 1 Mechanical imensions ..................................................................................................................... 2
Table 2 Available Power By Rail ..................................................................................................................... 2
Table 3 SW1 Switch Functions ....................................................................................................................... 5
Table 4 LE etails ........................................................................................................................................ 6

ADM-PCIE-8K5-FH User Manual
Table 5 PCIe Reference Clocks ..................................................................................................................... 7
Table 6 Fabric Clock ....................................................................................................................................... 8
Table 7 EMCCLK ............................................................................................................................................ 8
Table 8 SFP+ Reference Clocks .................................................................................................................... 8
Table 9 FireFly Reference Clocks .................................................................................................................. 9
Table 10 Memory Reference Clocks ................................................................................................................ 9
Table 11 FireFly Part Numbers ....................................................................................................................... 12
Table 12 Voltage, Current, and Temperature Monitors ................................................................................... 13
Table 13 Status LE efinitions ..................................................................................................................... 14
Table 14 Complete Pinout Table ..................................................................................................................... 21
List of Figures
Figure 1 A M-PCIE-8K5-FH Product Photo .................................................................................................... 1
Figure 2 Thermal Performance ........................................................................................................................ 3
Figure 3 8K5-FH With Attached Optional Blower ............................................................................................. 4
Figure 4 A M-PCIE-8K5-FH Block iagram ................................................................................................... 4
Figure 5 Switches ............................................................................................................................................ 5
Figure 6 LE s .................................................................................................................................................. 6
Figure 7 Clock Topology .................................................................................................................................. 7
Figure 8 SFP Locations .................................................................................................................................. 11
Figure 9 FireFly Locations ............................................................................................................................. 12
Figure 10 Timing Input Schematic ................................................................................................................... 15
Figure 11 SFP Locations ................................................................................................................................. 15
Figure 12 Flash Address Map .......................................................................................................................... 16
Figure 13 GPIO Connector .............................................................................................................................. 18

ADM-PCIE-8K5-FH User Manual
1 Introduction
The A M-PCIE-8K5-FH is a high-performance reconfigurable computing card intended for ata Center
applications, featuring a Xilinx Kintex UltraScale FPGA.
Figure 1 : ADM-PCIE-8K5-FH Product Photo
1 1 Key Features
Key Features
• PCIe Gen1/2/3 x1/2/4/8 capable
• Half-length, full-height x8 PCIe form factor
• Two banks of R4 S RAM 72 bit wide memory (ECC), 16GB (8GB per bank) default rated at 2400MT/s,
32GB option rated at 1866MT/s.
• Four SFP+ sites capable of data rates up to 16.375 Gbps per channel
• Optional Samtec FireFly sites capable of data rates up to 16.375 Gbps per channel (65.5 Gbps per
module). Can be routed to front panel or adjacent card slots.
• Optional SMA/U.FL timing input
• Front Panel JTAG Access via USB port
• FPGA configurable over USB/JTAG and BPI configuration flash
• XCKU115-2FLVA1517I Or XCKU060-2FLVA1517I FPGA
• Voltage, current, and temperature monitoring
• All components rated for operation down to -40 egC
1 2 Order Code
A M-PCIE-8K5-FH(d)(m)(c)(a)(o)(f)(NF)
See http://www.alpha-data.com/pdfs/adm-pcie-8k5-fh.pdf for complete ordering options.
Page 1Introduction
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ADM-PCIE-8K5-FH User Manual
2 PCB Information
2 1 Physical Specifications
The A M-PCIE-8K5-FH complies with PCI Express CEM revision 3.0.
escription Measure
Total y 111 mm
Total x (Inc. SFP+ Cages) 173 mm
Total z 17.5 mm
Weight 250g
Table 1 : Mechanical Dimensions
2 2 Chassis Requirements
2 2 1 PCI Express
The A M-PCIE-8K5-FH is capable of PCIe Gen 1/2/3 with 1/2/4/8 lanes, using the Xilinx Integrated Block for PCI
Express.
2 2 2 Mechanical Requirements
An 8-lane or 16-lane physical PCIe slot is required for mechanical compatibility.
Each A M-PCIE-8K5-FH is shipped with a full height PCIe card bracket installed by default.
2 2 3 Power Requirements
The PCIe Specification permits a standard full-height, half-length PCIe card to dissipate a maximum 75 W of
power, drawn from the PCIe slot. Power estimation requires the use of the Xilinx XPE spreadsheet and/or a
power estimator tool available from Alpha ata. Please contact support@alpha-data com to obtain this tool.
The power available to the rails calculated using XPE are as follows:
Voltage Source Name Current Capability
0.95 VCC_INT + VCCINT_IO + VCC_BRAM 36A
1.8 VCCAUX + VCCAUX_IO VCCO_1.8V 3A
3.3 VCCO_3.3V 2A
1.2 VCCO_1.2V 20A
1.8 MGTVCCAUX 1A
1.0 MGTAVCC 5A
1.2 MGTAVTT 2A
Table 2 : Available Power By Rail
Page 2 PCB Information
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ADM-PCIE-8K5-FH User Manual
2 3 Thermal Performance
The A M-PCIE-8K5-FH comes with a heat sink to reduce the heat of the FPGA which is typically the hottest
point on the card. The FPGA die temperature must remain under 100 degrees Celsius or the system monitor will
clear the FPGA design to ensure the card does not overheat. To calculate the FPGA die temperature, take your
application power and multiply by Theta JA from the table below, and add your systems internal ambient
temperature. If you are using the fan provided with the board, you will find Theta JA is approximately 1.6 degC/W
for the board.
The power dissipation can be estimated by using the Alpha ata power estimator in conjuction with the Xilinx
Power Estimator (XPE) downloadable at http://www.xilinx.com/products/technology/power/xpe.html. ownload
the UltraScale tool and set the evice to Kintex UltraScale, KU115/KU060, FLVA1517, -2, Extended. Set the
ambient temperature to your system ambient and select User Override for the Effective theta JA and enter the
figure associated with your system LFM in the blank field. Proceed to enter all applicable design elements and
utilization in the following spreadsheet tabs. Next aquire the 8K5-FH power estimator from Alpha ata by
contacting [email protected]. You will then plug in the FPGA power figures along with R4 and SFP
usage to get an estimated board level power dissipation.
The graph below shows Theta JA of the board with two 3.5 watt QSFP loopback connectors inserted.
Figure 2 : Thermal Performance
2 4 Optional Blower
Because it is possible for generic PC chassis to not provide sufficient airflow to cool the FPGA, the
A M-PCIE-8K5-FH is shipped with an uninstalled blower. The blower is optional and can be easily installed with
a Philips screw driver at the discretion of the user. Before screwing in the blower, plug in the small power
connector into the right angle connector along the back edge of the board. The blower hangs off the back of the
PCB outside of the PCIe card envelope.
Page 3PCB Information
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ADM-PCIE-8K5-FH User Manual
Figure 3 : 8K5-FH With Attached Optional Blower
3 Functional Description
3 1 Overview
The A M-PCIE-8K5-FH is a versatile reconfigurable computing platform with a Kintex UltraScale KU115-2I or
KU060-2I FPGA, Gen3x8 PCIe interface, two banks of R4 both 72 bits wide (for 64 bits with 8 bits ECC), two
SFP+ cages capable of up to 16.375Gbps each and any Xilinx supported standard (Ethernet, SRIO, Infiniband,
S I, etc.), a U.FL input for a timing synchronization input, a 12 pin header for general purpose use (clocking,
control pins, debug, etc.) and low speed serial communications, and a robust system monitor. epending on
selected FPGA (XCKU115 only), two optional Samtec FireFly connectors may be fitted, capable of 16.375G/
channel (8 channels).
XCKU115-2
FLVA1517E
(0,4) (5,7)
x8 PCIe Gen3 Edge
SFP Cage
(16.375 Gbps)
SFP Cage
(16.375 Gbps) DDR4 Bank 1
DDR4-2400/1866, 8/16GB ECC
DDR4 Bank 0
DDR4-2400/1866, 8/16GB ECC
System
Monitor
MGT
MGT HPIO
HPIO
HRIO
BPI
Config
x72
x72
MGT
MGTHRIO
USB JTAG 0
Auxiliary IO
(timing, etc)
MAC ID
EEPROM
FireFly
(4x16Gbps)
MGT
FireFly
(4x16Gbps)
SFP Cage
(16.375 Gbps)
SFP Cage
(16.375 Gbps)
Figure 4 : ADM-PCIE-8K5-FH Block Diagram
Page 4 Functional Description
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ADM-PCIE-8K5-FH User Manual
3 1 1 Switches
The A M-PCIE-8K5-FH has a quad IP switch SW1, located on the rear side of the board. The function of each
switch in SW1 is detailed below:
Figure 5 : Switches
Switch Factory
efault Function OFF State ON State
SW1-1 OFF User
Switch Pin AV18 = '1' Pin AV18 = '0'
SW1-2 OFF Flash
Lockdown Flash block Lockdown enabled Flash block Lockdown disabled
SW1-3 OFF Service
Mode Regular Operation Firmware update service mode
SW1-4 OFF PCIe Edge
JTAG JTAG to FPGA from USB JTAG to FPGA from PCIe Edge
Table 3 : SW1 Switch Functions
Use IO Standard "LVCMOS33" when constraining the user switch pin.
Page 5Functional Description
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ADM-PCIE-8K5-FH User Manual
3 1 2 LEDs
There are 6 LE s on the A M-PCIE-8K5-FH, 3 of which are general purpose and whose meaning can be
defined by the user. The other four have fixed functions described below:
Figure 6 : LEDs
Comp.
Ref. Function ON State OFF State
4 ONE FPGA is configured FPGA is not configured
2 USER_LE _G0 User defined '0' pin AT19 User defined '1' pin AT19
8 USER_LE _G1 User defined '0' pin AU19 User defined '1' pin AU19
7 USER_LE _R User defined '0' pin AU20 User defined '1' pin AU20
5 Status 0 See Status LE efinitions
6 Status 1 See Status LE efinitions
Table 4 : LED Details
Use IO Standard "LVCMOS33" when driving the user LE pins.
Page 6 Functional Description
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