In order to indicate the validity of the seven
data lines, another signal must be presented by
the host mputer to verify that it is placing valid
inrmation on them. This stbe signal is ac
cepted on the same trace on the edge nnector
as the serial input data stream. (NOTE: The
comete pinout of this edge connector may
be und in the Appendix.)
The DATA SOBE signal is represented by
a transition of this line om the L LOW level
to the L HIGH leve This transition may occur
at the same time that the seven data lines are
changed, thus permiing the entire output of
the host on a single eight bit por Upon receipt
of the DATA STROBE transition to the HIGH
state, the SPRINTER 40 will pause r approxi
mately 25 microseconds to allow the signals to
stabilize on the inteace cable, sample the state
of the seven data lines to determine the de
being sent by the host, and then assert the BUSY
signal as an active HIGH level to the hos The
host mputer must not alter the state of these
lines until the BUSY signal is removed (i.e. re
tued to the LOW level) by the SPRINT. As
long as this sequence is honored, any type of in
terce may be inserted between the host and
the SPRINTER 40. Just prior to the removal of the
BUSY signal, another signal known as acknowl
edge (ACK) is asserted by the SPRINT. This in
dicates that the fuished byte of data has been
processed. The ACK signal is removed simulta
neously with the removal of BUSY. ACK is fur
nished as an active LOW signal which retus to
a HIGH level upon the removal of BUSY. Thus
both a pulse type signal (ACK) and a level type
signal (BUSY) are available as a basis r n
structing other exteal parallel interces.
These signals were developed r a very fast
series of printers, to o
ccur very rapidly and to be
implemented in dis
ete hardware logi
In the
SPRINT
ntroller
,
these signals are im
p
le
mented in a mi
oprogrammed interce section
which
p
ermits the same hardware to be used in
several di
erent types of inteaces
.
As a result
the timing sequence is expanded althou
g
h the
same relative relations are presen Since most
host mputers implement their parallel inter
ces in software
they will be
q
uite m
p
at
-
ible with this technique. The basic software
se
q
uence llo
w
ed in the host should be
as llows
1. M
onitor the BUSY signal until it is inactive. I
f
it fails to be
me inactive
,
manual rrective
action must be taken.
2.
Remove the
D
AT A STROBE signa
3
.
A
ssert the
D
AT
A
STROBE si
g
nal and the
seven data signals.
4.
Pause approximately
3
0 microse nds.
5.
Confirm receipt of data by re gnition of the
BUSY signa
6
.
I
f BUSY not asserted
,
printer is inactive or in
-
terce has iled. Take apppriate manual
re very action.
7.
If BUSY is asserted
,
begin preparation of
next data byte
,
or next line of characters
,
as
appropriate.
8
. Retu to step
1
unless
a
ll
p
rintin
g
has been
ac mplished.
During
step 7, when
the data
om the ho
s
t i
s
either being bu
ered or prin
t
ed
, b
oth the host
and SPRINT
can be wor
k
ing in parallel. In
t
his
manner the host has the maximum time to pre
p
are
t
he next data byte while the SPRINT i
s
p
rocessing the previous da
t
a byte
,
or printin
g
t
he mpleted line of chara
c
ters.
T
his is an im
p
ortan
t
aspect
,
particularly when graphics inr
ma
t
ion is being transmitted to the
S
PRINT
.
The BUSY signal and
AC
K si
g
nals are pro
duced by an open llector circuit to prevent
p
roblems in the event that they are exteally
p
ulled low
.
This circuit is essentially a
47
0 ohm
resistor
t
ied to the SPRI
NT 5
volt supply and
pulled to ground by a transistor when these
signals are low. There is an additional invisible
clamping diode
b
uilt into the
t
ransistor which
nnects the lle
c
tor to
t
he main D
C s
upply
ca
p
acitor. In the event that an indu
c
tive load
should be
nnected
t
o either
o
f these lines
,
t
hese diodes would route any voltage excursions
over approximately
35
volts into the SPRI
NT
p
ower supply. While this is a highly unlikly pros
pect, the
interface designer should be aware of
its presence.
This inteace port can normally
b
e n
nected with proper cables to
a'Centronic type
inteace ca
b
le
,
although
j
umpers ma
y
have to
be modified in some of these units to produce or
honor the proper polarity of the BUSY or DAT
A
STROBE signals.
I
n most cases these inteaces
can be directly used without modification o
f
resi
dent BASIC software and system PRINT intrinsics.
The active Centronics ca
b
le contains slight hard
ware to standardize these signals to the highest
speed hard
w
are version of these signals.
7
