AMLOGIC S905D3 Service manual

S905D3
Quick Reference Manual
Revision: 0.6
Release Date: 2019–07–25
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Copyright
©2019 Amlogic. All rights reserved. No part of this document may be reproduced, transmitted, tran-
scribed, or translated into any language in any form or by any means without the written permission of
Amlogic.
Trademarks
, and other Amlogic icons are trademarks of Amlogic companies. All other trademarks and
registered trademarks are property of their respective holders.
Disclaimer
Amlogic may make improvements and/or changes in this document or in the product described in this
document at any time.
This product is not intended for use in medical, life saving, or life sustaining applications.
Circuit diagrams and other information relating to products of Amlogic are included as a means of illus-
trating typical applications. Consequently, complete information sufficient for production design is not
necessarily given. Amlogic makes no representations or warranties with respect to the accuracy or
completeness of the contents presented in this document.
Contact Information
●● Website: www.amlogic.com
●● Pre-sales consultation: [email protected]
●● Technical support: [email protected]
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Revision History
Version 0.6(2019–07–23)
This is the sixth release. Compare with the last version, the following part is added:
●● 1
The following parts are modified:
Section Change Description
4.4,4.5 Remove BT656 related signals.
Version 0.5(2019–05–14)
This is the fifth release. Compare with the last version, the following part has been modified:
Section Change Description
2,3Remove DVP description, update Neural Network Processing Unit description
Version 0.4(2019–04–10)
This is the forth release. Compare with last version the following part has been modified:
Section Change Description
3Update SOC diagram
4.3 Update eARC_N, eARC_P description, remove VDDAO_0V8.
5.5.1 Update RPD, RPU, add Note
5.7.1 Add Note part for Table 5-1.
5.8 Updated Table 5-18
5.10 Update Note5, remove VDDAO_0V8
5.11 Update Table and Note part
Compare with last version the following topic is new added:
●● 5.9
Version 0.3(2019-03-10)
This is the third release. Compare with last version the following part has been modified:
Section Change Description
4.3，5.2 Correct typo
5.3 Add note
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Version 0.2(2019-02-26)
This is the second release. Compare with last version the following topic is new added:
●● Pin Order
●● Pin Description
●● Recommended Operation Conditions
●● Thermal Resistance
●● Ethernet Timing
Compare with last version the following part has been modified:
Section Change Description
5.11 Add Power consumption data
Version 0.1(2019-02-21)
This is the first release. Compare with last version the following part has been modified:
Section Change Description
5.5.1 Correct typo
Preliminary Version(2019-01-30)
This is the preliminary release.
S905D3 Quick Reference Manual Revision History
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S905D3 Quick Reference Manual Contents
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Contents
Revision History ................................................................................................................................. ii
1About This Document....................................................................................................................1
2General Description.......................................................................................................................2
3Features Summary ........................................................................................................................3
4Pinout Specification ......................................................................................................................8
4.1 Pin-Out Diagram (top view) ....................................................................................................8
4.2 Pin Order ...............................................................................................................................8
4.3 Pin Description ....................................................................................................................13
4.4 Pin Multiplexing Tables ........................................................................................................25
4.5 Signal Description................................................................................................................31
5Operating Conditions ..................................................................................................................39
5.1 Absolute Maximum Ratings .................................................................................................39
5.2 Recommended Operating Conditions ..................................................................................39
5.3 Ripple Voltage Specifications...............................................................................................40
5.4 Thermal Resistance.............................................................................................................40
5.5 DC Electrical Characteristics................................................................................................41
5.5.1 Normal GPIO Specifications (For DIO_xmA) ..............................................................41
5.5.2 Open Drain GPIO Specifications (For DIO_OD) .........................................................42
5.5.3 DDR3/DDR3L/DDR4/LPDDR3/LPDDR4 SDRAM Specifications................................43
5.6 Recommended Oscillator Electrical Characteristics..............................................................44
5.7 Timing Information ...............................................................................................................45
5.7.1 I2C Timing Specification ............................................................................................45
5.7.2 EMMC/SD Timing Specification .................................................................................46
5.7.3 NAND Timing Specification ........................................................................................51
5.7.4 SPICC Timing Specification .......................................................................................53
5.7.5 SPIFC Timing Specification........................................................................................54
5.7.6 Ethernet Timing Specification.....................................................................................55
5.7.7 Audio Timing Specification .........................................................................................58
5.7.8 PDM Timing Specification ..........................................................................................61
5.7.9 UART Timing Specification ........................................................................................62
5.8 Power On Config .................................................................................................................62
5.9 Power On Reset ..................................................................................................................63
5.10 Recommended Power on sequence...................................................................................64
5.11 Power Consumption...........................................................................................................65
5.12 Storage and Baking Conditions ..........................................................................................66
6Mechanical Dimensions ..............................................................................................................67
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1 About This Document
This document is applicable to S905D3 SoC series, please contact your Amlogic sales representative
for more detail.
S905D3 Quick Reference Manual 1 About This Document
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2 General Description
S905D3 is an advanced application processor designed for hybrid OTT/IP Set Top Box (STB) and
high-end media box applications. It integrates a powerful CPU/GPU subsystem, a powerful NPU(Neu-
ral Network Processing Unit)Optional,a secured 4K video CODEC engine and a best-in-class HDR image
processing pipeline with all major peripherals to form the ultimate low power multimedia AP.
The main system CPU is a quad-core ARM Cortex-A55 CPU with unified L3 cache to improve system
performance. In addition, the Cortex-A55 CPU includes the NEON SIMD co-processor to improve soft-
ware media processing capability.
The graphic subsystem consists of two graphic engines and a flexible video/graphic output pipeline.
The ARM G31 MP2 GPU handles all OpenGL ES 3.2 Vulkan 1.0 and OpenCL 2.0 graphic programs,
while the 2.5D graphics processor handles additional scaling, alpha, rotation and color space conver-
sion operations. Together, the CPU and GPU handle all operating system, networking, user-interface
and gaming related tasks. The video output pipeline includes Dolby Visionoptional, HDR10 +, HDR10,
HLG and PRIME HDR processing, BT.709/BT.2020/BT.2100 processing, motion adaptive edge en-
hancing de-interlacing, flexible programmable scalar, and many picture enhancement filters before
passing the enhanced image to the video output ports.
Amlogic Video Engine (AVE-10) off-loads the Cortex-A55 CPUs from all video CODEC processing. It
includes dedicated hardware video decoder and encoder. AVE-10 is capable of decoding 4Kx2K reso-
lution video at 60fps with complete Trusted Video Path (TVP) for secure applications and supports full
formats including MVC, MPEG-1/2/4, VC-1/WMV, AVS, AVS +, AVS2 RealVideo, MJPEG streams,
H.264, H265-10, VP9 and also JPEG pictures with no size limitation. The independent encoder is able
to encode in JPEG or H.265/H.264 up to 1080p at 60fps.
S905D3 integrates all standard audio/video input/output interfaces including a HDMI2.1 transmitter
with 3D, Dynamic HDR(w/EMP), CEC and HDCP2.2, ALLM(Auto Low Latency Mode) support,stereo
audio DAC, a CVBS output,4-lane MIPI DSI interface,2–lane MIPI CSI interface, multiple TDM, PCM,
I2S and SPDIF digital audio input/output interfaces, and 8 channel far-field PDM digital microphone
(DMIC) inputs. It also has build-in Voice Activity Detection(VAD)module for ultra-low power operations
during system standby.
S905D3 also integrates a set of functional blocks for digital TV broadcasting streams. The built-in two
demux can process the TV streams from the serial and paralleltransport stream input interface, which
can connect to external tuner/demodulator.
The processor has rich advanced network and peripheral interfaces, including a 10/100/1000M Ether-
net MAC with RGMII, 10/100M Ethernet PHY,a set of multi-PHY for USB2, USB3 and PCIe,and multi-
ple SDIO/SD card controllers, UART, I2C, high-speed SPI and PWMs.
Standard development environment utilizing GNU/GCC Android tool chain is supported. Please con-
tact your AMLOGIC sales representative for more information.
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3 Features Summary
CPU Sub-system
●● Quad core ARM Cortex-A55 CPU
●● ARMv8-A architecture with Neon and Crypto extensions
●● 8-stage in-order full dual issue pipeline
●● Unified system L3 cache
●● Build-in Cortex-M4Optional core for always on processing
●● Build-in Cortex-M3 core for system control processing
●● Advanced TrustZone security system
●● Application based traffic optimization using internal QoS-based switching fabrics
Neural Network Processing Unit(NPU)Optional
●● 1.2 TOPS NN inference accelerator
●● Supports all major deep learning frameworks including TensorFlow and Caffe
3D Graphics Processing Unit
●● ARM G31 MP2 GPU
●● 4-wide warps, dual texture pipe, 2x 4-wide execution engines (EE)
●● Concurrent multi-core processing
●● OpenGL ES 3.2, Vulkan 1.1 and OpenCL 2.0 support
S905D3
Memory InterfaceSystem Interface
Video Output Unit
De-interlacer
Scalar
HDRProcessing
HDMI 2.1
Core and Fabric
TrustZone Security
Input/Output Interfaces
USB
HOST
USB
OTGSDIO3.0I2CUARTSPIPWM
SAR
ADC
SDXC/
SDHC/
SD
L3Cache
MMU
Audio Output Unit
TDM / I2S
HDMI 2.1
SPDIF
IR
Rx & Tx
PLLsPMUJTAG
Temp
SensorPerfMon
Audio Input Unit
SPDIF
DDR3/4/3L &
LPDDR3/4 Memory
Controller
eMMC/NAND Flash
Controller
SPI
Flash Controller
2.5D Graphic
Processing
Crypto
Engine
Secured NV
storage
Power
Management
Processor
10/100M
Ethernet
PHY
CVBS
TDM / I2S
Cortex-A55
32KB I/D-Cache
NEON/VFP
Cortex-A55
32KB I/D-Cache
NEON/VFP
Cortex-A55
32KB I/D-Cache
NEON/VFP
Cortex-A55
32KB I/D-Cache
NEON/VFP
PDM x8
Stereo Audio DAC
Enhancement
L2 Cache
MMU
Mali-G31 MP2
Video Input Unit
2x TsinDemux
MIPI-CSI
MIPI DSI
Giga
Ethernet
MAC
USB SS/
PCIe 2.0
USB 3.0 / PCIe 2.0 *
ISO7816
* Supported configuration: PCIe 2.0 port + USB 2.0 Host, or USB 3.0 port witout PCIe
A06ST01
NPU#
Cortex-M4#AVE-10
VAD
# Optional for special part no.
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2.5D Graphics Processor
●● Fast bitblt engine with dual inputs and single output
●● Programmable raster operations (ROP)
●● Programmable polyphase scaling filter
●● Supports multiple video formats 4:2:0, 4:2:2 and 4:4:4 and multiple pixel formats (8/16/24/32 bits
graphics layer)
●● Fast color space conversion
●● Advanced anti-flickering filter
Crypto Engine
●● AES/ block cipher with 128/256 bits keys, standard 16 bytes block size and streaming ECB,
CBC and CTR modes
●● TDES block cipher with ECB and CBC modes supporting 64 bits key for DES and 192 bits key
for 3DES
●● SM4 block cipher with ECB, CBC, CTR modes
●● Hardware crypto key-ladder operation and DVB-CSA for transport stream encryption
●● Built-in hardware True Random Number Generator (TRNG), CRC and SHA-1/SHA-2/HMAC
SHA engine
Video/Picture CODEC
●● Amlogic Video Engine (AVE) with dedicated hardware decoders and encoders
●● Support multi-video decoder up to 4x1080P@60fps
●● Supports multiple “secured” video decoding sessions and simultaneous decoding and encoding
●● Video/Picture Decoding
−VP9 Profile-2 up to 4Kx2K@60fps
−H.265 HEVC [email protected] up to 4Kx2K@60fps
−AVS2-P2 Profile up to 4Kx2K@60fps
−H.264 AVC [email protected] up to 4Kx2K@30fps
−MPEG-4 ASP@L5 up to 1080P@60fps (ISO-14496)
−WMV/VC-1 SP/MP/AP up to 1080P@60fps
−AVS-P16(AVS+) /AVS-P2 JiZhun Profile up to 1080P@60fps
−MPEG-2 MP/HL up to 1080P@60fps (ISO-13818)
−MPEG-1 MP/HL up to 1080P@60fps (ISO-11172)
−RealVideo 8/9/10 up to 1080P@60fps
−Multiple language and multiple format sub-title video support
−MJPEG and JPEG unlimited pixel resolution decoding (ISO/IEC-10918)
−Supports JPEG thumbnail, scaling, rotation and transition effects
−Supports *.mkv,*.wmv,*.mpg, *.mpeg, *.dat, *.avi, *.mov, *.iso, *.mp4, *.rm and *.jpg file
formats
●● Video/Picture Encoding
−Independent JPEG and H.264 encoder with configurable performance/bit-rate
−JPEG image encoding
−H.265/H.264 video encoding up to 1080P@60fps with low latency
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8th Generation Advanced Amlogic TruLife Image Engine
●● Supports Dolby Visionoptional, HDR10+, HDR10, HLG and Technicolor HDR processing
●● Motion compensated noise reduction and 3D digital noise reduction for random noise
●● Block noise, mosquito noise, spatial noise, contour noise reduction
●● Motion compensated and motion adaptive de-interlacer
●● Edge interpolation with low angle protection and processing
●● 3:2/2:2 pulldown and Video on Film (VOF) detection and processing
●● Smart sharpness with SuperScaler technology including de-contouring, de-ring, LTI, CTI, de-
jaggy, peaking
●● Dynamic non-Linear contrast enhancement
●● All dimension multiple regions smart color management including blue/green extension, flesh-
tone correction, wider gamut for video
●● 2 video planes and 3 graphics planes hardware composer
●● Independent HDR re-mapping of video and graphic layer
Video Input/Output Interface
●● MIPI-CSI camera interface with 2 lanes
●● Built-in HDMI 2.1 transmitter including both controller and PHY supporting eARC,CEC, Dynamic
HDR and HDCP 2.2, 4Kx2K@60 max resolution output
●● CVBS 480i/576i standard definition output
●● Supports all standard SD/HD/FHD video output formats: 480i/p, 576i/p, 720p, 1080i/p and
4Kx2K
●● 4-lane MIPI DSI interface, resolution up to 1920*1080
Audio Decoder and Input/Output
●● Supports MP3, AAC, WMA, RM, FLAC, Ogg,Dolby DigitalOptional, Dolby Digital PlusOptional, DTSOp-
tional and programmable with 7.1/5.1 down-mixing
●● Low-power VAD
●● Built-in serial digital audio SPDIF/IEC958 input/output and PCM input/output, SPDIF supports
192KHz 16/24/32bit stereo
●● 3 built-in TDM/PCM/I2S ports with TDM/PCM mode up to 384kHz x 32bits x 16ch or 96kHz x
32bits x 32ch and I2S mode up to 384kHz x 32bits x 16ch
●● Digital microphone PDM input with programmable CIC, LPF & HPF, support up to 8 DMICs
●● Built-in stereo audio DAC
●● Supports concurrent dual audio stereo channel output with combination of analog+PCM or I2S
+PCM
Memory and Storage Interface
●● 32-bit DRAM memory interface with dual ranks and max 4GB total address space
●● Compatible with JEDEC standard DDR3-2133 /DDR3L-2133 /DDR4-3200 /LPDDR3-2133
/LPDDR4-3200 SDRAM
●● Supports SLC/MLC/TLC NAND Flash with 60-bit ECC, compatible to Toshiba toggle mode in ad-
dition to ONFI 2.2
●● SDSC/SDHC/SDXC card and SDIO interface with 1-bit and 4-bit data bus width supporting spec
version 2.x/3.x/4.x DS/HS modes up to UHS-I SDR104
●● eMMC and MMC card interface with 1/4/8-bit data bus width fully supporting spec version 5.0
HS400
●● Supports serial 1, 2 or 4-bit NOR Flash via SPI interface
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●● Built-in 4k bits One-Time-Programming memory for key storage
Network
●● Integrated IEEE 802.3 10/100/1000M Ethernet MAC with RGMII interface
●● Integrate 10/100M Ethernet PHY interface
●● WiFi/IEEE802.11 & Bluetooth supporting via PCIE/SDIO /USB/UART/PCM
●● Network interface optimized for mixed WIFI and BT traffic
Digital Television Interface
●● One serial and one parallel Transport stream (TS) input interface with built-in demux processor
for connecting to external digital TV tuner/demodulator
●● Built-in PWM, I2C and SPI interfaces to control tuner and demodulator
●● Integrated ISO 7816 smart card controller
Integrated I/O Controllers and Interfaces
●● One USB XHCI OTG 2.0 port
●● One USB SS and PCIE 2.0 combo port up to 5Gbps, which supports 2 configurations:
−1 USB 2.0 Host + 1 PCIe
−1 USB3.0 (No PCIe)
●● Multiple PWM, UART, I2C and SPI interface with slave select
●● Programmable IR remote input/output controllers
●● Built-in 10bit SAR ADC with 4 input channels
●● A set of General Purpose IOs with built-in pull up and pull down
System, Peripherals and Misc. Interfaces
●● Integrated general purpose timers, counters, DMA controllers
●● 24 MHz crystal input
●● Embedded debug interface using ICE/JTAG
●● Integrated Power On Reset(POR) module
Power Management
●● Multiple internal power domains controlled by software
●● Multiple sleep modes for CPU, system, DRAM, etc.
●● Multiple internal PLLs for DVFS operation
●● Multi-voltage I/O design for 1.8V and 3.3V
●● Power management auxiliary processor in a dedicated always-on (AO) power domain that can
communicate with an external PMIC
Security
●● Trustzone based Trusted Execution Environment (TEE)
●● Secured boot, encrypted OTP, encrypted DRAM with memory integrity checker, hardware key
ladder and internal control buses and storage
●● Separated secure/non-secure Entropy true RNG
●● Pre-region/ID memory security control and electric fence
●● Hardware based Trusted Video Path (TVP) , video watermarking and secured contents (needs
SecureOS software)
●● Secured IO and secured clock
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Package
●● FCBGA, 16.1mmx14.3mm, 0.6mm ball pitch, RoHS compliant
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4 Pinout Specification
4.1 Pin-Out Diagram (top view)
Figure 4-1 Pinout Diagram(topview)
4.2 Pin Order
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BALL # NET NAME
A1 DDR_DQ31
A3 DDR_DQ30
A5 DVSS
A7 DDR_DQSP3
A11 DDR_DQ25
A15 GPIOA_8
A19 GPIOA_0
A24 GPIOC_4
A28 DVSS
A32 PCIE_RXP
A36 USBOTG_B_VBUS
A40 USBOTG_B_DM
A42 ENET_TXP
A44 ENET_RXP
A46 DVSS
C1 DVSS
C3 DDR_DQ18
C5 DDR_DQ29
C7 DDR_DQSN3
C9 DDR_DQ28
C11 DVSS
C13 DVSS
C15 GPIOA_9
C17 GPIOA_3
C19 GPIOA_1
C21 GPIOC_2
C24 GPIOC_5
C26 GPIOC_0
C28 GPIOC_6
C30 PCIE_CLK_p
C32 PCIE_RXN
C34 PCIE_TXN
C36 DVSS
C38 USBHOST_A_DM
C40 USBOTG_B_DP
C42 ENET_TXN
BALL # NET NAME
C44 ENET_RXN
C46 HDMITX_2P
E3 DDR_DQ19
E5 DDR_DQ17
E7 DVSS
E9 DDR_DQ26
E13 DDR_DQ24
E15 GPIOA_6
E17 GPIOA_2
E19 DVSS
E21 GPIOC_3
E24 DVSS
E26 VDDIO_C
E28 GPIOC_1
E30 PCIE_CLK_n
E32 DVSS
E34 PCIE_TXP
E36 ENET_EXTRES
E38 USBHOST_A_DP
E40 DVSS
E42 DVSS
E44 HDMITX_2N
E46 DVSS
G1 DDR_DQ21
G3 DDR_DQ20
G5 DVSS
G8 DDR_DQ27
G11 DDR_DQM3
G13 DVSS
G16 GPIOA_4
G19 VDDIO_A
G22 GPIOA_11
G25 GPIOA_10
G28 GPIOC_7
G31 USB_TXRTUNE
G34 HDMI_REXT
BALL # NET NAME
G37 GPIOH_8
G42 DVSS
G44 HDMITX_1P
G46 HDMITX_1N
H40 GPIOH_6
J3 DDR_DQSN2
J5 DDR_DQSP2
J13 GPIOA_5
J16 GPIOA_7
J19 GPIOA_12
J22 GPIOA_15
J25 DVSS
J28 PCIE_REXT
J31 USBOTG_B_ID
J34 HDMI_CEXT
J37 GPIOH_1
J42 DVSS
J44 HDMITX_0N
J46 HDMITX_0P
K7 DDR_DQM2
K9 DDR_DQ16
K11 DVSS
L1 DDR_DQ23
L3 DVSS
L5 DDR_DQ22
L13 VDDQ
L16 GPIOA_13
L19 DVSS
L22 GPIOA_14
L25 DVSS
L28 HCSL_REXT
L31 DVSS
L34 DVSS
L37 GPIOH_0
L40 GPIOH_3
L42 HDMITX_CKN
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BALL # NET NAME
L44 HDMITX_CKP
N3 DVSS
N5 AC_35
N7 DVSS
N9 AC_31
N11 DVSS
N15 VDDQ
N36 GPIOH_2
N38 VMID
N40 AVSS_AUDIO
N42 LOLP
N44 DVSS
P13 VDDQ
P18 DVSS
P20 DVSS
P22 DVSS
P24 AVDD18_PCIE
P26 AVDD18_ENET
P28 AVDD33_USB
P30 DVSS
P32 AVSS_HPLL
P34 DVSS
R1 DVSS
R3 AC_34
R5 AC_20
R15 DVSS
R42 LORN
R44 LOLN
R46 LORP
T7 AC_38
T9 DDR_RSTn
T11 DVSS
T36 REFP
T38 CVBS_RSET
T40 CVBS_VREF
U3 AC_21
U5 DVSS
BALL # NET NAME
U13 VDDQ
U15 DVSS
U17 DVSS
U19 VDD_DDR
U21 DVSS
U23 DVSS
U25 AVDD18_USB
U27 ENET_ATP
U29 AVSS_ENETPLL
U31 NC
U33 DVSS
U42 DVSS
U44 CVBS_IOUT
W1 AC_33
W3 AC_29
W5 AC_32
W7 AC_37
W9 AC_30
W11 PVREF
W36 CVBS_COMP
W38 GPIOH_5
W40 GPIOH_4
W42 DVSS
W44 eARC_P
W46 eARC_N
Y14 VDDQ
Y16 DVSS
Y18 DVSS
Y20 VDD_EE
Y22 DVSS
Y24 AVSS_HCSL
Y26 DVSS
Y28 AVDD0V8_USB_PCIE
Y30 AVDD0V8_HDMI
Y32 AVDD18_HDMI
Y34 AVSS_CVBS
AA3 AC_25
BALL # NET NAME
AA5 AC_24
AA42 NC
AA44 NC
AB7 AC_5
AB9 AC_4
AB11 PZQ
AB36 CSI_CLKA_P
AB38 GPIOH_7
AB40 DVSS
AC1 AC_28
AC3 DVSS
AC5 AC_22
AC13 DVSS
AC15 VDDQ
AC17 DVSS
AC19 VDD_DDR
AC21 DVSS
AC23 DVSS
AC25 DVSS
AC27 VDD_EE
AC29 DVSS
AC31 AVDD18_AUDIO
AC33 AVDD18_CVBS
AC42 DVSS
AC44 NC
AC46 NC
AE3 DVSS
AE5 AC_26
AE7 AC_6
AE9 AC_7
AE11 AC_12
AE36 CSI_CLKA_N
AE38 CSI_D1N
AE40 CSI_D1P
AE42 DSI_CLKN
AE44 DSI_CLKP
AF14 DVSS
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BALL # NET NAME
AF16 VDDQ
AF18 DVSS
AF20 DVSS
AF22 AVSS_AMPLL
AF24 DVSS
AF26 VDD_EE
AF28 VDD_EE
AF30 DVSS
AF32 AVDD18_MIPICSI
AF34 AVDD18_MIPIDSI
AG1 AC_15
AG3 AC_14
AG5 AC_23
AG42 DVSS
AG46 DSI_D0P
AH7 AC_13
AH9 DVSS
AH11 AC_9
AH14 AVDD_DDRPLL
AH17 VDD_DDR
AH20 VDDCPU
AH23 AVDD18_DPLL
AH26 VDD_EE
AH29 DVSS
AH32 DVSS
AH36 DVSS
AH38 CSI_D0N
AH40 CSI_D0P
AH44 DSI_D0N
AK1 AC_11
AK3 AC_10
AK5 DVSS
AK13 DVSS
AK15 VDDQ
AK17 DVSS
AK19 VDDCPU
AK21 VDDCPU
BALL # NET NAME
AK23 DVSS
AK25 DVSS
AK27 VDD_EE
AK29 VDD_EE
AK31 DVSS
AK33 AVDD18_SARADC
AK42 DVSS
AK44 DSI_D1P
AK46 DSI_D1N
AL7 AC_17
AL9 AC_16
AL11 AC_3
AL36 DSI_CEXT
AL38 DSI_R1K
AL40 DSI_R600
AM3 AC_2
AM5 AC_36
AM27 VDD_EE
AM42 DSI_D2N
AM44 DSI_D2P
AN14 DVSS
AN16 DVSS
AN18 DVSS
AN20 VDDCPU
AN22 VDDCPU
AN24 DVSS
AN30 DVSS
AN32 VDD18_AO_XTAL
AN34 DVSS
AP1 AC_0
AP3 DVSS
AP5 AC_18
AP7 DDR_DQM1
AP9 DDR_DQ15
AP11 AC_1
AP27 VDD_EE
BALL # NET NAME
AP36 GPIOAO_0
AP38 GPIOAO_1
AP40 DVSS
AP42 DVSS
AP44 DSI_D3P
AP46 DSI_D3N
AT3 DVSS
AT5 AC_8
AT13 DVSS
AT15 DVSS
AT17 VDDCPU
AT19 VDDCPU
AT21 VDDCPU
AT23 DVSS
AT25 DVSS
AT27 VDD_EE
AT33 DVSS
AT42 GPIOAO_8
AT44 GPIOAO_9
AU9 DDR_DQ12
AU11 DVSS
AU29 DVSS
AU31 DVSS
AU36 GPIOAO_10
AU38 GPIOE_2
AU40 GPIOAO_2
AV1 DVSS
AV3 DDR_DQ14
AV5 DDR_DQ11
AV42 RESET_N
AV44 GPIOAO_6
AV46 GPIOAO_7
AW14 DVSS
AW16 VDDCPU
AW18 VDDCPU
AW20 VDDCPU
AW22 VDDCPU
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BALL # NET NAME
AW24 DVSS
AW26 VDD_EE
AW28 DVSS
AW30 DVSS
AW32 VDDIO_Z
AW34 VDDIO_H
AY3 DDR_DQ10
AY5 DDR_DQ9
AY7 DVSS
AY9 DDR_DQ13
AY11 DVSS
AY36 VDDIO_AO
AY38 SARADC_CH0
AY40 SARADC_CH1
AY42 SYS_OSCIN
AY44 DVSS
BB1 DDR_DQSP1
BB3 DDR_DQSN1
BB5 DVSS
BB10 DVSS
BB13 DVSS
BB16 DVSS
BB19 BOOT_10
BB22 DVSS
BB25 DVSS
BB28 GPIOE_0
BB31 DVSS
BB34 GPIOX_8
BB42 GPIOZ_15
BB44 SYS_OSCOUT
BB46 DVSS
BC7 DVSS
BC36 GPIOZ_1
BC38 SARADC_CH2
BC40 SARADC_CH3
BD3 DDR_DQ8
BD5 DDR_DQ7
BALL # NET NAME
BD10 DVSS
BD13 GPIOAO_5
BD16 GPIOAO_4
BD19 BOOT_11
BD22 DVSS
BD25 DVSS
BD28 GPIOE_1
BD31 GPIOX_10
BD34 GPIOX_9
BD42 GPIOZ_12
BD44 GPIOZ_13
BF1 DDR_DQ6
BF3 DVSS
BF5 DDR_DQ5
BF7 DVSS
BF10 DVSS
BF13 GPIOAO_3
BF16 GPIOAO_11
BF19 BOOT_15
BF22 BOOT_9
BF25 VDDIO_X
BF28 TEST_N
BF31 GPIOX_17
BF34 GPIOX_11
BF36 GPIOZ_0
BF39 GPIOZ_14
BF42 GPIOZ_9
BF44 GPIOZ_11
BF46 GPIOZ_10
BH1 DVSS
BH3 DDR_DQ4
BH5 DVSS
BH7 DVSS
BH9 BOOT_1
BH11 BOOT_3
BH13 BOOT_4
BALL # NET NAME
BH17 BOOT_6
BH19 DVSS
BH21 VDDIO_BOOT
BH24 BOOT_8
BH26 GPIOX_19
BH28 GPIOX_14
BH30 GPIOX_13
BH32 DVSS
BH34 GPIOX_3
BH36 DVSS
BH38 DVSS
BH40 GPIOX_7
BH42 GPIOZ_6
BH44 DVSS
BH46 GPIOZ_8
BK1 DDR_DQM0
BK3 DDR_DQSN0
BK5 DDR_DQ3
BK7 DDR_DQ1
BK9 BOOT_0
BK11 BOOT_2
BK13 DVSS
BK15 DVSS
BK17 BOOT_7
BK19 BOOT_14
BK21 BOOT_12
BK24 DVSS
BK26 GPIOX_15
BK28 GPIOX_12
BK30 GPIOX_16
BK32 GPIOX_1
BK34 GPIOX_2
BK38 GPIOX_5
BK40 GPIOX_6
BK42 GPIOZ_2
BK44 GPIOZ_5
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BALL # NET NAME
BK46 GPIOZ_7
BM1 DDR_DQSP0
BM3 DVSS
BM5 DDR_DQ2
BM7 DDR_DQ0
BM11 DVSS
BALL # NET NAME
BM15 BOOT_5
BM19 BOOT_13
BM24 GPIOX_18
BM28 DVSS
BM32 GPIOX_0
BM36 GPIOX_4
BALL # NET NAME
BM40 DVSS
BM42 GPIOZ_3
BM44 GPIOZ_4
BM46 DVSS
4.3 Pin Description
The S905D3 application processor pin assignment is described in the following table.
Net Name Type Default
Pull UP/
DN
Description Power
Domain
If
Unused
GPIOZ - Refer to Table 4-1 for functional multiplex information.
GPIOZ_0 DIO Up General purpose input/output bank Z signal 0 VDDIO_Z NC
GPIOZ_1 DIO Up General purpose input/output bank Z signal 1 VDDIO_Z NC
GPIOZ_2 DIO Up General purpose input/output bank Z signal 2 VDDIO_Z NC
GPIOZ_3 DIO Up General purpose input/output bank Z signal 3 VDDIO_Z NC
GPIOZ_4 DIO Up General purpose input/output bank Z signal 4 VDDIO_Z NC
GPIOZ_5 DIO Up General purpose input/output bank Z signal 5 VDDIO_Z NC
GPIOZ_6 DIO Up General purpose input/output bank Z signal 6 VDDIO_Z NC
GPIOZ_7 DIO Up General purpose input/output bank Z signal 7 VDDIO_Z NC
GPIOZ_8 DIO Up General purpose input/output bank Z signal 8 VDDIO_Z NC
GPIOZ_9 DIO Down General purpose input/output bank Z signal 9 VDDIO_Z NC
GPIOZ_10 DIO Down General purpose input/output bank Z signal
10
VDDIO_Z NC
GPIOZ_11 DIO Down General purpose input/output bank Z signal
11
VDDIO_Z NC
GPIOZ_12 DIO Down General purpose input/output bank Z signal
12
VDDIO_Z NC
GPIOZ_13 DIO Down General purpose input/output bank Z signal
13
VDDIO_Z NC
GPIOZ_14 OD 5V Z General purpose input/output bank Z signal
14
VDDIO_Z NC
GPIOZ_15 OD 5V Z General purpose input/output bank Z signal
15
VDDIO_Z NC
VDDIO_Z P - Power supply for GPIO bank Z - NC
GPIOA - Refer to Table 4-2 for functional multiplex information.
GPIOA_0 DIO Down General purpose input/output bank A signal 0 VDDIO_A NC
GPIOA_1 DIO Down General purpose input/output bank A signal 1 VDDIO_A NC
GPIOA_2 DIO Down General purpose input/output bank A signal 2 VDDIO_A NC
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Net Name Type Default
Pull UP/
DN
Description Power
Domain
If
Unused
GPIOA_3 DIO Down General purpose input/output bank A signal 3 VDDIO_A NC
GPIOA_4 DIO Down General purpose input/output bank A signal 4 VDDIO_A NC
GPIOA_5 DIO Down General purpose input/output bank A signal 5 VDDIO_A NC
GPIOA_6 DIO Down General purpose input/output bank A signal 6 VDDIO_A NC
GPIOA_7 DIO Down General purpose input/output bank A signal 7 VDDIO_A NC
GPIOA_8 DIO Down General purpose input/output bank A signal 8 VDDIO_A NC
GPIOA_9 DIO Down General purpose input/output bank A signal 9 VDDIO_A NC
GPIOA_10 DIO Down General purpose input/output bank A signal
10
VDDIO_A NC
GPIOA_11 DIO Down General purpose input/output bank A signal
11
VDDIO_A NC
GPIOA_12 DIO Down General purpose input/output bank A signal
12
VDDIO_A NC
GPIOA_13 DIO Down General purpose input/output bank A signal
13
VDDIO_A NC
GPIOA_14 DIO Up General purpose input/output bank A signal
14
VDDIO_A NC
GPIOA_15 DIO Up General purpose input/output bank A signal
15
VDDIO_A NC
VDDIO_A P - Power supply for GPIO bank A - NC
BOOT - Refer to Table 4-3 for functional multiplex information.
BOOT_0 DIO UP General purpose input/output bank BOOT
signal 0
VDDIO_
BOOT
NC
BOOT_1 DIO UP General purpose input/output bank BOOT
signal 1
VDDIO_
BOOT
NC
BOOT_2 DIO UP General purpose input/output bank BOOT
signal 2
VDDIO_
BOOT
NC
BOOT_3 DIO UP General purpose input/output bank BOOT
signal 3
VDDIO_
BOOT
NC
BOOT_4 DIO UP General purpose input/output bank BOOT
signal 4
VDDIO_
BOOT
NC
BOOT_5 DIO UP General purpose input/output bank BOOT
signal 5
VDDIO_
BOOT
NC
BOOT_6 DIO UP General purpose input/output bank BOOT
signal 6
VDDIO_
BOOT
NC
BOOT_7 DIO UP General purpose input/output bank BOOT
signal 7
VDDIO_
BOOT
NC
BOOT_8 DIO UP General purpose input/output bank BOOT
signal 8
VDDIO_
BOOT
NC
BOOT_9 DIO UP General purpose input/output bank BOOT
signal 9
VDDIO_
BOOT
NC
BOOT_10 DIO UP General purpose input/output bank BOOT
signal 10
VDDIO_
BOOT
NC
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Net Name Type Default
Pull UP/
DN
Description Power
Domain
If
Unused
BOOT_11 DIO UP General purpose input/output bank BOOT
signal 11
VDDIO_
BOOT
NC
BOOT_12 DIO DOWN General purpose input/output bank BOOT
signal 12
VDDIO_
BOOT
NC
BOOT_13 DIO DOWN General purpose input/output bank BOOT
signal 13
VDDIO_
BOOT
NC
BOOT_14 DIO UP General purpose input/output bank BOOT
signal 14
VDDIO_
BOOT
NC
BOOT_15 DIO UP General purpose input/output bank BOOT
signal 15
VDDIO_
BOOT
NC
VDDIO_
BOOT
P - Power supply for GPIO bank BOOT - To
VDDIO_
BOOT
GPIOC - Refer to Table 4-4 for functional multiplex information.
GPIOC_0 DIO UP General purpose input/output bank C signal 0 VDDIO_C NC
GPIOC_1 DIO UP General purpose input/output bank C signal 1 VDDIO_C NC
GPIOC_2 DIO UP General purpose input/output bank C signal 2 VDDIO_C NC
GPIOC_3 DIO UP General purpose input/output bank C signal 3 VDDIO_C NC
GPIOC_4 DIO UP General purpose input/output bank C signal 4 VDDIO_C NC
GPIOC_5 DIO UP General purpose input/output bank C signal 5 VDDIO_C NC
GPIOC_6 DIO UP General purpose input/output bank C signal 6 VDDIO_C NC
GPIOC_7 OD 5V Z General purpose input/output bank C signal 7 VDDIO_C NC
VDDIO_C P - Power supply for GPIO bank C - NC
GPIOX - Refer to Table 4-5 for functional multiplex information.
GPIOX_0 DIO Up General purpose input/output bank X signal 0 VDDIO_X NC
GPIOX_1 DIO Up General purpose input/output bank X signal 1 VDDIO_X NC
GPIOX_2 DIO Up General purpose input/output bank X signal 2 VDDIO_X NC
GPIOX_3 DIO Up General purpose input/output bank X signal 3 VDDIO_X NC
GPIOX_4 DIO Up General purpose input/output bank X signal 4 VDDIO_X NC
GPIOX_5 DIO Up General purpose input/output bank X signal 5 VDDIO_X NC
GPIOX_6 DIO Down General purpose input/output bank X signal 6 VDDIO_X NC
GPIOX_7 DIO Up General purpose input/output bank X signal 7 VDDIO_X NC
GPIOX_8 DIO Up General purpose input/output bank X signal 8 VDDIO_X NC
GPIOX_9 DIO Up General purpose input/output bank X signal 9 VDDIO_X NC
GPIOX_10 DIO Up General purpose input/output bank X signal
10
VDDIO_X NC
GPIOX_11 DIO Up General purpose input/output bank X signal
11
VDDIO_X NC
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