ST EVLONE65W User manual

Introduction
To reduce the noise on the ORGD pin, it is important to implement an external circuit as highlighted in the figure below. A
resistor of 470 kΩ is connected in series with a diode. These two components are placed between the VDRV pin and the gate of
OR-FET.
Figure 1. EVLONE65W schematic with ORGD external circuit
Diod e STPS 3017 0DJF
Comm unic atio n conn ecto r - plac ed on de tach able b ezel
plac ed on de tach able b ezel
NTC te mp. se nsor
JP1 is n orma lly cl osed .
Used f or cur rent m onit orin g.
GND
GND
GND
SPG ND C ONN_G ND
SPG ND
GND SPG ND
SPG ND
SSG ND
SPG ND
CONN_ GND
GND GND
GNDGNDGND
SPG ND
SSG NDSPG ND
GND
PG
PG
SPG ND
GND
D6
BAS 16LD
R2
2.2M
LN2
+ C29
680u
35V
D10
BAT 54SW
HON
N.M .
C34
10n
J3
9032 5-00 06
1
2
3
4
5
6
MG 1
Mas terG aN
PVCC
1GL 2
PGND
3
S EN SE
4
S EN SE
5
S EN SE
6
S EN SE
7
S EN SE
8
S EN SE
9
S EN SE
10
S EN SE
11
OU T 12
OU T 13
OU T 14
VS 15 VS 16 VS
17
VS 18 VS 19
GH 20
OU Tb 21
BOOT 22
LIN
24
SD/DIAG
25
HIN
26
VCC
27
GN D
28
EP1_G ND
EP1
EP3_O UT EP3
E P2_S NS
EP 2
C13
N.M .
R23
100K
C12
100n
+ C28
270u
25V
R10 1K
C26
220p
D5 BA S21 LL
AC
C42 100n
R4
220R
C21 100n
C4
470n
450V
R30
100K
R1 4.7K
C38 100n
Q1
BSS 169
G
DS
R17 47K
C9
10n
0805
250V
C0G
Q2
BSS 169
G
DS
R37 47K
C17
22u
25V
0805
C20
47n
R33
100R
R36 47R
C27
1u
C19
4.7u
Q5
ZVN 3320FTA
G
DS
C24 100p
R13 18K
D8
ES1 JFL
AC
+ C6
22u
400V
D1 S1 ML
A C
J2 USB-C-R ecept acle
GN DA1
A1
Tx+1
A2
Tx-1
A3
VbusA1
A4
CC1
A5
D+1
A6
D-1
A7
Sbu1
A8
VbusA2
A9
Rx-2
A10
Rx+2
A11
GN DA2
A12
GN DB2 B12
Rx+1 B 11
Rx-1 B10
VbusB2 B 9
Sbu2 B8
D-2 B 7
D+2 B 6
CC2 B5
VbusB1 B 4
Tx-2 B3
Tx+2 B2
GN DB1 B1
G 1 G 1 G 2 G 2 G 3 G 3 G 4 G 4
JP1
SMD Jum per - CLOS ED
12
R11 12.1K
GP1
N.M .
C18
4.7u
50V
0805
+ C8
22u
400V
R14 270K
R3 20R
+ C5
22u
400V
R7 0 R62
+ C15
33u
100V
R19 10R
R20
120K
-+
BR1
Z4G P208L-H F
AC1
+
AC2
-
LN3
R12 1k5
C35 1u
R5 0 R62
C31
4.7u
50V
0805
U2
LDO 40LPUR Y
G ND
1
EN 2
VIN 3 VOUT
4
Vse nse
5
ADJ
6
TAB
7
D3
S1M L
AC
D9
CDZ VT2 R6. 2B
AC
C37 4.7u
R35 0R0
R31
1R
C30
22u
35V
1206
C39
22n
D2 S1 ML
A C
R16 19.1K
ESD A25 L
D12
R38
470K
C11
100n
C25 100p
F1
FUS E 3.15 A
C22 100n
R22
22R
GP0
N.M .
T1A
W E_7 503188 10_R5
2 7
1 4
3
5
6
R6 0 R62
T1B
W E_7 503188 10_R5
10
8
9
R29
287R
Q6
STL160N S3L LH7
G 4
D5
S1
S2
S3D6
D7
D8
U1
ST- ONE
HV
1
POTP
5
SS
6
OVP
7
PVCC
8
PGND
9
P3V 3
10
HO N
11
LON
12
EN_OU T
13
OSC
14
DT
15
LEB
16
ISEN
17
PGND
18 PU MP 19
VDRV 20
SRVDS 2 1
SRGD 22
SPGND 2 3
OR GD 24
SSGND 2 5
CC2/D M 26
CC1/D P 27
VOSNS 2 8
SVCC 29
SV3V 30
SSGND 3 1
V1V 2 32
CSM 33
CSP 34
GPIO1 35
GPIO0 36
J5
STR IP4P MD
2
1
3
4
C43 4.7n
SRG D
N.M .
R8 0 R62
Q3
BC8 47BM
LON
N.M .
R9
220R
LN1
J1
Input P ads
1 2
C33
4.7u
50V
0805
R34
100K
C32
100n
L1
CM13090CT-242
1
1
2
2
3
3
4
4
L2 10u
C2
470n
450V
R21 430K
C23 100n
C14
2.2u
1210
R32
0R005
1W
C40
N.M .
R18
47K
D7
CDZ VT2 R10 B
D4 BA S52 1LP-7
AC
C10 22n
J4
Scr ews c onnec tor
1 2
R26
10R
D13
1N4148
RT1 4 70k
C41
N.M .
R24
0R0
C36 1u
C3
470n
450V
R28
100K
D11
ESD A25 P35-1U1M
A C
C1
100n
305V ac
Q4
BSC 146N10L S5A TMA1
G 4
D5
S1
S2
S3D6
D7
D8
R27
1K
R25
N.M .
+ C7
22u
400V
R15 470K
C16
100n
VBU S VBU S
CSM
SVC C
CC2
VAU XH
CC1
CSP
GP0 /RX
GP1 /TX
SVC C
VOU T
ORGD
VBU S
SRV DS
LS_CTR L
PVC C
EN_ CTR L
OVP
SRG D
ISEN
SS
DT
LEB
SV3 V
V1V 2
CC2
CC1
VDR V
PUM P
CC1
VRE CT
PVC C
PV5 V
CC2
GP0 /RX
SV3 V
VDR V
CC1
SVC C
VDR V
VAU XL
VBU S
DP
DP DN
DN DP
DN
VBO OT
OUTb
HS_ CTR L PHASE
LS_CTR L
EN_ CTR L
PV5 V
PG
VB_ UR VB OO T OUTb
PV5 V
ISEN
GND_ISEN
SVC C
GP0 /RX
GP1 /TX
SVC C
VRE CT
HV
VCL
HS_ CTR L
How to implement an external circuit to improve ORGD robustness of the ST-
ONE and ST-ONEMP
UM3130
User manual
UM3130 - Rev 1 - February 2023
For further information contact your local STMicroelectronics sales office.
www.st.com

Revision history
Table 1. Document revision history
Date Version Changes
05-Feb-2023 1 Initial release.
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UM3130 - Rev 1 page 2/4

Contents
Revision history ........................................................................2
UM3130
Contents
UM3130 - Rev 1 page 3/4

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