Analog Devices AD5934 User manual

250 kSPS, 12-Bit Impedance Converter,
Network Analyzer
AD5934
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2005–2008 Analog Devices, Inc. All rights reserved.
FEATURES
Programmable output peak-to-peak excitation voltage
to a maximum frequency of 100 kHz
Programmable frequency sweep capability with
serial I2C interface
Frequency resolution of 27 bits (<0.1 Hz)
Impedance measurement range from 1 kΩ to 10 MΩ
Capable of measuring 100 Ω to 1 kΩ with additional circuitry
Phase measurement capability
System accuracy of 0.5%
2.7 V to 5.5 V power supply operation
Temperature range: −40°C to +125°C
16-lead SSOP package
APPLICATIONS
Electrochemical analysis
Bioelectrical impedance analysis
Impedance spectroscopy
Complex impedance measurement
Corrosion monitoring and protection equipment
Biomedical and automotive sensors
Proximity sensing
Nondestructive testing
Material property analysis
Fuel/battery cell condition monitoring
GENERAL DESCRIPTION
The AD5934 is a high precision impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 250 kSPS, analog-to-digital converter (ADC). The
frequency generator allows an external complex impedance to
be excited with a known frequency. The response signal from
the impedance is sampled by the on-board ADC and a discrete
Fourier transform (DFT) is processed by an on-board DSP
engine. The DFT algorithm returns a real (R) and imaginary (I)
data-word at each output frequency.
Once calibrated, the magnitude of the impedance and relative
phase of the impedance at each frequency point along the sweep
is easily calculated using the following two equations:
Magnitude = 22 IR +
Phase = tan−1(I/R)
A similar device, available from Analog Devices, Inc., is the
AD5933, which is a 2.7 V to 5.5 V, 1 MSPS, 12-bit impedance
converter, with an internal temperature sensor, available in a
16-lead SSOP.
FUNCTIONAL BLOCK DIAGRAM
ADC
(12 BITS)
VDD/2
DDS
CORE
(27 BITS)
DAC
V
BIAS
Z(ω)
I
2
C
INTERFACE
IMAGINARY
REGISTER
GAIN
REAL
REGISTER
1024-POINT DFT
LPF
SCL
S
D
A
DVDDAVDDMCLK
AGND DGND
R
OUT
VOUT
AD5934
RFB
VIN
05325-001
Figure 1.

AD5934
Rev. A | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
I2C Serial Interface Timing Characteristics .............................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Teminolog y ...................................................................................... 11
System Description......................................................................... 12
Transmit Stage............................................................................. 13
Frequency Sweep Command Sequence................................... 14
Receive Stage ............................................................................... 14
DFT Operation ........................................................................... 14
Impedance Calculation .................................................................. 15
Magnitude Calculation .............................................................. 15
Gain Factor Calculation ............................................................ 15
Impedance Calculation Using Gain Factor............................. 15
Gain Factor Variation with Frequency .................................... 15
2-Point Calibration..................................................................... 16
2-Point Gain Factor Calculation .............................................. 16
Gain Factor Setup Configuration............................................. 16
Gain Factor Recalculation......................................................... 16
Gain Factor Temperature Variation ......................................... 17
Impedance Error......................................................................... 17
Measuring the Phase Across an Impedance ........................... 19
Performing a Frequency Sweep .................................................... 21
Register Map.................................................................................... 22
Control Register (Register Address 0x80, Register Address
0x81)............................................................................................. 22
Start Frequency Register (Register Address 0x82, Register
Address 0x83, Register Address 0x84)..................................... 23
Frequency Increment Register (Register Address 0x85,
Register Address 0x86, Register Address 0x87) ..................... 23
Number of Increments Register (Register Address 0x88,
Register Address 0x89) .............................................................. 24
Number of Settling Time Cycles Register (Register Address
0x8A, Register Address 0x8B) .................................................. 24
Status Register (Register Address 0x8F).................................. 24
Real and Imaginary Data Registers (16 Bits—Register Address
0x94, Register Address 0x95, Register Address 0x96, Register
Address 0x97) .............................................................................. 25
Serial Bus Interface......................................................................... 26
General I2C Timing.................................................................... 26
Writing/Reading to the AD5934 .............................................. 27
Block Write.................................................................................. 27
Read Operations......................................................................... 28
Typical Applications ....................................................................... 29
Measuring Small Impedances................................................... 29
Biomedical: Noninvasive Blood impedance Measurement.. 30
Sensor/Complex Impedance Measurement............................ 31
Electro-Impedance Spectroscopy............................................. 31
Choosing a Reference for the AD5934 ........................................ 32
Layout and Configuration............................................................. 33
Power Supply Bypassing and Grounding................................ 33
Evaluation Board ............................................................................ 34
Using the AD5934 Evaluation Board....................................... 34
Prototyping Area ........................................................................ 34
Crystal Oscillator (XO) vs. External Clock............................. 34
Schematics................................................................................... 35
Bill Of Materials.......................................................................... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40

AD5934
Rev. A | Page 3 of 40
REVISION HISTORY
5/8—Rev. 0 to Rev. A
Changes to Layout.............................................................. Universal
Changes to Features Section, General Description Section, and
Figure 1 ...............................................................................................1
Deleted Table 1; Renumbered Sequentially ...................................1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................6
Changes to Figure 3 and Table 4 .....................................................8
Changes to System Description Section and Figure 14..............12
Changes to Figure 16 ......................................................................13
Changes to Frequency Sweep Command Sequence Section and
Receive Stage Section......................................................................14
Changes to Gain Factor Calculation Section and Impedance
Calculation Using Gain Factor Section ........................................15
Changes to Figure 20 ......................................................................16
Changes to Impedance Error Section...........................................17
Added Measuring the Phase Across an Impedance Section .....19
Added Figure 28 and Figure 29; Renumbered Sequentially......20
Added Table 6; Renumbered Sequentially...................................20
Deleted Table 8 ................................................................................19
Deleted Table 10 and Table 11.......................................................20
Changes to Table 9 ..........................................................................22
Deleted Table 14, Table 16, and Table 17 .....................................22
Changes to Status Register (Register Address 0x8F) Section....24
Added Measuring Small Impedances Section, Figure 37, and
Table 16.............................................................................................29
Changes to Table 17 ........................................................................32
Added Evaluation Board Section..................................................34
Added Figure 40 ..............................................................................35
Added Figure 41 ..............................................................................36
Added Figure 42 ..............................................................................37
Added Figure 43 ..............................................................................38
Added Table 18 ................................................................................39
Changes to Ordering Guide...........................................................40
6/05—Revision 0: Initial Version

AD5934
Rev. A | Page 4 of 40
SPECIFICATIONS
VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 kΩ connected between Pin 5 and Pin 6; feedback
resistor = 200 kΩ connected between Pin 4 and Pin 5; PGA gain = ×1, unless otherwise noted.
Table 1.
Y Version1
Parameter Min Typ Max Unit Test Conditions/Comments
SYSTEM
Impedance Range 1 k 10 M Ω 100 Ω to 1 kΩ requires extra buffer circuitry,
see Measuring Small Impedances section
Total System Accuracy 0.5 % 2 V p-p output excitation voltage at 30 kHz,
200 kΩ connected between Pin 5 and Pin 6
System Impedance Error Drift 30 ppm/°C
TRANSMIT STAGE
Output Frequency Range21100 kHz
Output Frequency Resolution 0.1 Hz <0.1 Hz resolution achievable using
direct digital synthesis (DDS) techniques
MCLK Frequency 16.776 MHz Maximum system clock frequency
TRANSMIT OUTPUT VOLTAGE
Range 1
AC Output Excitation Voltage31.98 V p-p Refer to Figure 4 for output voltage distribution
DC Bias41.48 V DC bias of the ac excitation signal; see Figure 5
DC Output Impedance 200 Ω TA= 25°C
Short-Circuit Current to Ground atVOUT ±5.8 mA TA= 25°C
Range 2
AC Output Excitation Voltage30.97 V p-p See Figure 6
DC Bias40.76 V DC bias of output excitation signal; see Figure 7
DC Output Impedance 2.4 kΩ
Short-Circuit Current to Ground at VOUT ±0.25 mA
Range 3
AC Output Excitation Voltage30.383 V p-p See Figure 8
DC Bias40.31 V DC bias of output excitation signal; see Figure 9
DC Output Impedance 1 kΩ
Short-Circuit Current to Ground at VOUT ±0.20 mA
Range 4
AC Output Excitation Voltage30.198 V p-p See Figure 10
DC Bias40.173 V DC bias of output excitation signal; see Figure 11
DC Output Impedance 600 Ω
Short-Circuit Current to Ground atVOUT ±0.15 mA
SYSTEM AC CHARACTERISTICS
Signal-to-Noise Ratio 60 dB
Total Harmonic Distortion −52 dB
Spurious-Free Dynamic Range
Wide Band (0 MHz to 1 MHz) −56 dB
Narrow Band (±5 kHz) −85 dB

AD5934
Rev. A | Page 5 of 40
Y Version1
Parameter Min Typ Max Unit Test Conditions/Comments
RECEIVE STAGE
Input Leakage Current 1 nA To VIN pin
Input Capacitance50.01 pF Pin capacitance between VOUT and GND
Feedback Capacitance, CFB 3 pF
Feedback capacitance around current-to-
voltage amplifier; appears in parallel with
feedback resistor
ANALOG-TO-DIGITAL CONVERTER5
Resolution 12 Bits
Sampling Rate 250 kSPS ADC throughput rate
LOGIC INPUTS
Input High Voltage, VIH 0.7 × VDD
Input Low Voltage, VIL 0.3 × VDD
Input Current61 μA TA= 25°
Input Capacitance 7 pF TA= 25°C
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD, Normal Mode 10 15 mA VDD = 3.3 V
17 25 mA VDD = 5.5 V
IDD, Standby Mode 7 mA VDD = 3.3 V; see the Control Register section
9 mA VDD = 5.5 V
IDD, Power-Down Mode 0.7 5 μA VDD = 3.3 V
1 8 μA VDD = 5.5 V
1Temperature range for Y version = −40°C to +125°C, typical at +25°C.
2The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934.
3The peak-to-peak value of the ac output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
4The dc bias value of the output excitation voltage scales with supply voltage according to the following formula. VDD is the supply voltage.
Output Excitation Voltage (V p-p) = [2/3.3] × VDD
5Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
6The accumulation of the currents into Pin 8, Pin 15, and Pin 16.

AD5934
Rev. A | Page 6 of 40
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted (see Figure 2).
Table 2.
Parameter1Limit at TMIN, TMAX Unit Description
fSCL 400 kHz max SCL clock frequency
t12.5 μs min SCL cycle time
t20.6 μs min tHIGH, SCL high time
t31.3 μs min tLOW, SCL low time
t40.6 μs min tHD, STA, start/repeated start condition hold time
t5100 ns min tSU, DAT, data setup time
t620.9 μs max tHD, DAT, data hold time
0 μs min tHD, DAT, data hold time
t70.6 μs min tSU, STA, setup time for repeated start
t80.6 μs min tSU, STO, stop condition setup time
t91.3 μs min tBUF, bus free time between a stop and a start condition
t10 300 ns max tR, rise time of SDA when transmitting
0 ns min tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11 300 ns max tF, fall time of SCL and SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS compatible)
250 ns max tF, fall time of SDA when receiving
20 + 0.1 Cb3ns min tF, fall time of SCL and SDA when transmitting
Cb400 pF max Capacitive load for each bus line
1Guaranteed by design and characterization, not production tested.
2A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) to bridge the undefined falling edge of SCL.
3Cbis the total capacitance of one bus line in pF. Note that tRand tFare measured between 0.3 VDD and 0.7 VDD.
05325-002
SCL
S
D
A
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure 2. I2C Interface Timing Diagram

AD5934
Rev. A | Page 7 of 40
ABSOLUTE MAXIMUM RATINGS
TA= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
DVDD to GND −0.3 V to +7.0 V
AVDD1 to GND −0.3 V to +7.0 V
AVDD2 to GND −0.3 V to +7.0 V
SDA/SCL to GND −0.3 V to VDD + 0.3 V
VOUT to GND −0.3 V to VDD + 0.3 V
VIN to GND −0.3 V to VDD + 0.3 V
MCLK to GND −0.3 V to VDD + 0.3 V
Operating Temperatures
Extended Industrial Range (Y Grade) −40°C to +125°C
Storage Temperature Range −65°C to +160°C
Maximum Junction Temperature 150°C
SSOP Package, Thermal Impedance
θJA 139°C/W
θJC 136°C/W
Reflow Soldering (Pb-Free)
Peak Temperature 260°C
Time at Peak Temperature 10 sec to 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION

AD5934
Rev. A | Page 8 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1
NC 2
NC 3
RFB 4
SCL 16
SDA
15
AGND2 14
AGND1 13
VIN 5
VOUT 6
NC 7
DGND 12
AVDD2 11
AVDD1 10
MCLK
NOTES:
1. IT IS RECOMMENDED TO TIE ALL SUPPLY
CONNECTIONS (PIN 9, PIN 10, AND PIN 11)
AND RUN FROM A SINGLE SUPPLY BETWEEN
2.7V AND 5.5V.
2. IT IS ALSO RECOMMENDED TO
CONNECT ALL GROUND SIGNALS TOGETHE
R
(PIN 12, PIN 13, AND PIN 14).
8
DVDD 9
NC = NO CONNECT
AD5934
TOP VIEW
(Not to Scale)
05325-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 to 3, 7 NC No Connect.
4 RFB
External Feedback Resistor. Connect from Pin 4 to Pin 5. This pin sets the gain of the current-to-voltage amplifier
on the receive side.
5 VIN Input to Receive Transimpedance Amplifier. VIN presents a virtual earth voltage of VDD/2.
6 VOUT Excitation Voltage Signal Output.
8 MCLK The master clock for the system is supplied by the user.
9 DVDD Digital Supply Voltage.
10 AVDD1 Analog Supply Voltage 1.
11 AVDD2 Analog Supply Voltage 2.
12 DGND Digital Ground.
13 AGND1 Analog Ground 1.
14 AGND2 Analog Ground 2.
15 SDA I2C® Data Input.
16 SCL I2C Clock Input.

AD5934
Rev. A | Page 9 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
35
0
NUMBER OF DEVICES
30
25
20
15
10
5
2.06
05325-064
VOLTAGE (V)
1.92 1.94 1.96 1.98 2.00 2.02 2.04
MEAN = 1.9824
SIGMA = 0.0072
Figure 4. Range 1 Output Excitation Voltage Distribution, VDD = 3.3 V
1.30 1.75
05325-072
VOLTAGE (V)
1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70
MEAN = 1.4807
SIGMA = 0.0252
0
NUMBER OF DEVICES
30
25
20
15
10
5
Figure 5. Range 1 DC Bias Distribution, VDD = 3.3 V
30
0
NUMBER OF DEVICES
25
20
15
10
5
05325-066
VOLTAGE (V)
0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02
MEAN = 0.9862
SIGMA = 0.0041
Figure 6. Range 2 Output Excitation Voltage Distribution, VDD = 3.3 V
0.68 0.86
05325-073
VOLTAGE (V)
0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84
MEAN = 0.7543
SIGMA = 0.0099
30
0
NUMBER OF DEVICES
25
20
15
10
5
Figure 7. Range 2 DC Bias Distribution, VDD = 3.3 V
30
0
0.370 0.400
05325-077
VOLTAGE (V)
NUMBER OF DEVICES
25
20
15
10
5
0.375 0.380 0.385 0.390 0.395
MEAN = 0.3827
SIGMA = 0.00167
Figure 8. Range 3 Output Excitation Voltage Distribution, VDD = 3.3 V
0.290 0.320
05325-074
VOLTAGE (V)
0.295 0.300 0.305 0.310 0.315
MEAN = 0.3092
SIGMA = 0.0014
30
0
NUMBER OF DEVICES
25
20
15
10
5
Figure 9. Range 3 DC Bias Distribution, VDD = 3.3 V

AD5934
Rev. A | Page 10 of 40
05325-070
VOLTAGE (V)
0.192 0.194 0.196 0.198 0.200 0.202 0.204 0.206
MEAN = 0.1982
SIGMA = 0.0008
30
0
NUMBER OF DEVICES
25
20
15
10
5
Figure 10. Range 4 Output Excitation Voltage Distribution, VDD = 3.3 V
0.160 0.205
05325-075
VOLTAGE (V)
0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200
MEAN = 0.1792
SIGMA = 0.0024
30
0
NUMBER OF DEVICES
25
20
15
10
5
Figure 11. Range 4 DC Bias Distribution, VDD = 3.3 V
15.8
10.8
018
05325-088
MCLK FREQUENCY (MHz)
IDD (mA)
15.3
14.8
14.3
13.8
13.3
12.8
12.3
11.8
11.3
AVDD1, AVDD2, DVDD CONNECTED TOGETHER
OUTPUT EXCITATION FREQUENCY = 30kHz
RFB, Z
CALIBRATION
= 100kΩ
2 4 6 8 10 12 14 16
Figure 12. Typical Supply Current (IDD) vs. MCLK Frequency
0.4
–1.0
0400
05325-028
PHASE (Degrees)
PHASE ERROR (Degrees)
0.2
0
–0.2
–0.4
–0.6
–0.8
50 100 150 200 250 300 350
VDD = 3.3V
T
A
= 25°C
f = 32kHz
Figure 13. Typical Phase Error

AD5934
Rev. A | Page 11 of 40
TEMINOLOGY
Tot al Syst em Ac cu rac y
The AD5934 can accurately measure a range of impedance
values to less than 0.5% of the correct impedance value for
supply voltages between 2.7 V to 5.5 V.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the fundamental
frequency and images of these frequencies are present at the
output of a DDS device. The spurious-free dynamic range refers
to the largest spur or harmonic present in the band of interest.
The wideband SFDR gives the magnitude of the largest harmonic
or spur relative to the magnitude of the fundamental frequency
in the 0 Hz to Nyquist bandwidth. The narrow-band SFDR
gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz, about the fundamental frequency.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental,
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics. THD is defined as
V1
V6V5V4V3V2
THD
22222
log20)dB( ++++ =

AD5934
Rev. A | Page 12 of 40
SYSTEM DESCRIPTION
ADC
(12 BITS)
VDD/2
DDS
CORE
(27 BITS)
DAC
Z(ω)
I2C
INTERFACE
IMAGINARY
REGISTER
REAL
REGISTER
MAC CORE
(1024 DFT)
LPF
SCL
SDA
MCLK
ROUT VOUT
AD5934
RFB
VIN
05325-078
PROGRAMMABLE
GAIN AMPLIFIER
×5
×1
WINDOWING
OF DATA
COS SIN
MICROCONTROLLER
MCLK
VBIAS
Figure 14. Block Overview
The AD5934 is a high precision, impedance converter system
solution that combines an on-board frequency generator with a
12-bit, 250 kSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase is easily calculated using the following equations:
Magnitude = 22 IR +
Phase = tan−1(I/R)
To characterize an impedance profile Z(ω), generally a frequency
sweep is required such as that shown in Figure 15.
05325-033
FREQUENCY (Hz)
IMPEDANCE (Ω)
Figure 15. Impedance vs. Frequency Profile
The AD5934 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 5 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range for 3.3 V. These
values are ratiometric with VDD. So for a 5 V supply:
ppV3
3.3
0.5
98.1 −=×=1RangeforVoltageExcitationOutput
ppV24.2
3.3
0.5
48.1 −=×=1RangeforVoltageBiasDCOutput
Table 5. Voltage Levels Respective Bias Levels for 3.3 V
Range
No.
Output Excitation
Voltage Amplitude Output DC Bias Level
1 1.98 V p-p 1.48 V
2 0.99 V p-p 0.74 V
3 383 mV p-p 0.31 V
4 198 mV p-p 0.179 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques that permit subhertz resolution. The receive
stage receives the input signal current from the unknown impedance,
performs signal processing, and digitizes the result. The clock for
the DDS is generated from an external reference clock that is
provided by the user at MCLK.

AD5934
Rev. A | Page 13 of 40
TRANSMIT STAGE
As shown in Figure 16, the transmit stage of the AD5934 is made
up of a 27-bit phase accumulator DDS core that provides the output
excitation signal at a particular frequency. The input to the phase
accumulator is taken from the contents of the start frequency register
(see Register Address 0x82, Register Address 0x83, and Register
Address 0x84). Although the phase accumulator offers 27 bits of
resolution, the start frequency register has the three most significant
bits (MSBs) set to 0 internally; therefore, the user has the ability to
program only the lower 24 bits of the start frequency register.
PHASE
ACCUMULATOR
(27 BITS) VOUT
R
OUT
DAC
R(GAIN)
V
BIAS
05325-034
Figure 16. Transmit Stage
The AD5934 offers a frequency resolution programmable by the
user down to 0.1 Hz. The frequency resolution is programmed via
a 24-bit word loaded serially over the I2C interface to the frequency
increment register.
The frequency sweep is fully described by the programming of
three parameters: the start frequency, the frequency increment,
and the number of increments.
Start Frequency
This is a 24-bit word that is programmed to the on-board RAM
at Register Address 0x82, Register Address 0x83, and Register
Address 0x84 (see the Register Map section). The required code
loaded to the start frequency register is the result of the formula
shown in Equation 1, based on the master clock frequency and the
required start frequency output from the DDS.
27
2
16
×
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
=
MCLK
FrequencyStartOutputRequired
CodeFrequencyStart
(1)
For example, if the user requires the sweep to begin at 30 kHz and
has a 16 MHz clock signal connected to MCLK, the code that needs
to be programmed is given by
0x3D70A32
16
MHz16
kHz30 27 =×
⎟
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛
=CodeFrequencyStart
The user programs the value of 0x3D to Register Address 0x82,
the value 0x70 to Register Address 0x83, and the value 0xA3 to
Register Address 0x84.
Frequency Increment
This is a 24-bit word that is programmed to the on-board RAM at
Register Address 0x85, Register Address 0x86, and Register Address
0x87 (see the Register Map section). The required code loaded to
the frequency increment register is the result of the formula shown in
Equation 2, based on the master clock frequency and the required
increment frequency output from the DDS.
27
2
16
×
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
=
MCLK
IncrementFrequencyRequired
CodeIncrementFrequency
(2)
For example, if the user requires the sweep to have a resolution of
10 Hz and has a 16 MHz clock signal connected to MCLK, the code
that needs to be programmed is given by
0x00053E
16
MHz16
Hz10 ≡
⎟
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛
=
CodeIncrementFrequency
The user programs the value 0x00 to Register Address 0x85, the
value 0x05 to Register Address 0x86, and the value 0x3E to
Register Address 0x87.
Number of Increments
This is a 9-bit word that represents the number of frequency
points in the sweep. The number is programmed to the on-board
RAM at Register Address 0x88 and Register Address 0x89 (see the
Register Map section). The maximum number of points that can
be programmed is 511.
For example, if the sweep needs 150 points, the user programs
the value 0x00 to Register Address 0x88 and the value 0x96 to
Register Address 0x89.
Once the three parameter values are programmed, the sweep is
initiated by issuing a start frequency sweep command to the
control register at Register Address 0x80 and Register Address
0x81 (see the Register Map section). Bit D2 in the status register
(Register Address 0x8F) indicates the completion of the frequency
measurement for each sweep point. Incrementing to the next
frequency sweep point is under the control of the user. The measured
result is stored in the two register groups that follow: 0x94, 0x95
(real data) and 0x96, 0x97 (imaginary data) that should be read
before issuing an increment frequency command to the control
register to move to the next sweep point. There is the facility to
repeat the current frequency point measurement by issuing a
repeat frequency command to the control register. This has the
benefit of allowing the user to average successive readings. When
the frequency sweep has completed all frequency points, Bit D3 in
the status register is set, indicating the completion of the sweep.
Once this bit is set, further increments are disabled.

AD5934
Rev. A | Page 14 of 40
FREQUENCY SWEEP COMMAND SEQUENCE
The following sequence must be followed to implement a
frequency sweep:
1. Enter standby mode. Prior to issuing a start frequency sweep
command, the device must be placed in standby mode by
issuing an enter standby mode command to the control
register (Register Address 0x80 and Register Address 0x81).
In this mode, the VOUT and VIN pins are connected internally
to ground so there is no dc bias across the external impedance or
between the impedance and ground.
2. Enter initialize mode. In general, high Q complex circuits
require a long time to reach steady state. To facilitate the
measurement of such impedances, this mode allows the user
full control of the settling time requirement before entering
start frequency sweep mode where the impedance
measurement takes place.
An initialize with start frequency command to the control
register enters initialize mode. In this mode, the impedance
is excited with the programmed start frequency but no
measurement takes place. The user times out the required
settling time before issuing a start frequency sweep command to
the control register to enter the start frequency sweep mode.
3. Enter start frequency sweep mode. The user enters this mode
by issuing a start frequency sweep command to the control
register. In this mode, the ADC starts measuring after the
programmed number of settling time cycles elapses. The user
can program an integer number of output frequency cycles
(settling time cycles) to Register Address 0x8A and Register
Address 0x8B before beginning the measurement at each
frequency point (see Figure 30).
The DDS output signal is passed through a programmable
gain stage to generate the four ranges of peak-to-peak output
excitation signals listed in Table 5. The peak-to-peak output
excitation voltage is selected by setting Bit D10 and Bit D9 in
the control register (see the Control Register section) and is
made available at the VOUT pin.
RECEIVE STAGE
The receive stage comprises a current-to-voltage amplifier,
followed by a programmable gain amplifier (PGA), antialiasing
filter, and ADC. The receive stage schematic is shown in Figure 17.
The unknown impedance is connected between the VOUT and
VIN pins. The first stage current-to-voltage amplifier configuration
means that a voltage present at the VIN pin is a virtual ground
with a dc value set at VDD/2. The signal current that is developed
across the unknown impedance flows into the VIN pin and
develops a voltage signal at the output of the current-to-voltage
converter. The gain of the current-to voltage amplifier is determined
by a user-selectable feedback resistor connected between Pin 4
(RFB) and Pin 5 (VIN). It is important for the user to choose a
feedback resistance value which, in conjunction with the selected
gain of the PGA stage, maintains the signal within the linear range
of the ADC (0 V to VDD).
05325-038
5 × R
R
R
R
C
V
IN
VDD/2
RFB
ADC
LPF
Figure 17. Receive Stage
The PGA allows the user to gain the output of the current-to-
voltage amplifier by a factor of 5 or 1 depending upon the status
of Bit D8 in the control register (see the Register Map section
Register Address 0x80). The signal is then low-pass filtered and
presented to the input of the 12-bit, 250 kSPS ADC.
The digital data from the ADC is passed directly to the DSP core
of the AD5934 that performs a DFT on the sampled data.
DFT OPERATION
A DFT is calculated for each frequency point in the sweep. The
AD5934 DFT algorithm is represented by
(
)
))sin())(cos(()(
1023
0
njnnxfX
n
−= ∑
=
where:
X(f) is the power in the signal at the Frequency Point f.
x(n) is the ADC output.
cos(n) and sin(n) are the sampled test vectors provided by the
DDS core at the Frequency f.
The multiplication is accumulated over 1024 samples for each
frequency point. The result is stored in two 16-bit registers
representing the real and imaginary components of the result. The
data is stored in twos complement format.

AD5934
Rev. A | Page 15 of 40
IMPEDANCE CALCULATION
MAGNITUDE CALCULATION
The first step in the impedance calculation for each frequency
point is to calculate the magnitude of the DFT at that point.
The DFT magnitude is given by
22 IRMagnitude +=
where:
Ris the real number stored at Register Address 0x94 and
Register Address 0x95.
Iis the imaginary number stored at Register Address 0x96 and
Register Address 0x97.
For example, assume the results in the real data and imaginary
data registers are as follows at a frequency point:
Real Data Register = 0x038B = 907 decimal
Imaginary Data Register = 0x0204 = 516 decimal
1043.506)516(907 22 =+=Magnitude
To convert this number into impedance, it must be multiplied
by a scaling factor called the gain factor. The gain factor is
calculated during the calibration of the system with a known
impedance connected between the VOUT and VIN pins.
Once the gain factor is calculated, it can be used in the
calculation of any unknown impedance between the VOUT and
VIN pins.
GAIN FACTOR CALCULATION
An example of a gain factor calculation follows, with these
assumptions:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 200 kΩ
PGA gain = ×1
Current-to-voltage amplifier gain resistor = 200 kΩ
Calibration frequency = 30 kHz
The typical contents of the real data and imaginary data
registers after a frequency point conversion would then be
Real Data Register = 0xF064 = −3996 decimal
Imaginary Data Register = 0x227E = +8830 decimal
()
106.9692)8830(3996 22 =+−=Magnitude
Magnitude
Impedance
1
Code
Admittance
FactorGain
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
⎟
⎠
⎞
⎜
⎝
⎛
=
12
10819.515
106.9692
k200
1
−
×=
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
=FactorGain
IMPEDANCE CALCULATION USING GAIN FACTOR
The next example illustrates how the calculated gain factor
derived previously is used to measure an unknown impedance.
For this example, assume that the unknown impedance is 510 kΩ.
After measuring the unknown impedance at a frequency of
30 kHz, assume that the real data and imaginary data registers
contain the following data:
Real Data Register = 0xFA3F = −1473 decimal
Imaginary Data Register = 0x0DB3 = +3507 decimal
3802.863)(3507)1473)(( 22 =+−=Magnitude
The measured impedance at the frequency point is then given by
MagnitudeFactorGain
Impedance × =1

3802.86310515.819273
1
12 ××
=−= 509.791 kΩ
GAIN FACTOR VARIATION WITH FREQUENCY
Because the AD5934 has a finite frequency response, the gain
factor also shows a variation with frequency. This variation in
gain factor results in an error in the impedance calculation over
a frequency range. Figure 18 shows an impedance profile based
on a single-point gain factor calculation. To minimize this error,
the frequency sweep should be limited to as small a frequency
range as possible.
101.5
98.5
54 66
05325-085
FREQUENCY (kHz)
IMPEDANCE (kΩ)
101.0
100.5
100.0
99.5
99.0
56 58 60 62 64
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
T
A
= 25°C
MEASURED CALIBRATION IMPEDANCE = 100kΩ
Figure 18. Impedance Profile Using a Single-Point Gain Factor Calculation

AD5934
Rev. A | Page 16 of 40
2-POINT CALIBRATION
Alternatively, it is possible to minimize this error by assuming
that the frequency variation is linear and adjusting the gain
factor with a 2-point calibration. Figure 19 shows an impedance
profile based on a 2-point gain factor calculation.
101.5
98.5
54 66
05325-086
FREQUENCY (kHz)
IMPEDANCE (kΩ)
101.0
100.5
100.0
99.5
99.0
56 58 60 62 64
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
T
A
= 25°C
MEASURED CALIBRATION IMPEDANCE = 100kΩ
Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation
2-POINT GAIN FACTOR CALCULATION
This is an example of a 2-point gain factor calculation assuming
the following:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZUNKNOWN = 100.0 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 kΩ
Calibration frequencies = 55 kHz and 65 kHz
Typical values of the gain factor calculated at the two calibration
frequencies read
Gain factor calculated at 55 kHz is 1.031224 × 10−9.
Gain factor calculated at 65 kHz is 1.035682 × 10−9.
Difference in gain factor (GF) is
1.035682 × 10−9 − 1.031224 × 10−9 = 4.458000 × 10−12.
Frequency span of sweep (F) is 10 kHz.
Therefore, the gain factor required at 60 kHz is given by
9-
101.031224kHz5
kHz10
12-4.458000E ×+
⎟
⎠
⎞
⎜
⎝
⎛×
The required gain factor is 1.033453 × 10−9.
The impedance is calculated as previously described in the
Impedance Calculation section.
GAIN FACTOR SETUP CONFIGURATION
When calculating the gain factor, it is important that the receive
stage is operating in its linear region. This requires careful selection
of the excitation signal range, current-to-voltage gain resistor
and PGA gain. The gain through the system shown in Figure 20
is given by
Output Excitation Voltage Range ×
UNKNOWN
Z
ResistorSettingGain × PGA Gain
05325-089
VIN
VDD/2
RFB
ADC
LPF
Z
UNKNOWN
V
OUT
CURRENT-TO-VOLTAGE
GAIN SETTING RESISTOR
PGA
(×1 OR ×5)
Figure 20. System Voltage Gain
For this example, assume the following system settings:
VDD = 3.3 V
Gain setting resistor = 200 kΩ
ZUNKNOWN = 200 kΩ
PGA setting = ×1
The peak-to-peak voltage presented to the ADC input is 2 V p-p.
However, had the user chosen a PGA gain of ×5, the voltage
would saturate the ADC.
GAIN FACTOR RECALCULATION
The gain factor must be recalculated for a change in any of the
following parameters:
•Current-to-voltage gain setting resistor
•Output excitation voltage
•PGA gain

AD5934
Rev. A | Page 17 of 40
GAIN FACTOR TEMPERATURE VARIATION
The typical impedance error variation with temperature is in
the order of 30 ppm/°C. Figure 21 shows an impedance profile
with a variation in temperature for 100 kΩ impedance using a
2-point gain factor calibration.
101.5
98.5
54 66
05325-087
FREQUENCY (kHz)
IMPEDANCE (kΩ)
101.0
100.5
100.0
99.5
99.0
56 58 60 62 64
+125°C
+25°C
–40°C
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
MEASURED CALIBRATION IMPEDANCE = 100kΩ
Figure 21. Impedance Profile Variation with Temperature Using a
2-Point Gain Factor Calibration
IMPEDANCE ERROR
Minimizing the impedance range under test optimizes the
AD5934 measurement performance. Following are the examples of
the AD5934 performance when operating in the six different
impedance ranges. The gain factor is calculated with a precision
resistor in each case. Note that ROUT was measured to be 200 
for 2 V p-p. ROUT was calibrated out in the gain factor calculations.
In Figure 22 to Figure 26, the 10 kHz excitation frequency was
generated using a 4 MHz clock.
Impedance Range 1 (0.1 kΩ to 1 kΩ)
The following conditions were used to conduct the tests shown
in Figure 22:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 100 Ω
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 Ω
7
0
10
05325-079
FREQUENCY (kHz)
% IMPEDANCE ERROR
6
5
4
3
2
1
35 60 100
R
FB
= 0.1kΩ
CALIBRATION IMPEDANCE = 0.1kΩ
T
A
= 25°C
0.5kΩ
1kΩ
Figure 22. Impedance Range 1 Typical % Impedance Error over Frequency
Impedance Range 2 (1 kΩ to 10 kΩ)
The following conditions were used to conduct the tests shown
in Figure 23:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 1 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 1 kΩ
2.0
0
10
05325-080
FREQUENCY (kHz)
% IMPEDANCE ERROR
35 60 100
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
R
FB
= 1kΩ
CALIBRATION IMPEDANCE = 1kΩ
T
A
= 25°C
5kΩ
10kΩ
Figure 23. Impedance Range 2 Typical % Impedance Error over Frequency

AD5934
Rev. A | Page 18 of 40
Impedance Range 3 (10 kΩ to 100 kΩ)
The following conditions were used to conduct the tests shown
in Figure 24:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 10 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 10 kΩ
0.3
–0.3
10
05325-081
FREQUENCY (kHz)
% IMPEDANCE ERROR
35 60 100
0.2
0.1
0
–0.1
–0.2
R
FB
= 10kΩ
CALIBRATION IMPEDANCE = 10kΩ
T
A
= 25°C 50kΩ
100kΩ
Figure 24. Impedance Range 3 Typical % Impedance Error over Frequency
Impedance Range 4 (100 kΩ to 1 MΩ)
The following conditions were used to conduct the tests shown
in Figure 25:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 100 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 kΩ
1.0
–3.5
10
05325-082
FREQUENCY (kHz)
% IMPEDANCE ERROR
35 60 100
0.5
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
500kΩ
1MΩ
R
FB
= 100kΩ
CALIBRATION IMPEDANCE = 100kΩ
T
A
= 25°C
Figure 25. Impedance Range 4 Typical % Impedance Error over Frequency
Impedance Range 5 (1 MΩ to 2 MΩ)
The following conditions were used to conduct the tests shown
in Figure 26:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 100 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 kΩ
3
–9
10
05325-083
FREQUENCY (kHz)
% IMPEDANCE ERROR
35 60 100
1
–1
–3
–5
–7
R
FB
= 1MΩ
CALIBRATION IMPEDANCE = 1MΩ
T
A
= 25°C
1.5MΩ
2MΩ
Figure 26. Impedance Range 5 Typical % Impedance Error over Frequency
Impedance Range 6 (9 MΩ to 10 MΩ)
The following conditions were used to conduct the tests shown
in Figure 27:
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 9 MΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 9 MΩ
4
–10
10
05325-084
FREQUENCY (kHz)
% IMPEDANCE ERROR
2
0
–2
–4
–6
–8
35 60 100
R
FB
= 10MΩ
CALIBRATION IMPEDANCE = 10MΩ
T
A
= 25°C
9.5MΩ
10MΩ
Figure 27. Impedance Range 6 Typical % Impedance Error over Frequency

AD5934
Rev. A | Page 19 of 40
MEASURING THE PHASE ACROSS AN IMPEDANCE
The AD5934 returns a complex output code made up of a
separate real and imaginary components. The real component is
stored at Register Address 0x94 and Register Address 0x95, and
the imaginary component is stored at Register Address 0x96
and Register Address 0x97 after each sweep measurement. These
correspond to the real and imaginary components of the DFT
and not the resistive and reactive components of the impedance
under test.
For example, it is a common misconception to assume that if a
user was analyzing a series RC circuit that the real value stored
in Register Address 0x94 and Register Address 0x95 and the
imaginary value stored in Register Address 0x96 and Register
Address 0x97 would correspond to the resistance and capacitive
reactance, respectfully. However, this is incorrect because the
magnitude of the impedance (|Z|) can be calculated by calculating
the magnitude of the real and imaginary components of the
DFT given by the following formula:
22 IRMagnitude +=
After each measurement, multiply it by the calibration term and
invert the product. Therefore, the magnitude of the impedance
is given by the following formula:
MagnitudeFactorGain
Impedance × =1
Where the gain factor is given by
Magnitude
Impedance
1
Code
Admittance
FactorGain
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
⎟
⎠
⎞
⎜
⎝
⎛
=
The user must calibrate the AD5934 system for a known
impedance range to determine the gain factor before any valid
measurement can take place. Therefore, the user must know
the impedance limits of the complex impedance (ZUNKNOWN) for
the sweep frequency range of interest. The gain factor is simply
determined by placing a known impedance between the input/
output of the AD5934 and measuring the resulting magnitude of
the code. The AD5934 system gain settings need to be chosen to
place the excitation signal in the linear region of the on-board ADC.
Because the AD5934 returns a complex output code made up of
real and imaginary components, the user is also able to calculate
the phase of the response signal through the signal path of the
AD5934. The phase is given by the following formula:
Phase (rads) = tan−1(I/R) (3)
The phase measured by Equation 3 accounts for the phase
shift introduced to the DDS output signal as it passes through the
internal amplifiers on the transmit and receive side of the AD5934,
along with the low-pass filter, and also the impedance connected
between the VOUT and VIN pins of the AD5934.
The parameters of interest for many users are the magnitude of
the impedance (|ZUNKNOWN|) and the impedance phase (ZØ).The
measurement of the impedance phase (ZØ) is a 2-step process.
The first step involves calculating the AD5934 system phase.
The AD5934 system phase can be calculated by placing a
resistor across the VOUT and VIN pins of the AD5934 and
calculating the phase (using Equation 3) after each measurement
point in the sweep. By placing a resistor across the VOUT and
VIN pins, there is no additional phase lead or lag introduced to
the AD5934 signal path, and the resulting phase is due entirely
to the internal poles of the AD5934, that is, the system phase.
Once the system phase is calibrated using a resistor, the second
step involves calculating the phase of any unknown impedance
can be calculated by inserting the unknown impedance between
the VIN and VOUT terminals of the AD5934 and recalculating
the new phase (including the phase due to the impedance) using
the same formula. The phase of the unknown impedance (ZØ)
is given by
ZØ = (Φunknown − )system∇
where:
system
∇
is the phase of the system with a calibration resistor
connected between VIN and VOUT.
Φunknown is the phase of the system with the unknown
impedance connected between VIN and VOUT.
ZØ is the phase due to the impedance, that is, the impedance phase.
Note that it is possible to calculate the gain factor and to calibrate
the system phase using the same real and imaginary component
values when a resistor is connected between the VOUT and
VIN pins of the AD5934, for example, measuring the impedance
phase (ZØ) of a capacitor.
The excitation signal current leads the excitation signal voltage
across a capacitor by −90 degrees. Therefore, an approximate
−90 degrees phase difference between the system phase responses
measured with a resistor and the system phase responses measured
with a capacitive impedance exists.
As previously outlined, if the user wants to determine the phase
angle of the capacitive impedance (ZØ), the user first must
determine the system phase response ( ) and subtract
this from the phase calculated with the capacitor connected
between VOUT and VIN (Φunknown).
system∇
Figure 28 shows the AD5934 system phase response calculated
using a 220 kΩ calibration resistor (RFB = 220 k, PGA = ×1)
and the repeated phase measurement with a 10 pF capacitive
impedance.
One important point to note about the phase formula used to
plot Figure 28 is that it uses the arctangent function that returns
a phase angle in radians and, therefore, it is necessary to convert
from radians to degrees.

AD5934
Rev. A | Page 20 of 40
0
20
40
60
80
100
120
140
160
180
200
SYSTEM PHASE (Degrees)
60k45k15k 30k0 75k 90k 105k 120k
FREQUENCY (Hz)
05325-090
220kΩRESISTOR
10pF CAPACITOR
Figure 28. System Phase Response vs. Capacitive Phase
The phase difference (that is, ZØ) between the phase response
of a capacitor and the system phase response using a resistor is
the impedance phase of the capacitor (ZØ) and is shown in
Figure 29.
PHASE (Degrees)
60k45k15k 30k0 75k 90k 105k 120k
FREQUENCY (Hz)
05325-091
–
100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
Figure 29. Phase Response of a Capacitor
In addition, when using the real and imaginary values to interpret
the phase at each measurement point, care should be taken
when using the arctangent formula. The arctangent function
only returns the correct standard phase angle when the sign of
the real and imaginary values are positive, that is, when the
coordinates lie in the first quadrant. The standard angle is
taken counterclockwise from the positive real x-axis. If the sign
of the real component is positive and the sign of the imaginary
component is negative, that is, the data lies in the second
quadrant, the arctangent formula returns a negative angle, and
it is necessary to add an additional 180° to calculate the correct
standard angle. Likewise, when the real and imaginary components
are both negative, that is, when data lies in the third quadrant,
the arctangent formula returns a positive angle, and it is necessary
to add an additional 180° to calculate the correct standard
phase. When the real component is positive and the imaginary
component is negative, that is, the data lies in the fourth quadrant,
the arctangent formula returns a negative angle, and it is necessary
to add an additional 360° to calculate the correct standard phase.
Therefore, the correct standard phase angle is dependent
upon the sign of the real and imaginary components, which is
summarized in Table 6.
Table 6. Phase Angle
Real Imaginary Quadrant Phase Angle
π
°
×
−180
)/(tan 1RI
Positive Positive First
Positive Negative Second ⎟
⎠
⎞
⎜
⎝
⎛
π
°
×+° −180
)/(tan180 1RI
Negative Negative Third ⎟
⎠
⎞
⎜
⎝
⎛
π
°
×+° −180
)/(tan180 1RI
Positive Negative Fourth ⎟
⎠
⎞
⎜
⎝
⎛
π
°
×+° −180
)/(tan360 1RI
Once the magnitude of the impedance (|Z|) and the impedance
phase angle (ZØ, in radians) are correctly calculated, it is possible
to determine the magnitude of the real (resistive) and imaginary
(reactive) components of the impedance (ZUNKNOWN) by the vector
projection of the impedance magnitude onto the real and
imaginary impedance axis using the following formulas:
The real component is given by
|ZREAL| = |Z| × cos(ZØ)
The imaginary component is given by
|ZIMAG| = |Z| × sin(ZØ)