Analog Devices ADXL180 iMEMS User manual

Configurable, High g,
iMEMS Accelerometer
ADXL180
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Wide sensor range: 50 gto 500 g
Adjustable filter bandwidth: 100 Hz to 800 Hz
Configurable communication protocol
2-wire, current mode bus interface
Selectable sensor data resolution: 8 bit or 10 bit
Continuous auto-zero
Fully differential sensor and interface circuitry
High resistance to EMI/RFI
Sensor self-test
5.0 V to 14.5 V operation
8 bits of user-defined OTP memory
32-bit electronic serial number
Dual device per bus option
APPLICATIONS
Crash sensing
GENERAL DESCRIPTION
The ADXL180 iMEMS® accelerometer is a configurable, single
axis, integrated satellite sensor that enables low cost solutions
for front and side impact airbag applications. Acceleration data
is sent to the control module via a digital 2-wire current loop
interface bus. The communication protocol is programmable for
compatibility with various automotive interface bus standards.
The sensor grange is configurable to provide full-scale ranges
from ±50 gto ±500 g. The sensor signal third-order, low-pass
Bessel filter bandwidth is configurable at 100 Hz, 200 Hz,
400 Hz, and 800 Hz.
The 10-bit analog-to-digital converter (ADC) allows either 8-bit
or 10-bit acceleration data to be transmitted to the control module.
Each part has a unique electronic serial number. The device is
rated for operation from −40°C to +125°C and is available in a
5 mm × 5 mm LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
V
BN
V
DD
ADXL180
V
BP
3-POLE
BESSEL
FILTER
TRIMS
10-
BIT
ADC
VOLTAGE
REGULATOR
COMM
INTERFACE
SERIAL
PORT
STATE
MACHINE
SERIAL
NUMBER
SUPPLY
MONITOR
AUTO-
ZERO
SYNC
DETECT
PROGRAM
INTERFACE
CONFIGURATION
DATA
OTP
FUSE
ROM
V
BC
SELF-
TEST
07544-001
DIFF
SENSOR
MOD
OSCILLATOR/
TIMING
GENERATOR
V/Q
DEMOD
AMP
V
CM
REF
V
SCO
V
CM
V
SCI
Figure 1.

ADXL180
Rev. 0 | Page 2 of 56
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ...................................................................................... 9
Theory of Operation ...................................................................... 10
Overview...................................................................................... 10
Acceleration Sensor.................................................................... 10
Signal Processing ........................................................................ 11
Digital Communications State Machine ................................. 11
2-Wire Current Modulated Interface....................................... 11
Synchronous Operation and Dual Device Bus....................... 11
Programmed Memory and Configurability............................ 11
Physical Interface............................................................................ 13
Application Circuit..................................................................... 13
Current Modulation................................................................... 13
Manchester Data Encoding....................................................... 14
Operation at Low VBP or Low VDD............................................ 14
Operation at High VDD............................................................... 14
Communications Timing and Bus Topologies........................... 15
Asynchronous Communication ............................................... 15
Synchronous Communication.................................................. 15
Synchronous Communication Mode—Dual Device............. 17
Data Frame Definition................................................................... 21
Data Frame Transmission Format............................................ 21
Data Frame Configuration Options......................................... 21
Acceleration Data Coding ......................................................... 23
State Vector Coding ................................................................... 24
State Vector Descriptions .......................................................... 24
Transmission Error Detection Options................................... 25
Application Layer: Communication Protocol State Machine... 26
ADXL180 State Machine ........................................................... 26
Phase 1: Power-on-Reset Initialization.................................... 26
Phase 2: Device Data Transmission ......................................... 26
Phase 2: Mode Description ....................................................... 28
Phase 3: Self-Test Diagnostic .................................................... 35
Phase 4: Auto-Zero Initialization............................................. 38
Phase 5: Normal Operation ...................................................... 38
Signal Range and Filtering ............................................................ 39
Transfer Function Overview..................................................... 39
Range............................................................................................ 39
Three-Pole Bessel Filter............................................................. 39
Auto-Zero Operation................................................................. 39
Error Detection............................................................................... 41
Overview ..................................................................................... 41
Parity Error Due to Communications Protocol Configuration
Bit Error....................................................................................... 41
Self-Test Error............................................................................. 42
Offset Error/Offset Drift Monitoring...................................... 42
Voltage Regulator Monitor Reset Operation.......................... 42
Test and Diagnostic Tools ............................................................. 43
VSCI Signal Chain Input Test Pin .............................................. 43
VSCO Analog Signal Chain Output Test Pin ............................ 43
Configuration Specification.......................................................... 44
Overview ..................................................................................... 44
Configuration Mode Transmit Communications Protocol.. 45
Configuration Mode Command (Receive) Communications
Protocol........................................................................................ 46
Configuration Mode Communications Handshaking.......... 47
Configuration and User Data Registers .................................. 48
Configuration Mode Exit .......................................................... 48
Serial Number and Manufacturer Identification Data
Registers....................................................................................... 48
Programming the Configuration and User Data Registers .. 48
OTP Programming Conditions and Considerations ............ 49
Configuration/User Register OTP Parity................................ 49
Configuration Mode Error Reporting..................................... 49
Configuration Register Reference ................................................ 50
UD[7:0] User Data Bits.............................................................. 51
UD8 Configuration Bit.............................................................. 51
BDE .............................................................................................. 51
SCOE............................................................................................ 51
FDLY ............................................................................................ 51
ADME.......................................................................................... 51
STI ................................................................................................ 51
FC[1:0]......................................................................................... 51

ADXL180
Rev. 0 | Page 3 of 56
RG[2:0] .........................................................................................51
MD[1:0]........................................................................................52
SYEN.............................................................................................53
AZE ...............................................................................................53
ERC ...............................................................................................53
DAT...............................................................................................53
SVD...............................................................................................53
CUPAR and CUPRG ..................................................................53
Axis of Sensitivity............................................................................54
Branding...........................................................................................55
Outline Dimensions........................................................................56
Ordering Guide ...........................................................................56
REVISION HISTORY
8/08—Revision 0: Initial Version

ADXL180
Rev. 0 | Page 4 of 56
SPECIFICATIONS
TA= −40°C to +125°C, VBP − VBN = 5.0 V to 14.5 V, fLP = 400 Hz, acceleration = 0 g, unless otherwise noted.
Table 1.
Parameter1Symbol Min Typ Max Unit Test Conditions/Comments
SENSOR
Scale Factor Measurement frequency: 100 Hz
50 gRange See Table 37
8-Bit Data 0.465 0.50 0.535 g/LSB
10-Bit Data 0.116 0.1250 0.134 g/LSB
100 gRange
8-Bit Data 0.930 1.00 1.070 g/LSB
10-Bit Data 0.233 0.2500 0.268 g/LSB
150 gRange
8-Bit Data 1.395 1.50 1.605 g/LSB
10-Bit Data 0.349 0.3750 0.401 g/LSB
200 gRange
8-Bit Data 1.860 2.00 2.140 g/LSB
10-Bit Data 0.465 0.5000 0.535 g/LSB
250 gRange
8-Bit Data 2.325 2.50 2.675 g/LSB
10-Bit Data 0.581 0.625 0.669 g/LSB
350 gRange
8-bit Data 3.255 3.50 3.745 g/LSB
10-bit Data 0.830 0.8925 0.955 g/LSB
500 gRange
8-Bit Data 4.650 5.00 5.350 g/LSB
10-Bit Data 1.163 1.2500 1.338 g/LSB
Offset All ranges, auto-zero disabled
8-Bit Data −12 +11 LSB
10-Bit Data −48 +47 LSB
Noise (Peak-to-Peak) 50 grange
8-Bit Data 2 LSB 10 Hz to 400 Hz
10-Bit Data 2 3 LSB 10 Hz to 400 Hz
Self Test
Amplitude 20 25 30
g
Internal Self-Test Limit 20 30 g STI enabled, see Table 35
Nonlinearity 0.2 2 % Of full-scale range
Cross-Axis Sensitivity −5 +5 %
Resonant Frequency 12.8 kHz
Q 1.5
LOW-PASS FILTER
Frequency Response Third-order
Bessel
Pass Band fLP Programmable, see Table 38
−3 dB Frequency 670 800 880 Hz
−3 dB Frequency 335 400 440 Hz
−3 dB Frequency 167.5 200 220 Hz
−3 dB Frequency 83.75 100 110 Hz
AUTO-ZERO
Update Rate
Slow Mode 5.0 sec/LSB 10-bit LSB
Fast Mode 0.5 sec/LSB 10-bit LSB

ADXL180
Rev. 0 | Page 5 of 56
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
REGULATOR VOLTAGE MONITOR
Regulator Operating Voltage VDD 4.20 V
Power-Up Reset Voltage VPUR 3.77 4.0 4.23 V See Figure 31
Overvoltage Level VOV 4.7 4.95 5.3 V See Figure 31
Reset Hysteresis Voltage VHYST 0.12 V
COMMUNICATIONS INTERFACE
Quiescent (Idle) Current ILDLE 5 6 7.7 mA
Modulation Current IMOD 23 25 30 mA
Signal Current ISIG 28 31 37.7 mA ISIG = IIDLE + IMOD
Autodelay Detect Current IDET 18 22 26 mA Total including IIDLE
Data Bit Period2 tB8 s tB= 8 × tCLK
Data Bit Duty Cycle DDC 45 50 53 % DDC = tA/tB, see Figure 7
Data Bit Rise/Fall See Figure 7
Fall Time tR400 1000 ns
Rise Time tF350 1000 ns
Encoding Manchester See Figure 8
ADC Conversion Time2 tADC 35 s See Figure 10
Error Checking (Selectable)
Number of CRC Bits 3 x³ + x¹+ x0
Number of Parity Bits 1 Even
Synchronization Pulse Detect
No Detect Limit VSPND 3.0 V
Detect Threshold VSPT 3.5 V VBP − VBN + VSPT ≤ 14.5 V; see Figure 12
Threshold Hysteresis 0.1 V
Synchronization Pulse Detect
Time
tSPD 8 tCLK See Figure 12
Synchronization Pulse
Discharge (Pull-Down)
Time
tSPP 40 tCLK See Figure 12
Synchronization Mode
Transmission Delay
tSTD 63 tCLK See Figure 12
Configuration Mode Receive
Communications Interface
All @ 25°C only; VBP − VBN + VCT ≤ 12.25 V
Detect Threshold VCT 5.25 V See Figure 33
Threshold Hysteresis 0.1 V
Interbit Time tIB 250 tCLK See Figure 33
Data 0 Pulse Width tPG0 40 55 tCLK See Figure 33
Data 1 Pulse Width tPG1 80 tCLK See Figure 33
Configuration Mode
Response Time
tTM1 24 s See Figure 33
Configuration Mode Write
Delay Time
tTM2 50 s See Figure 33
VBP During Fuse
Programming
VBPF 7.5 V Compliant up to the maximum operating
voltage
VBP Current During Fuse
Programming
IFP 15 mA Maximum drawn by the part

ADXL180
Rev. 0 | Page 6 of 56
Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments
ASYNCHRONOUS MODE TIMING2
Message Transmission Period
Phase 2, Mode 0 tPM0 456 s ADIFX compatible
All Other Phases and Modes tP228 s
Initialization State (Phase 1) tI100 ms
Device Data State (Phase 2) ms
Mode 0 tDD0 4.10 ms
Mode 1 tDD1 109 ms
Mode 2 tDD2 109 ms
Mode 3 tDD3 117 ms
Self-Test State (Phase 3)
Self-Test Time3 tST 394 ms See Figure 26
Self-Test Interval tSTI 21.9 ms See Figure 26
Self-Test Cycle tSTC 65.7 ms See Figure 26
Auto-Zero Initialization State
(Phase 4)
tAZ 14.94 sec
SYNCHRONOUS MODE TIMING4
Message Transmission Period tPS N/A Determined by sync pulse, See Figure 12,
minimum tPS = tSPD + tSTD + tM+ tB
Initialization State1 (Phase 1) tI100 ms
Device Data State (Phase 2) ms
Mode 0 tDD0s 9 × tPS ms
Mode 1 tDD1s 480 × tPS ms
Mode 2 tDD2s 480 × tPS ms
Mode 3 tDD3s 512 × tPS ms
Self-Test State (Phase 3)
Self-Test Time3 tSTS 1728 × tPS ms
Self-Test Interval tSTIS 96 × tPS ms
Self-Test Cycle tSTCS 288 × tPS ms
Auto-Zero Initialization State
(Phase 4)
tAZs 65,535 × tPS sec
CLOCK
Period2 tCLK 1.05 1.0 0.95 s fCLK = 1/tCLK
PSRR5 <1 LSB
8-bit LSB; test conditions: VBP − VBN = 7.00 V,
VAC = 500 mV p-p, 100 kHz to 1.1 MHz
POWER SUPPLY HOLDUP TIME 500 ns @ IBUS = ISIG
THERMAL RESISTANCE, JUNCTION
TO CASE
θJC 30 °C/W
1All parameters are specified using the application circuit shown in Figure 6. CB= 10 nF, CVDD = 100 nF.
2All timing is driven from the on-chip master clock.
3tST and tSTS are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode.
4Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode.

ADXL180
Rev. 0 | Page 7 of 56
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (VBP − VBN) −0.3 V to +21 V
Voltage at Any Pin with
Respect to VBN Except VBP
−0.3 V to VDD + 0.3 V
Storage Temperature Range −55°C to +150°C
Soldering Temperature 255°C
Operating Temperature Range −40°C to +125°C
ESD All Pins 1.5 kV HBM
Latch-Up Current 100 mA
Mechanical Shock
Unpowered ±4000 g(0.5 ms, half sine)
Powered ±2000 g(0.5 ms, half sine);
−0.3 V to +7.0 V
Drop Test (onto Concrete)11.2 m
Thermal Gradient ±20°C/minute
1Soldered to FR4 coupon printed circuit board (PCB) at the dimensions of
25.4 mm × 25 mm. During test, the PCB is fastened to a support with 46 g
mass, equivalent to a typical satellite module PCB.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
RAMP-DOWN
RAMP-UP
CRITICAL ZONE
t
L
TO t
P
TEMPERATURE
T
A
= 25°C
t
L
t
P
TIME
t = 25°C TO PEAK
t
S
PREHEAT
t
L
t
P
T
SMIN
T
SMAX
07544-004
Figure 2. ADXL180 Pb-Free Solder Profile
Table 3. ADXL Solder Profile Parameters
Profile Feature Small Body Pb-Free Assemblies
Average Ramp-Up Rate (TLto TP) 3°C/second maximum
Preheat Temperature Min (TSmin) to Temperature Max (TSmax) 150°C to 200°C
Time (min to max) (tS) 60 sec to 180 sec
TSmax to TLRamp-Up Rate 3°C/second maximum
Time Maintained Above Temperature (TL) 217°C
Time (tL) 60 sec to 150 sec
Peak Temperature (TP) 260°C +5/−5°C
Time Within 5°C of Actual Peak Temperature (tP) 20 sec to 40 sec
Ramp-Down Rate 6°C/sec maximum
Time 25°C to Peak Temperature 8 minutes maximum

ADXL180
Rev. 0 | Page 8 of 56
V
DD
NC V
SCO
V
CM
V
CM
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
BP
V
BN
V
BC
NC
NC
NC
9
10
11
12
V
CM
NC
V
V
BN
V
CM
13
14
1516
SCI
4
3
2
1
876
V
BN
5
V
BN
NC = NO CONNECT
DAP1
ADXL180
TOP VIEW
(Not to Scale)
DAP2
07544-002
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 NC Reserved for Analog Devices Use Only. VBN or do not connect.
2 VCM Reserved for Analog Devices, Inc., Use Only. Do not connect.
3 VBN Negative Bus Voltage.
4 NC Reserved for Analog Devices Use Only. VBN or do not connect.
5 VDD Voltage Regulator Bypass Capacitor.
6 NC Reserved for ADI Use Only. VBN or do not connect.
7 VSCO Reserved for ADI Use Only. Do not connect.
8 VBN Negative Bus Voltage.
9 VBC Daisy-Chain Connection. Daisy-chain connection to VBP of the second device or do not connect.
10 VBN Negative Bus Voltage.
11 VCM Reserved for ADI Use Only. Do not connect.
12 VBP Positive Bus Voltage.
13 NC Reserved for ADI Use Only. VBN or do not connect.
14 NC Reserved for ADI Use Only. VBN or no connect
15 VSCI Analog Signal Chain Input. VBN when not in use.
16 VCM Reserved for ADI Use Only. Do not connect.
DAP1 VCM Exposed Pad: Reserved for ADI Use Only. Do not connect.
DAP2 VBN Exposed Pad: Negative Bus Voltage.

ADXL180
Rev. 0 | Page 9 of 56
TERMINOLOGY
Full-Scale Range (FSR)
The full-scale range of a device, also referred to as the dynamic
range, is the maximum and minimum glevel that reports on the
output following the internal filtering. As a reference, there is
usually a trade-off in increased sensitivity and resolution for
decreased full-scale range, and vice versa.
Noise
Device noise is the noise content between 10 Hz and 400 Hz, as
noted in the Specifications Tabl e 1. Device noise can be measured
by performing an FFT on the digital output and measuring the
noise content between the specified frequency limits.
Sensitivity
The sensitivity of a device is the amount of output change per
input change. In this device, it is most usually referred to in
units of LSB/g.
Scale Factor
The scale factor is the amount of input change per output change.
In this device, it is most usually referred to in units of g/LSB.
Offset
Offset is the low frequency component of the output signal that
is not due to changes in input acceleration. Slow moving effects,
such as temperature changes and self-heating during start up,
may affect offset, but the time scale for these effects is beyond
that of a typical shock or crash event.
Auto-Zero
Auto-zero is an offset compensation technique intended to
reduce the long term offset drift effects of temperature and
aging. This technique is designed to limit interaction with true
acceleration signals. For more information, see Figure 30.
Rise/Fall Times
The device rise time is defined as the amount of time necessary
for the Manchester encoded signal (IMOD) to transition from 10%
to 90% of its final value (ISIG). Device fall time is the amount of
time required for the IMOD signal to fall from 90% of ISIG to within
10% of IIDLE.
Idle Current
Idle current is the current of the device when at rest, waiting for
a synchronization pulse, or in between current modulation.
Modulation Current
Modulation current is the amount of current that the ADXL180
device pulls from the bus when communicating. For more
information, see Figure 7.
Phase
A phase is a stage in the ADXL180 state machine. For more
information, see Figure 20.
Mode
Mode refers to the selection of the Phase 2 method of device
data communication. The ADXL180 is configurable into four
unique operating modes.
CRC
A cyclic redundancy check (CRC) is calculated from a set of
data and then transmitted alongside that data. If the calculation
technique is defined and known to the receiving device, the
receiver can then check whether the CRC bits match the data. If
they do not match, a transmission error has occurred.
Parity
Parity is defined by the count of 1s in a binary string of data.
If this count is even, then the data is determined to have even
parity. Often a bit is used, such as the CUPAR, in a configuration
register that is defined in such a way as to establish a particular
parity in the register to detect single bit changes during the life
of the device. This is possible because a single bit change changes
parity and a monitor circuit can detect this. Similarly, a parity
bit can be added in a data transmission to detect single bit errors
if the parity of communication is preestablished for the transmit
and receive systems.

ADXL180
Rev. 0 | Page 10 of 56
THEORY OF OPERATION
OVERVIEW
The ADXL180 is a complete satellite system, including
acceleration sensor, data filtering, digital protocol functionality,
and a 2-wire, high-voltage, current-modulated bus interface
communications port.
ACCELERATION SENSOR
The ADXL180 provides a fully differential sensor structure and
circuit path. This device uses electrical feedback with zero force
feedback. Figure 4 is a simplified view of one of the differential
sensor elements. Each sensor includes several differential capa-
citor unit cells. Each cell is composed of fixed plates attached to the
substrate and movable plates attached to the frame. Displacement
of the frame changes the differential capacitance, which the on-
chip circuitry measures.
Complementary signals drive the fixed capacitor plates. The
relative phasing between the two halves of the differential
sensor is such that the displacement signal is differential
between the two measurement channels. Using the fully
differential sensor and an antiphase clocking scheme helps
reject electrical environmental noise (see Figure 5).
The ADXL180 acceleration sensor uses two electrically isolated,
mechanically coupled sensors to measure acceleration as shown
in Figure 5. The clock phasing of the readout is such that the
electrical signal due to acceleration is differential between the
channels and environmental disturbances couple in as a common-
mode signal. The following differential amplifier can then extract
the acceleration signal while suppressing the environmental noise.
Electrical feedback adjusts the amplitudes of the fixed capacitor
plates’ drive signals such that the ac signal on the moving plates
is zero. The feedback signal is linearly proportional to the applied
acceleration. This feedback technique ensures that there is no
net electrostatic force applied to the sensor.
A
MOVABLE
FRAME
ACCELERATION
UNIT SELF-TEST
FORCING CELL
UNIT SENSING
CELL
MOVING
PLATE
FIXED
PLATES
PLATE
CAPACITORS
NCHOR
ANCHOR
MOTION
07544-024
Figure 4. Simplified View of ADXL180 Sensor Under Acceleration
AMP
–
VOUT
–
0
+EMI DISTURBANCE RESPONSE
COMMON TO BOTH CHANNELS
0
ACCELERATION RESPONSE
DIFFERENTIAL BETWEEN CHANNELS
ACCELERATION SENSING AXIS
+X-AXIS SEN
–X-AXIS SENSOR
ISOLATED
MECHANICAL
COUPLINGS
SPRING
SOR
+
07544-025
Figure 5. Differential Acceleration Sensing