Analog Devices dBCool ADT7476 User manual

dBCool Remote Thermal
Controller and Voltage Monitor
ADT7476
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: [phone] www.analog.com
Fax: [phone] ©2005–2007 Analog Devices, Inc. All rights reserved.
FEATURES
Monitors up to 5 voltages
Controls and monitors up to 4 fans
High and low frequency fan drive signal
1 on-chip and 2 remote temperature sensors
Extended temperature measurement range up to 191°C
Automatic fan speed control mode controls system cooling
based on measured temperature
Enhanced acoustic mode dramatically reduces user
perception of changing fan speeds
Thermal protection feature via THERM output
Monitors performance impact of Intel Pentium 4 processor
Thermal control circuit via THERM input
3-wire and 4-wire fan speed measurement
Limit comparison of all monitored values
Meets SMBus 2.0 electrical specifications
GENERAL DESCRIPTION
The ADT7476 dBCool® controller is a thermal monitor
and multiple PWM fan controller for noise-sensitive or power-
sensitive applications requiring active system cooling. The
ADT7476 can drive a fan using either a low or high frequency
drive signal, monitor the temperature of up to two remote
sensor diodes plus its own internal temperature, and measure
and control the speed of up to four fans so they operate at the
lowest possible speed for minimum acoustic noise.
The automatic fan speed control loop optimizes fan speed for a
given temperature. The effectiveness of the system’s thermal
solution can be monitored using the THERM input. The
ADT7476 also provides critical thermal protection to the
system using the bidirectional THERM pin as an output to
prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
05382-001
ACOUSTIC
ENHANCEMENT
CONTROL
BAND GAP
REFERENCE
10-BIT
ADC
INTERRUPT
MASKING
PWM
CONFIGURATION
REGISTERS
ADDRESS
POINTER
REGISTER
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
INPUT
SIGNAL
CONDITIONING
AND
ANALOG
MULTIPLEXER
VCC TO ADT7476
VCC
D1+
D1–
D2+
D2–
+5VIN
+12VIN
+2.5VIN
VCCP
VID/GPIO
REGISTER
VID5
V
ID4/GPIO4
V
ID3/GPIO3
V
ID2/GPIO2
V
ID1/GPIO1
V
ID0/GPIO0
GPIO6
SERIAL BUS
INTERFACE
SCL SDA SMBALERT
SMBus
ADDRESS
SELECTION
ADDR
SELECT
ADDREN
GND
PWM1
PWM2
PWM3
PWM
REGISTERS
AND
CONTROLLERS
(HF AND LF)
AUTOMATIC
FAN SPEED
CONTROL
TACH1
TACH2
TACH3
TACH4
FAN
SPEED
COUNTER
THERMAL
PROTECTION
PERFORMANCE
MONITORING
THERM
BAND GAP
TEMP. SENSOR
ADT7476
Figure 1.
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ADT7476
Rev. B | Page 2 of 72
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Product Description....................................................................... 11
Feature Comparisons Between ADT7476 and ADT7468..... 11
Recommended Implementation............................................... 12
Serial Bus Interface..................................................................... 13
Write Operations ........................................................................ 15
Read Operations ......................................................................... 16
SMBus Timeout .......................................................................... 16
Virus Protection.......................................................................... 16
Voltage Measurement Input...................................................... 17
Analog-to-Digital Converter .................................................... 17
Input Circuitry............................................................................ 17
Voltage Measurement Registers................................................ 17
Voltage Limit Registers .............................................................. 17
Extended Resolution Registers ................................................. 17
Additional ADC Functions for Voltage Measurements ........ 17
VID Code Monitoring ............................................................... 20
VID Code Input Threshold Voltage......................................... 20
VID Code Change Detect Function ........................................ 20
Programming the GPIOs........................................................... 20
Temperature Measurement Method ........................................ 20
Factors Affecting Diode Accuracy........................................... 22
Additional ADC Functions for Temperature Measurement 23
Limits, Status Registers, and Interrupts....................................... 25
Limit Values ................................................................................ 25
Status Registers ........................................................................... 26
THERM Timer ........................................................................... 28
Fan Drive Using PWM Control ............................................... 31
Laying Out 3-Wire Fans ............................................................ 33
Programming TRANGE.................................................................. 36
Programming the Automatic Fan Speed Control Loop ............ 37
Manual Fan Control Overview................................................. 37
THERM Operation in Manual Mode...................................... 37
Automatic Fan Control Overview............................................ 37
Step 1: Hardware Configuration .............................................. 38
Step 2: Configuring the Mux .................................................... 41
Step 3: TMIN Settings for Thermal Calibration Channels ...... 43
Step 4: PWMMIN for Each PWM (Fan) Output ...................... 44
Step 5: PWMMAX for PWM (Fan) Outputs.............................. 45
Step 6: TRANGE for Temperature Channels................................ 46
Step 7: TTHERM for Temperature Channels ............................... 48
Step 8: THYST for Temperature Channels.................................. 50
Fan Presence Detect................................................................... 51
Fan Sync....................................................................................... 52
Standby Mode ............................................................................. 52
XNOR Tree Test Mode .............................................................. 52
Power-On Default ...................................................................... 52
Register Tables ................................................................................ 53
Outline Dimensions....................................................................... 72
Ordering Guide .......................................................................... 72
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ADT7476
Rev. B | Page 3 of 72
REVISION HISTORY
10/07—Rev. A to Rev. B
Changes to Register 0x76 and Register 0x77 in Table 18...........53
Changes to Bit 3 in Table 26...........................................................58
Changes to Table 29 Register Address..........................................59
Changes to Bit 1 in Table 51...........................................................68
3/06—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to Table 1 ............................................................................4
Inserted Table 3..................................................................................6
Changes to Feature Comparisons Between ADT7476 and
ADT7468 Section............................................................................11
Changes to Figure 23 ......................................................................16
Changes to Fan Speed Measurement Registers Section.............34
Changes to Register Tables Section...............................................53
Changes to Ordering Guide...........................................................72
4/05—Revision 0: Initial Version
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ADT7476
Rev. B | Page 4 of 72
SPECIFICATIONS
TA= TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage 3.0 3.3 3.6 V
Supply Current, ICC 1.5 3 mA Interface inactive, ADC active
TEMPERATURE-TO-DIGITAL CONVERTER
Local Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C –40°C ≤ TA≤ 125°C
Resolution 0.25 °C
Remote Diode Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA≤ 85°C
±2.5 °C –40°C ≤ TA≤ 125°C
Resolution 0.25 °C
Remote Sensor Source Current 180 μA High level
11 μΑ Low level
ANALOG-TO-DIGITAL CONVERTER
(INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error (TUE) ±2 % For 12 V channel
±1.5 % For all other channels
Differential Nonlinearity (DNL) ±1 LSB 8 bits
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Voltage Input) 11 ms Averaging enabled
Conversion Time (Local Temperature) 12 ms Averaging enabled
Conversion Time (Remote Temperature) 38 ms Averaging enabled
Total Monitoring Cycle Time 145 ms Averaging enabled
19 ms Averaging disabled
Input Resistance 70 120 kΩ For VCCP channel
70 114 kΩ For all other channels
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ±6 % 0°C ≤ TA≤ 70°C
±10 % −40°C ≤ TA≤ +120°C
Full-Scale Count 65,535
Nominal Input RPM 109 RPM Fan count = 0xBFFF
329 RPM Fan count = 0x3FFF
5000 RPM Fan count = 0x0438
10,000 RPM Fan count = 0x021C
OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO
Current Sink, IOL 8.0 mA
Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA
High Level Output Current, IOH 0.1 20 μA VOUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA
High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.4 V
Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH 2.0 V
3.6 V Maximum input voltage
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ADT7476
Rev. B | Page 5 of 72
Parameter Min Typ Max Unit Test Conditions/Comments
Input Low Voltage, VIL 0.8 V
−0.3 V Minimum input voltage
Hysteresis 0.5 V p-p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH 0.75 × VCC V
Input Low Voltage, VIL 0.4 V
DIGITAL INPUT CURRENT
Input High Current, IIH ±1 μA VIN = VCC
Input Low Current, IIL ±1 μA VIN = 0
Input Capacitance, CIN 5 pF
SERIAL BUS TIMING2See Figure 2
Clock Frequency, fSCLK 10 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, tBUF 4.7 μs
SCL Low Time, tLOW 4.7 μs
SCL High Time, tHIGH 4.0 50 μs
SCL, SDA Rise Time, tr1000 ns
SCL, SDA Fall Time, tf 300 μs
Data Setup Time, tSU;DAT 250 ns
Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be disabled
1All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA= 25°C and represent a most likely parametric norm. Logic inputs
accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge,
and VIH = 2.0 V for a rising edge.
2SMBus timing specifications are guaranteed by design and are not production tested.
TIMING DIAGRAM
SCL
SD
A
PS
SP
t
BUF
t
HD; STA
t
HD; DAT
t
SU; DAT
t
F
t
R
t
LOW
t
SU; STA
t
HIGH
t
HD; STA
t
SU; STO
05382-002
Figure 2. Serial Bus Timing Diagram
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ADT7476
Rev. B | Page 6 of 72
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Positive Supply Voltage (VCC) 3.6 V
Maximum Voltage on +12VIN Pin 16 V
Maximum Voltage on +5VIN Pin 6.25V
Maximum Voltage on All Open-Drain Outputs 3.6 V
Voltage on Any Input or Output Pin −0.3 V to +4.2 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ MAX) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
IR Reflow Peak Temperature 220°C
Pb-Free Peak Temperature 260°C
Lead Temperature (Soldering, 10 sec) 300°C
ESD Rating 1500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
JC Unit
24-Lead QSOP 122 31.25 °C/W
ESD CAUTION
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ADT7476
Rev. B | Page 7 of 72
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05382-003
20
19
18
17
16
15
14
13
+5V
IN
VID4/GPIO4
D1+
D1–
24
23
22
21
PWM1/XTO
V
CCP
+2.5V
IN
/THERM
+12V
IN
/VID5
D2+
D2–
PWM3/ADDREN
TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT
5
6
7
8
9
10
11
12
VID0/GPIO0
VID1/GPIO1
VID2/GPIO2
VID3/GPIO3
TACH1
TACH2
TACH3
PWM2/SMBALERT
1
2
3
4
SDA
SCL
GND
V
CC
ADT7476
TOP VIEW
(Not to Scale)
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.
2 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.
3 GND Ground Pin.
4 VCC Power Supply. Powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored
through this pin.
5 VID0 Digital Input. Voltage supply readouts from CPU. This value is read into the VID code register (0x43).
GPIO0 General-Purpose Open-Drain Digital I/O.
6 VID1 Digital Input. Voltage supply readouts from CPU. This value is read into the VID code register (0x43).
GPIO1 General-Purpose Open-Drain Digital I/O.
7 VID2 Digital Input. Voltage supply readouts from CPU. This value is read into the VID code register (0x43).
GPIO2 General-Purpose Open-Drain Digital I/O.
8 VID3 Digital Input. Voltage supply readouts from CPU. This value is read into the VID code register (0x43).
GPIO3 General-Purpose Open-Drain Digital I/O.
9 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.
10 PWM2 Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control Fan 2
speed. Can be configured as a high or low frequency drive.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-
limit conditions.
11 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.
12 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.
13 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3 and Fan 4 speed. Requires 10 kΩ typical
pull-up. Can be configured as a high or low frequency drive.
ADDREN If pulled low on power-up, the ADT7476 enters address select mode, and the state of Pin 14 (ADDR SELECT)
determines the ADT7476 slave address.
14 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.
THERM Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Use to time and monitor assertions on
the THERM input. For example, can be connected to the PROCHOT output of an Intel® Pentium® 4 processor or
to the output of a trip point temperature sensor. Can be used as an output to signal overtemperature
conditions.
SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-
limit conditions.
GPIO6 General-Purpose Open-Drain Digital I/O.
ADDR SELECT If in address select mode, the logic state of this pin defines the SMBus device address.
15 D2– Cathode Connection to Second Thermal Diode.
16 D2+ Anode Connection to Second Thermal Diode.
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ADT7476
Rev. B | Page 8 of 72
Pin No. Mnemonic Description
17 D1– Cathode Connection to First Thermal Diode.
18 D1+ Anode Connection to First Thermal Diode.
19 VID4 Digital Input. Voltage supply readouts from CPU. This value is read into the VID code register (0x43).
GPIO4 General-Purpose Open-Drain Digital I/O.
20 +5VIN Analog Input. Monitors +5 V power supply.
21 +12VIN Analog Input. Monitors +12 V power supply.
VID5 Digital Input. Voltage supply readouts from CPU. This value is read into the VID code register (0x43).
22 +2.5VIN Analog Input. Monitors +2.5 V supply, typically a chipset voltage.
THERM Alternatively, this pin can be reconfigured as a bidirectional/omnidirectional THERM pin. Can be used to time
and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of an Intel
Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal
overtemperature conditions.
23 VCCP Analog Input. Monitors processor core voltage (0 V to 3 V).
24 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical
pull-up.
XTO Also functions as the output from the XOR tree in XOR test mode.
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ADT7476
Rev. B | Page 9 of 72
TYPICAL PERFORMANCE CHARACTERISTICS
0
–10
–20
–30
–40
–50
–60
024681012
CAPACITANCE (nF)
TEMPERATURE ERROR (°C)
14 16 18 20 22
05382-004
Figure 4. Temperature Error vs. Capacitance Between D+ and D−
30
20
10
0
–10
–20
–30
0204060
LEAKAGE RESISTANCE (MΩ)
TEMPERATURE ERROR (°C)
80 100
–40
05382-006
D+ TO V
CC
D+ TO GND
Figure 5. Remote Temperature Error vs. PCB Resistance
30
25
20
15
10
5
0
–5
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
100mV
60mV
40mV
05382-007
Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency
70
60
50
40
30
20
0
10
0 100M 200M 300M 400M 500M 600M
NOISE FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
40mV
05382-008
–10
60mV
100mV
Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
3.0 3.1 3.2 3.3 3.4
V
DD
(V)
I
DD
(mA)
1.04
1.02
3.5 3.6
1.00
0.98
05382-009
Figure 8. Normal IDD vs. Power Supply
100mV
250mV
15
10
5
0
–5
–10
–15
0 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
05382-010
Figure 9. Internal Temperature Error vs. Power Supply
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ADT7476
Rev. B | Page 10 of 72
05382-011
6
4
2
0
–2
–4
–6
0 100M 200M 300M
FREQUENCY (Hz)
TEMPERATURE ERROR (°C)
400M 500M 600M
–8
–10
–12
100mV
250mV
Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (°C)
TEMPERATURE ERROR (°C)
–1.0
–1.5
105 125
05382-012
Figure 11. Internal Temperature Error vs. Temperature
3.0
2.5
2.0
1.5
1.0
0.5
0
–0.5
–40 –20 0 20 40 60 85
OIL BATH TEMPERATURE (°C)
TEMPERATURE ERROR (°C)
–1.0
–1.5
105 125
05382-013
–2.0
Figure 12. Remote Temperature Error vs. Temperature
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ADT7476
Rev. B | Page 11 of 72
PRODUCT DESCRIPTION
The ADT7476 is a complete thermal monitor and multiple fan
controller for any system requiring thermal monitoring and
cooling. The device communicates with the system via a serial
system management bus. The serial bus controller has a serial
data line for reading and writing addresses and data (Pin 1),
and an input line for the serial clock (Pin 2). All control and
programming functions for the ADT7476 are performed over
the serial bus. In addition, a pin can be reconfigured as an
SMBALERT output to signal out-of-limit conditions.
FEATURE COMPARISONS BETWEEN ADT7476
AND ADT7468
•Dynamic TMIN , dynamic operating point, and associated
registers are no longer available on the ADT7476. The
following related registers are not available in the
ADT7476:
•Calibration Control 1 and Calibration Control 2
(Register 0x36 and Register 0x37)
•Operating Point (Register 0x33, Register 0x34, and
Register 0x35)
•Previously, TRANGE defined the slope of the automatic fan
control algorithm. For the ADT7476, TRANGE now defines a
true temperature range.
•For the ADT7476, acoustic filtering is now assigned to
temperature zones and not to fans. Smoothing times have
been increased for better acoustic performance.
•For the ADT7476, temperature measurements are made
with two switching currents instead of three. SRC is not
available in the ADT7476.
•For the ADT7476, high frequency PWM can now be
enabled/disabled on each PWM output individually.
•For the ADT7476, THERM can now be enabled/disabled
on each temperature channel individually.
•The ADT7476 does not support full shutdown mode.
•The ADT7476 defaults to twos complement temperature
measurement mode.
•Some pins have swapped/added functions.
•The power-up routine for the ADT7476 is simplified.
Other minor changes in the ADT7476 include the following:
•Vcore_low_enable has been reallocated to Bit 7 of
Configuration Register 1 (0x40).
•Device ID register (0x3D) reads 0x76.
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ADT7476
Rev. B | Page 12 of 72
RECOMMENDED IMPLEMENTATION
Configuring the ADT7476, as shown in Figure 13, allows the
system designer to use the following features:
•Two PWM outputs for fan control of up to three fans. (The
front and rear chassis fans are connected in parallel.)
•Three TACH fan speed measurement inputs.
•VCC measured internally through Pin 4.
•CPU temperature measured using Remote 1 temperature
channel.
•Remote temperature zone measured through Remote 2
temperature channel.
•Local temperature zone measured through the internal
temperature channel.
•Bidirectional THERM pin. This feature allows Intel
Pentium 4 PROCHOT monitoring and can function as an
overtemperature THERM output. It can alternatively be
programmed as an SMBALERT system interrupt output.
05382-014
TACH2
PWM3
TACH3
D1+
D1–
V
CC
+5V
IN
+12V
IN
/VID5
GND
ADT7476
SCL
SDA
D2+
D2–
TACH1
VID[0:4]/VID[0:5]
PWM1
AMBIENT
TEMPERATURE
SMBALERT
THERM
5(VRM9)/6(VRM10)
PROCHOT
FRONT
CHASSIS
FAN
REAR
CHASSIS
FAN
Figure 13. ADT7476 Configuration
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ADT7476
Rev. B | Page 13 of 72
SERIAL BUS INTERFACE
Control of the ADT7476 is carried out using the serial system
management bus (SMBus). The ADT7476 is connected to this
bus as a slave device, under the control of a master controller.
The ADT7476 has a 7-bit serial bus address. When the device is
powered up with Pin 13 (PWM3/ADDREN) high, the ADT7476
has a default SMBus address of 0101110 or 0x2E. The read/write
bit must be added to get the 8-bit address. If more than one
ADT7476 is used in a system, each ADT7476 is placed in
ADDR SELECT mode by strapping Pin 13 low on power-up.
The logic state of Pin 14 then determines the device’s SMBus
address. The logic of these pins is sampled on power-up.
The device address is sampled on power-up and latched on the first
valid SMBus transaction, more precisely on the low-to-high
transition at the beginning of the 8th SCL pulse, when the serial
bus address byte matches the selected slave address. The selected
slave address is chosen using the ADDREN pin/ ADDR SELECT
pin. Any attempted changes in the address have no effect after
this.
Table 5. Hardwiring the ADT7476 SMBus Device Address
Pin 13 State Pin 14 Address
0 Low (10 kΩ to GND) 0101100 (0x2C)
0 High (10 kΩ pull-up) 0101101 (0x2D)
1 Don’t care 0101110 (0x2E)
05382-015
ADT7476
14
ADDRESS = 0x2E
VCC
ADDR SELECT
13
PWM3/ADDREN
10kΩ
Figure 14. Default SMBus Address = 0x2E
0
5382-016
ADT7476
14
ADDRESS = 0x2C
13
10kΩ
ADDR SELECT
PWM3/ADDREN
Figure 15. SMBus Address = 0x2C (Pin 14 = 0)
05382-017
ADT7476
14
ADDRESS = 0x2D
13
V
CC
10kΩ
ADDR SELECT
PWM3/ADDREN
Figure 16. SMBus Address = 0x2D (Pin 14 = 1)
05382-018
DO NOT LEAVE ADDREN
UNCONNECTED! CAN
CAUSE UNPREDICTABLE
ADDRESSES.
ADT7476
14
13 NC
V
CC
10kΩ
C
ARE SHOULD BE TAKEN TO ENSURE THAT PIN 13
(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 1
3
FLOATING COULD CAUSE THE ADT7476 TO POWER UP WITH AN
UNEXPECTED ADDRESS.
NOTE THAT IF THE ADT7476 IS PLACED INTO ADDR SELECT
MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE
FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT
C
IRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO
HANDLE THESE DUAL FUNCTIONS.
ADDR SELECT
PWM3/ADDREN
Figure 17. Unpredictable SMBus Address if Pin 13 Is Unconnected
The ability to make hardwired changes to the SMBus slave
address allows the user to avoid conflicts with other devices
sharing the same serial bus, for example, if more than one
ADT7476 is used in a system.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit address (MSB first) plus a R/Wbit that determines
the direction of the data transfer, that is, whether data is
written to or read from the slave device.
2. The peripheral whose address corresponds to the transmit-
ted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus now remain
idle while the selected device waits for data to be read from
or written to it. If the R/Wbit is a 0, the master writes to
the slave device. If the R/Wbit is a 1, the master reads from
the slave device.
3. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period. A low-to-high transition,
when the clock is high, can be interpreted as a stop signal.
The number of data bytes transmitted over the serial bus in
a single read or write operation is limited only by what the
master and slave devices can handle.
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ADT7476
Rev. B | Page 14 of 72
4. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition.
In read mode, the master device overrides the acknowledge
bit by pulling the data line high during the low period before
the ninth clock pulse. This is known as No Acknowledge.
The master then takes the data line low during the low
period before the 10th clock pulse, and then high during the
10th clock pulse to assert a stop condition. Any number of
bytes of data can be transferred over the serial bus in one
operation. It is not possible to mix read and write in one
operation because the type of operation is determined at the
beginning and cannot subsequently be changed without
starting a new operation. For the ADT7476, read operations
contain one byte, and write operations contain either one or
two bytes.
To write data to one of the device data registers or read
data from it, the address pointer register must be set so that
the correct data register is addressed; then data can be
written into that register or read from it. The first byte of a
write operation always contains an address stored in the
address pointer register. If data is to be written to the
device, the write operation contains a second data byte that
is written to the register selected by the address pointer
register (see Figure 18).
The device address is sent over the bus followed by the
R/Wbit set to 0. This is followed by two data bytes. The
first data byte is the address of the internal data register to
be written to, which is stored in the address pointer
register. The second data byte is the data to be written to
the internal data register.
On PCs and servers, control of the ADT7476 is carried out
using the SMBus. The ADT7476 is connected to this bus as a
slave device, under the control of a master controller, which is
usually (but not necessarily) the ICH.
The ADT7476 has three 7-bit serial bus addresses. The R/Wbit
must be added to get the 8-bit address (that is, 01011100 or
0x5C). Data is sent over the serial bus in sequences of nine
clock pulses: eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period because a low-to-high transition when
the clock is high might be interpreted as a stop signal. The
number of data bytes transmitted over the serial bus in a single
read or write operation is limited only by what the master and
slave devices can handle.
When reading data from a register, there are two possibilities:
•If the ADT7476 address pointer register value is unknown,
or not the desired value, it must first be set to the correct
value before data can be read from the desired data register.
This is done by performing a write to the ADT7476 as
before, but only the data byte containing the register
address is sent because no data is written to the register
(see Figure 19). A read operation is then performed
consisting of the serial bus address, R/Wbit set to 1,
followed by the data byte read from the data register (see
Figure 20.)
•If the address pointer register is already at the desired
address, data can be read from the corresponding data
register without first writing to the address pointer register
(see Figure 20).
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7476
START BY
MASTER
19
1
ACK. BY
ADT7476
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7476
STOP BY
MASTER
19
SCL (CONTINUED)
SDA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
05382-019
Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
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ADT7476
Rev. B | Page 15 of 72
R/W
0
SCL
SDA 10
11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7476 STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE
119
ACK. BY
ADT7476
9
05382-020
Figure 19. Writing to the Address Pointer Register Only
R/W
0
SCL
SDA 1011A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
NO ACK. BY
MASTER STOP BY MASTER
START BY
MASTER FRAME 1
SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT7476
119
ACK. BY
ADT7476
9
05382-021
Figure 20. Reading Data from a Previously Selected Register
It is possible to read a data byte from a data register without
first writing to the address pointer register if the address pointer
register is already at the correct value. However, it is not possible
to write data to a register without writing to the address pointer
register because the first data byte of a write is always written to
the address pointer register.
In addition to supporting the send byte and receive byte
protocols, the ADT7476 also supports the read byte protocol.
(See System Management Bus (SMBus) Specifications Version 2
for more information; it is available at www.smbus.org/specs.)
If several read operations or write operations must be performed
in succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
WRITE OPERATIONS
The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the ADT7476
are discussed in this section and the next section. The following
abbreviations are used in the diagrams:
S – Start
P – Stop
R – Read
W – Write
A – Acknowledge
A– No acknowledge
The ADT7476 uses the following SMBus write protocols.
Send Byte
In this operation, the master device sends a single command
byte to a slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
For the ADT7476, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address. This operation is illustrated in Figure 21.
05382-022
SLAVE
ADDRESS WASAP
REGISTER
ADDRESS
231564
Figure 21. Setting a Register Address for Subsequent Read
If the master is required to read data from the register immedi-
ately after setting up the address, it can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read without asserting an intermediate stop
condition.
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ADT7476
Rev. B | Page 16 of 72
Write Byte
In this operation, the master device sends a command byte
and one data byte to the slave device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by
the write bit (active low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA,
and the transaction ends.
This operation is illustrated in Figure 22.
05382-023
SLAVE
ADDRESS W A DATASA
REGISTER
ADDRESS
23154
AP
678
Figure 22. Single-Byte Write to a Register
READ OPERATIONS
The ADT7476 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address is set up previously. In this
operation, the master device receives a single byte from a slave
device, as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
read bit (high).
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
In the ADT7476, the receive byte protocol is used to read a
single byte of data from a register whose address has been set by
a send byte or write byte operation. This operation is illustrated
in Figure 23.
05382-024
SLAVE
ADDRESS DATAARSA
24315
P
6
Figure 23. Single-Byte Read from a Register
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
The SMBALERT output can be used as either an interrupt out-
put or an SMBALERT. One or more outputs can be connected
to a common SMBALERT line connected to the master. If a device
SMBALERT line goes low, the following procedure occurs:
1. SMBALERT is pulled low.
2. The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
3. The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of this device is now known and can
be interrogated in the usual way.
4. If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
5. Once the ADT7476 has responded to the alert response
address, the master must read the status registers, and the
SMBALERT is cleared only if the error condition is gone.
SMBus TIMEOUT
The ADT7476 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7476 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
be disabled.
Configuration Register 1 (0x40)
Bit 6 TODIS = 0, SMBus timeout disabled (default)
Bit 6 TODIS = 1, SMBus timeout enabled
VIRUS PROTECTION
To prevent rogue programs or viruses from accessing critical
ADT7476 register settings, the lock bit can be set. Setting Bit 1
of Configuration Register 1 (0x40) sets the lock bit and locks
critical registers. In this mode, certain registers can no longer be
written to until the ADT7476 is powered down and powered up
again. For more information on which registers are locked, see
the Register Tables section.
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ADT7476
Rev. B | Page 17 of 72
VOLTAGE MEASUREMENT INPUT
The ADT7476 has four external voltage measurement channels.
It can also measure its own supply voltage, VCC. Pin 20 to Pin 23
can measure 5 V, 12 V, and 2.5 V supplies and the processor
core voltage VCCP (0 V to 3 V input). The VCC supply voltage
measurement is carried out through the VCC pin (Pin 4). The
2.5 V input can be used to monitor a chipset supply voltage in
computer systems.
ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive-
approximation, analog-to-digital converter. This has a resolution
of 10 bits. The basic input range is 0 V to 2.25 V, but the inputs
have built-in attenuators to allow measurement of 2.5 V, 3.3 V, 5
V, 12 V, and the processor core voltage VCCP without any exter-
nal components. To allow the tolerance of these supply voltages,
the ADC produces an output of 3/4 full scale (768 dec or 300
hex) for the nominal input voltage and, therefore, has adequate
headroom to deal with overvoltages.
INPUT CIRCUITRY
The internal structure for the analog inputs is shown in
Figure 24. The input circuit consists of an input protection
diode, an attenuator, and a capacitor to form a first-order low-
pass filter that gives input immunity to high frequency noise.
V
CCP
17.5kΩ
52.5kΩ35pF
2
.5
V
IN
45kΩ
94kΩ30pF
3
.3
V
IN
68kΩ
71kΩ30pF
5V
IN
93kΩ
47kΩ30pF
12V
IN
120k
Ω
20kΩ30pF
0
5382-025
MUX
Figure 24. Structure of Analog Inputs
VOLTAGE MEASUREMENT REGISTERS
Register 0x20, 2.5 V Measurement = 0x00 default
Register 0x21, VCCP Measurement = 0x00 default
Register 0x22, VCC Measurement = 0x00 default
Register 0x23, 5 V Measurement = 0x00 default
Register 0x24, 12 V Measurement = 0x00 default
VOLTAGE LIMIT REGISTERS
Associated with each voltage measurement channel is a high
and low limit register. Exceeding the programmed high or low
limit causes the appropriate status bit to be set. Exceeding either
limit can also generate SMBALERT interrupts.
Register 0x44, 2.5 V Low Limit = 0x00 default
Register 0x45, 2.5 V High Limit = 0xFF default
Register 0x46, VCCP Low Limit = 0x00 default
Register 0x47, VCCP High Limit = 0xFF default
Register 0x48, VCC Low Limit = 0x00 default
Register 0x49, VCC High Limit = 0xFF default
Register 0x4A, 5 V Low Limit = 0x00 default
Register 0x4B, 5 V High Limit = 0xFF default
Register 0x4C, 12 V Low Limit = 0x00 default
Register 0x4D, 12 V High Limit = 0xFF default
Table 9 shows the input ranges of the analog inputs and output
codes of the 10-bit ADC.
When the ADC is running, it samples and converts a voltage
input in 0.7 ms and averages 16 conversions to reduce noise; a
measurement takes nominally 11 ms.
EXTENDED RESOLUTION REGISTERS
Voltage measurements can be made with higher accuracy using
the extended resolution registers (0x76 and 0x77). Whenever
the extended resolution registers are read, the corresponding
data in the voltage measurement registers (0x20 to 0x24) is
locked until their data is read. That is, if extended resolution is
required, the extended resolution register must be read first
immediately followed by the appropriate voltage measurement
register.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE
MEASUREMENTS
Several other functions are available on the ADT7476 to offer
the system designer increased flexibility.
Turn-Off Averaging
For each voltage/temperature measurement read from a value
register, 16 readings have been made internally and the results
averaged before being placed into the value register. When faster
conversions are needed, setting Bit 4 of Configura-tion Register 2
(0x73) turns averaging off. This effectively gives a reading that is
16 times faster, but the reading can be noisier. The default round-
robin cycle time is 146.5 ms.
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ADT7476
Rev. B | Page 18 of 72
Table 6. Conversion Time with Averaging Disabled
Channel Measurement Time (ms)
Voltage Channels 0.7
Remote Temperature 1 7
Remote Temperature 2 7
Local Temperature 1.3
When Bit 7 of Configuration Register 6 (0x10) is set, the default
round-robin cycle time increases to 240 ms.
Bypass All Voltage Input Attenuators
Setting Bit 5 of Configuration Register 2 (0x73) removes the
attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12 V
inputs. This allows the user to directly connect external sensors
or rescale the analog voltage measurement inputs for other
applications. The input range of the ADC without the attenua-
tors is 0 V to 2.25 V.
Bypass Individual Voltage Input Attenuators
Bits [7:4] of Configuration Register 4 (0x7D) can be used to
bypass individual voltage channel attenuators.
Table 7. Bypassing Individual Voltage Input Attenuators
Using Configuration Register 4 (0x7D)
Bit Channel Attenuated
4 Bypass 2.5 V attenuator
5 Bypass VCCP attenuator
6 Bypass 5 V attenuator
7 Bypass 12 V attenuator
Configuration Register 2 (0x73)
Bit 4 = 1, averaging off.
Bit 5 = 1, bypass input attenuators.
Bit 6 = 1, single-channel convert mode.
TACH1 Minimum High Byte Register (0x55)
Bits [7:5] select ADC channel for single-channel convert mode.
Single-Channel ADC Conversion
While single-channel mode is intended as a test mode that can
be used to increase sampling times for a specific channel,
therefore helping to analyze that channel’s performance in
greater detail, it can also have other applications.
Setting Bit 6 of Configuration Register 2 (0x73) places the
ADT7476 into single-channel ADC conversion mode. In this
mode, the ADT7476 can read a single voltage channel only. The
selected voltage input is read every 0.7 ms. The appropriate
ADC channel is selected by writing to Bits [7:5] of the TACH1
minimum high byte register (0x55).
Table 8. Programming Single-Channel ADC Mode
Register 0x55, Bits [7:5] Channel Selected1
000 2.5 V
001 VCCP
010 VCC
011 5 V
100 12 V
101 Remote 1 temperature
110 Local temperature
111 Remote 2 temperature
1In the process of configuring single-channel ADC conversion mode, the
TACH1 minimum high byte is also changed, possibly trading off TACH1
minimum high byte functionality with single-channel mode functionality.
.
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ADT7476
Rev. B | Page 19 of 72
Table 9. 10-Bit ADC Output Code vs. VIN
Input Voltage ADC Output
12 VIN 5 VIN V
CC (3.3 VIN)2.5 VIN V CCP Decimal Binary (10 Bits)
<0.0156 <0.0065 <0.0042 <0.0032 <0.00293 0 00000000 00
0.0156 to 0.0312 0.0065 to 0.0130 0.0042 to 0.0085 0.0032 to 0.0065 0.0293 to 0.0058 1 00000000 01
0.0312 to 0.0469 0.0130 to 0.0195 0.0085 to 0.0128 0.0065 to 0.0097 0.0058 to 0.0087 2 00000000 10
0.0469 to 0.0625 0.0195 to 0.0260 0.0128 to 0.0171 0.0097 to 0.0130 0.0087 to 0.0117 3 00000000 11
0.0625 to 0.0781 0.0260 to 0.0325 0.0171 to 0.0214 0.0130 to 0.0162 0.0117 to 0.0146 4 00000001 00
0.0781 to 0.0937 0.0325 to 0.0390 0.0214 to 0.0257 0.0162 to 0.0195 0.0146 to 0.0175 5 00000001 01
0.0937 to 0.1093 0.0390 to 0.0455 0.0257 to 0.0300 0.0195 to 0.0227 0.0175 to 0.0205 6 00000001 10
0.1093 to 0.1250 0.0455 to 0.0521 0.0300 to 0.0343 0.0227 to 0.0260 0.0205 to 0.0234 7 00000001 11
0.1250 to 0.14060 0.0521 to 0.0586 0.0343 to 0.0386 0.0260 to 0.0292 0.0234 to 0.0263 8 00000010 00
•
•
•
4.0000 to 4.0156 1.6675 to 1.6740 1.1000 to 1.1042 0.8325 to 0.8357 0.7500 to 0.7529 256 (¼ scale) 01000000 00
•
•
•
8.0000 to 8.0156 3.3300 to 3.3415 2.2000 to 2.2042 1.6650 to 1.6682 1.5000 to 1.5029 512 (½ scale) 10000000 00
•
•
•
12.0000 to 12.0156 5.0025 to 5.0090 3.3000 to 3.3042 2.4975 to 2.5007 2.2500 to 2.2529 768 (¾ scale) 11000000 00
•
•
•
15.8281 to 15.8437 6.5983 to 6.6048 4.3527 to 4.3570 3.2942 to 3.2974 2.9677 to 2.9707 1013 11111101 01
15.8437 to 15.8593 6.6048 to 6.6113 4.3570 to 4.3613 3.2974 to 3.3007 2.9707 to 2.9736 1014 11111101 10
15.8593 to 15.8750 6.6113 to 6.6178 4.3613 to 4.3656 3.3007 to 3.3039 2.9736 to 2.9765 1015 11111101 11
15.8750 to 15.8906 6.6178 to 6.6244 4.3656 to 4.3699 3.3039 to 3.3072 2.9765 to 2.9794 1016 11111110 00
15.8906 to 15.9062 6.6244 to 6.6309 4.3699 to 4.3742 3.3072 to 3.3104 2.9794 to 2.9824 1017 11111110 01
15.9062 to 15.9218 6.6309 to 6.6374 4.3742 to 4.3785 3.3104 to 3.3137 2.9824 to 2.9853 1018 11111110 10
15.9218 to 15.9375 6.6374 to 6.4390 4.3785 to 4.3828 3.3137 to 3.3169 2.9853 to 2.9882 1019 11111110 11
15.9375 to 15.9531 6.6439 to 6.6504 4.3828 to 4.3871 3.3169 to 3.3202 2.9882 to 2.9912 1020 11111111 00
15.9531 to 15.9687 6.6504 to 6.6569 4.3871 to 4.3914 3.3202 to 3.3234 2.9912 to 2.9941 1021 11111111 01
15.9687 to 15.9843 6.6569 to 6.6634 4.3914 to 4.3957 3.3234 to 3.3267 2.9941 to 2.9970 1022 11111111 10
>15.9843 >6.6634 >4.3957 >3.3267 >2.9970 1023 11111111 11
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ADT7476
Rev. B | Page 20 of 72
VID CODE MONITORING
The ADT7476 has five dedicated voltage ID (VID code) inputs.
These are digital inputs that can be read back through the VID
register (0x43) to determine the processor voltage required or
being used in the system. Five VID code inputs support VRM9.x
solutions. In addition, Pin 21 (12 V input) can be reconfigured as
a sixth VID input to satisfy future VRM requirements.
VID Code Register (0x43)
Bit 0 = VID0, reflects logic state of Pin 5.
Bit 1 = VID1, reflects logic state of Pin 6.
Bit 2 = VID2, reflects logic state of Pin 7.
Bit 3 = VID3, reflects logic state of Pin 8.
Bit 4 = VID4, reflects logic state of Pin 19.
Bit 5 = VID5, reconfigurable 12 V input. This bit reads 0 when
Pin 21 is configured as the 12 V input. This bit reflects the logic
state of Pin 21 when the pin is configured as VID5.
VID CODE INPUT THRESHOLD VOLTAGE
The switching threshold for the VID code inputs is approximately
1 V. To enable future compatibility, it is possible to reduce the
VID code input threshold to 0.6 V. Bit 6 (THLD) of the VID
register (0x43) controls the VID input threshold voltage.
VID Code Register (0x43)
Bit 6 THLD = 0, VID switching threshold = 1 V,
VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V.
Bit 6 THLD = 1, VID switching threshold = 0.6 V,
VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V.
Bit 7 VIDSEL = 0, Pin 21 functions as a 12 V measurement
input. Software can read this bit to determine that there are five
VID inputs being monitored. Bit 5 of Register 0x43 (VID5)
always reads back 0. Bit 0 of Status Register 2 (0x42) reflects
12 V out-of-limit measurements.
Bit 7 VIDSEL = 1, Pin 21 functions as the sixth VID code input
(VID5). Software can read this bit to determine that there are
six VID inputs being monitored. Bit 5 of Register 0x43 reflects
the logic state of Pin 21. Bit 0 of Status Register 2 (0x42) reflects
VID code changes.
Reconfiguring Pin 21 as VID5 Input
Pin 21 can be reconfigured as a sixth VID code input (VID5)
for VRM10 compatible systems. Because the pin is configured
as VID5, it is not possible to monitor a 12 V supply.
Bit 7 of the VID configuration register (0x43) determines the
function of Pin 21. System or BIOS software can read the state
of Bit 7 to determine whether the system is designed to monitor
12 V or is monitoring a sixth VID input.
VID CODE CHANGE DETECT FUNCTION
The ADT7476 has a VID code change detect function. When
Pin 21 is configured as the VID5 input, VID code changes are
detected and reported back by the ADT7476. Bit 0 of Interrupt
Status Register 2 (0x42) is the 12 V/VC bit and denotes a VID
change when set. The VID code change bit is set when the logic
states on the VID inputs are different than they were 11 µs
previously. The change of VID code is used to generate an
SMBALERT interrupt. If an SMBALERT interrupt is not
required, Bit 0 of Interrupt Mask Register 2 (0x75), when set,
prevents SMBALERTs from occurring on VID code changes.
Interrupt Status Register 2 (0x42)
Bit 0 12 V/VC = 0, if Pin 21 is configured as VID5, Logic 0
denotes no change in VID code within the last 11 µs.
Bit 0 12 V/VC = 1, if Pin 21 is configured as VID5, Logic 1 means
that a change has occurred on the VID code inputs within the
last 11 µs. An SMBALERT is generated if this function is enabled.
PROGRAMMING THE GPIOS
The ADT7476 follows an upgrade path from the ADM1027 to
ADT7476. To maintain consistency between versions, it is
necessary to omit references to GPIO5. As a result, there are six
GPIOs as follows: GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, and
GPIO6.
Setting Bit 4 of Configuration Register 5 (0x7C) to 1 enables
GPIO functionality. This turns all pins configured as VID
inputs into general-purpose outputs. Writing to the corres-
ponding VID bit in the VID register (0x43) sets the polarity for
the corresponding GPIO. GPIO6 can be programmed indepen-
dently as an input/output using Bits [3:2] of Configuration
Register 5 (0x7C).
TEMPERATURE MEASUREMENT METHOD
Local Temperature Measurement
The ADT7476 contains an on-chip band gap temperature
sensor whose output is digitized by the on-chip, 10-bit ADC.
The 8-bit MSB temperature data is stored in the temperature
registers (Register 0x25, Register 0x26, and Register 0x27).
Because both positive and negative temperatures can be
measured, the temperature data is stored in Offset 64 format or
twos complement format, as shown in Table 10 and Table 11.
Theoretically, the temperature sensor and ADC can measure
temperatures from −63°C to +127°C (or −61°C to +191°C in
the extended temperature range) with a resolution of 0.25°C.
However, this exceeds the operating temperature range of the
device, so local temperature measurements outside the ADT7476
operating temperature range are not possible.
Remote Temperature Measurement
The ADT7476 can measure the temperature of two remote
diode sensors or diode-connected transistors connected to
Pin 17 and Pin 18 or to Pin 15 and Pin 16.
The forward voltage of a diode or diode-connected transistor
operated at a constant current exhibits a negative temperature
coefficient of about −2 mV/°C. Unfortunately, the absolute
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