Analog Devices ADE9000 Product manual

ADE9000 Technical Reference Manual
UG-1098
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Functionality and Features of the ADE9000 High Performance, Multiphase Energy
and Power Quality Monitoring IC
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 86
SCOPE
This reference manual provides a detailed description of the ADE9000 functionality and features. This document must be used in
conjunction with the ADE9000 data sheet.
FUNCTIONAL BLOCK DIAGRAM
CF1
CF2
DIGITAL BLOCK
SINC + DECIMATION
DSPENGINE
TOTAL AND FUNDAMENTAL:
{ IRMS, VRMS, ACTIVE,
REACTIVE,
APPARENT POWER
AND ENERGY }
VTHD, ITHD, FREQUENCY,
PHASE ANGLE,
POWER FACTOR,
VPEAK, IPEAK, DIP,
SWELL, OVERCURRENT,
FAST RMS,
10/12 CYCLE RMS,
PHASE SEQ ERROR
SAR
TEMP
SENSOR
SPI
INTERFACE
CLKIN
CLKOUT
SCLK
MISO
MOSI
CS
GND
IAP
IAN
VAP
VAN ADC
PGA
ADC
PGA
ADE9000
ADC
PGA
ADC
PGA
ADC
PGA
ADC
PGA
RESAMPLING
ENGINE
WAVEFFORM BUFFER
(32ksps, 8ksps ADC SAMPLES
OR RESAMPLED DATA)
USER ACCESSIBLE
REGISTERS
DIGITAL TO
FREQUENCY
CONVERSION (CF)
CF3/ZX
CF4/EVENT/DREADY
1.25V
REFERENCE
RESET
IRQ0
IRQ1
EVENT
INTERRUPTS
IBP
IBN
VBP
VBN
ICP
ICN
VCP
VCN
INP
INN
DIGITAL TO
FREQUENCY
CONVERSION
(CF)
15523-001
Figure 1.

UG-1098 ADE9000 Technical Reference Manual
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TABLE OF CONTENTS
Scope .................................................................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Analog-to-Digital Converter (ADC) ............................................. 3
Overview........................................................................................ 3
Analog Input Configuration ....................................................... 3
Internal RF Immunity Filter ....................................................... 4
Modes of Operation ..................................................................... 4
Output Data Rates and Format................................................... 4
Voltage Reference ......................................................................... 5
Crystal Oscillator/External Clock .................................................. 6
Power Management.......................................................................... 7
Power Modes................................................................................. 7
Power-On Sequence ..................................................................... 7
Brownout Detection..................................................................... 8
Reset ............................................................................................... 8
Changing Power Modes............................................................... 8
Measurements ................................................................................... 9
Current Channel Measurement Update Rates ......................... 9
Full-Scale Codes ......................................................................... 13
Power and Filter-Based RMS Measurement Algorithms...... 13
Energy Measurements Overview ............................................. 17
Energy Accumulation ................................................................ 18
Power Accumulation.................................................................. 23
Power Quality Measurements................................................... 24
Temperature ................................................................................ 31
Accessing On-Chip Data ............................................................... 32
SPI Protocol Overview............................................................... 32
SPI Write ...................................................................................... 33
SPI Read....................................................................................... 33
SPI Burst Read ............................................................................ 33
SPI Protocol CRC ....................................................................... 34
Additional Communication Verification Registers............... 34
CRC of Configuration Registers............................................... 35
Waveform Buffer ............................................................................ 36
Fixed Data Rate Waveforms...................................................... 36
Fixed Data Rate Waveforms Filling and Trigger-Based
Modes........................................................................................... 37
Resampled Waveforms .............................................................. 39
Configuring the Waveform Buffer........................................... 40
Burst Read Waveform Buffer Samples from SPI.................... 40
Interrupts/EVENT ......................................................................... 43
Interrupts (IRQ0 and IRQ1)..................................................... 43
EVENT......................................................................................... 43
Status Bits in Additional Registers ........................................... 43
Applying the ADE9000 to Different Metering
Configurations ................................................................................ 44
Non-Blondel Compliant Meters............................................... 45
Applying the ADE9000 to a 4-Wire Wye Service .................. 46
Applying the ADE9000 to a 3-Wire Delta Service................. 47
Applying the ADE9000 to a Non-Blondel Compliant 4-Wire
Wye Service................................................................................. 48
Applying the ADE9000 to a Non-Blondel Compliant 4-Wire
Delta Service ............................................................................... 48
ADE9000 Service Type Summary............................................ 48
Quick Start....................................................................................... 50
Calibration....................................................................................... 51
System Parameters ..................................................................... 51
RMS Calibration......................................................................... 51
Phase Calibration ....................................................................... 51
Power Calibration....................................................................... 52
Conversion Constants................................................................ 52
Register Information...................................................................... 53
Register Details ........................................................................... 65
REVISION HISTORY
3/2017—Revision 0: Initial Version

ADE9000 Technical Reference Manual UG-1098
Rev. 0 | Page 3 of 86
ANALOG-TO-DIGITAL CONVERTER (ADC)
OVERVIEW
The ADE9000 incorporates seven independent, second-order,
Σ-Δ ADCs that sample simultaneously. Each ADC is 24 bits and
supports fully differential and pseudo differential inputs, which
can go above and below ground. The ADE9000 includes a low
noise, low drift, internal band gap reference. Set the EXT_REF
bit in the CONFIG1 register if using an external voltage
reference. Each ADC contains a programmable gain amplifier
which allows a gain of 1, 2, or 4.
ANALOG INPUT CONFIGURATION
There is no internal buffering; the impedance of the ADE9000
depends on the programmable gain selected.
Fully Differential Inputs
The input signals on the IAP, IAN, IBP, IBN, ICP, ICN, VAP,
VAN, VBP, VBN, VCP, and VCN pins must not exceed 0.6 V.
The differential full-scale input range of the ADCs is ±1 V peak
(0.707 V rms).
Figure 2 and Figure 3 show two common types of input signals
for an energy monitoring application. Figure 2 shows the
maximum input allowed with differential antiphase signals.
A current transformer with center tapped burden resistor
generates differential, antiphase signals. Figure 3 shows the
maximum input signal with pseudo differential signals, similar
to those obtained when sensing the mains voltage signal through
a resistive divider or using a Rogowski coil current sensor.
The following conditions must be met for the input signals with
gain = 1:
•|IAP, IAN, IBP, IBN, ICP,ICN, VAP, VAN, VBP, VBN, VCP,
and VCN| ≤ +0.6 V peak
•|IxP − IxN| ≤ +1 V peak, |VxP − VxN| ≤ +1 V peak
Each ADC contains a programmable gain amplifier which allows
a gain of 1, 2, or 4. The ADC produces full-scale output codes
with an input of ±1 V. With a gain of 1, this full-scale output
corresponds to a differential antiphase input of 0.707 V rms,
as shown in Figure 2. At a gain of 2, full-scale output codes are
produced with an input of 0.353 V rms, as shown in Figure 3. At
gain of 4, full-scale output codes are generated with a 0.1765 V rms
input signal. Note that the voltages on the xP and xN pins must
be within ±0.6 V, as specified in the data sheet.
Write the x_GAIN bits in the PGA_GAIN register to configure
the gain for each channel.
+0.1V
0
+0.6V
–0.4V
0x0471 44AD =
NOTES
1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED
AFTER GAINAND PHASE COMPENSATION.
+74,532,013
0xFB8E BB53 =
–74,532,013
CHANNEL(x_PCF) WAVEFORM
DATARANGE WITH x_GAIN = 1
xP INPUT PIN
xM INPUT PIN
+0.1V
+0.6V
–0.4V
15523-002
Figure 2. Maximum Input Signal with Differential Antiphase Input with
Common Mode Voltage = 0.1 V, Gain = 1
+0.1V
0
+0.6V
–0.4V
+0.1V
0x0471 44AD =
+74,532,013
0xFB8E BB53 =
–74,532,013
CHANNEL(x_PCF) WAVEFORM
DATARANGE WITH x_GAIN = 2
xP INPUT PIN
xM INPUT PIN
NOTES
1. x_PCF IS THE INSTANTANEOUS WAVEFORM OBTAINED
AFTER GAINAND PHASE COMPENSATION.
15523-003
Figure 3. Maximum Input Signal with Pseudo Differential Input with
Common Mode Voltage = 0.1 V, Gain = 2

UG-1098 ADE9000 Technical Reference Manual
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Interfacing to Current and Voltage Sensors
Figure 4 and Figure 6 show the recommended circuits to
connect to current transformer sand Rogowski coil current
sensors. Figure 5 shows the interface circuit to measure the
mains voltage.
The antialiasing filter corner is chosen around 7 kHz to provide
sufficient attenuation of out of band signals near the modulator
clock frequency. The same RC filter corner is used on voltage
channels as well, to avoid phase errors between current and
voltage signals. Note that the Rogowski coil input network has a
second-order antialias filter to further reduce out of band noise
because the Rogowski sensor has a 1/f response.
1kΩ
Rb1 22nF
AGND
IxP
IxN
0.707Vrms max
CT
I
Rb2
1kΩ
22nF
AGND
15523-004
Figure 4. Application Circuit with Current Transformer Current Sensor
1MΩ
1kΩ 22nF
AGND
VxP
VxN
0.240V rms
240V rms
1kΩ 22nF
NEUTRAL
PHASE
AGND
15523-005
Figure 5. Application Circuit with Voltage Sensed Through Resistor Divider
1kΩ
IxP
IxN
0.3535V rms
22nF
22nF
100Ω
1kΩ
22nF22nF
100Ω
15523-006
Figure 6. Application Circuit with Rogowski Coil Current Sensor
INTERNAL RF IMMUNITY FILTER
Energy metering applications require the meter to be immune
to external radio frequency fields of 30 V/m, from 80 MHz up
to 10 GHz, according to IEC 61000-4-3. The ADE9000 has
internal antialiasing filters to improve performance in this
testing because it is difficult to filter these signals externally.
The second-order, internal low-pass filter (LPF) has a corner
frequency of 10 MHz. Note that external antialias filters are
required to attenuate frequencies above 7 kHz, as shown in the
Interfacing to Current and Voltage Sensors section.
MODES OF OPERATION
Each ADC has two modes of operation: normal mode and
disabled mode.
In the normal mode of operation, ADCs are turned on and
sample continuously. The CHNL_DIS register can be used to
disable the ADCs individually.
There are 2 different power modes available in the ADE9000
(see the Power Modes section). All ADCs are turned on in
PSM0 power mode. In PSM3 mode, all ADCs are disabled and
cannot be turned on.
Table 1. ADC Operation in PSMx Power Modes
PSMx Power Mode ADC Mode of Operation
PSM0 Normal (on)
PSM3 Disabled (always off)
OUTPUT DATA RATES AND FORMAT
When a conversion has been completed, the DREADY bit of the
STATUS0 register is set to 1. If the CF4_CFG[3:2] bits in the
CONFIG1 register are equal to 11, the CF4/EVENT/DREADY
pin corresponds to DREADY and pulses high to indicate when
seven new ADC results are ready.
In the ADE9000, the modulator sampling rate (MODCLK) is
fixed at 2.048 MHz (CLKIN/12 = 24.576/12). The output data
rate of the sinc filter is MODCLK/64, whereas the low-pass
filter/decimator stage yields an output rate 4 times slower than
the sinc filter output rate. Figure 7 shows the digital filtering
that takes the 2.048 MHz ADC samples and creates waveform
information at a decimated rate of 32 kHz or 8 kHz.
ANALOG
INPUT Σ-Δ × 7
DIGITAL
MULTIBIT SINC4 IIR LPF/
DECIMATOR
DIGITAL
WAVEFORM
WAVEFORM
BUFFER
(×7 CHANNELS)
2.048MHz 32kHz 8kHz
15523-007
Figure 7. Datapath Following ADC Stage
The output data rates are summarized in Table 2.
Table 2. Output Data Rates
Parameter Output Data Rate
CLKIN Frequency 24.576 MHz
ADC Modulator Clock, MODCLK 2.048 MHz
SINC Output Data Rate, SINC_ODR 32 kHz
Low-Pass Filter Output Data Rate 8 kHz
3 dB Bandwidth 3.2 kHz

ADE9000 Technical Reference Manual UG-1098
Rev. 0 | Page 5 of 86
The ADC data in the waveform buffer is stored as 32-bit data by
shifting left by 4 bits and sign extending, as shown in Table 3.
Table 3. 32-Bit ADC Data Format
Bits[31:28] Bits[27:4] Bits[3:0]
SE ADC_DATA[23:0] 0000
The expected output code in the waveform buffer from the sinc
filter when input is at 1 V peak is 67,107,786 (decimal). The
expected output code in the waveform buffer from the decimator
filter when input is at 1 V peak is 74,518,668. See the Waveform
Buffer section for more information.
VOLTAGE REFERENCE
The ADE9000 supports a 1.25 V internal reference. An external
reference can be connected between the REFIN and REFGND
pins. When using an external voltage reference, set the
EXT_REF bit of the CONFIG1 register, which disables the
internal reference buffer.

UG-1098 ADE9000 Technical Reference Manual
Rev. 0 | Page 6 of 86
CRYSTAL OSCILLATOR/EXTERNAL CLOCK
The ADE9000 contains a crystal oscillator. Alternatively, a
digital clock signal can be applied at the CLKIN pin of the
ADE9000.
When a crystal is used as the clock source for the ADE9000,
attach the crystal and the ceramic capacitors, with capacitances
of CL1 and CL2, as shown in Figure 8. It is not recommended to
attach an external feedback resistor in parallel to the crystal.
When a digital clock signal is applied at the CLKIN pin, the
inverted output is available at the CLKOUT pin. This output is
not buffered internally and cannot be used to drive any other
external devices directly. Note that CLKOUT is available in
PSM0 operating mode only.
C
P1
C
L1
CLKIN CLKOUT29 30
C
P2
C
L2
1.75kΩ2.5kΩ
C
IN1
C
IN2
24.576MHz
2.5MΩ
15523-008
Figure 8. Crystal Application Circuit
Crystal Selection
The transconductance of the crystal oscillator circuit in the
ADE9000, gm, is provided in the data sheet. It is recommended
to have 3 to 5 times more gm than the calculated gmCRITICAL for
the crystal.
The following equation shows how to calculate the gmCRITICAL
for the crystal from information given in the crystal data sheet:
gmCRITICAL = 4 × ESRMAX × 1000 × (2 × π× fCLK(Hz))2× (C0+ CL)2
where:
gmCRITICAL is the minimum gain required to start the crystal,
expressed in mA/V.
ESRMAX is the maximum ESR, expressed in ohms.
fCLK is 24.576 MHz, expressed in Hz as 24.576 × 106.
C0is the maximum shunt capacitance, expressed in farads.
CLis the load capacitance, expressed in farads.
Crystals with low ESR and smaller load capacitance have a
lower gmCRITICAL and are easier to drive.
The ADE9000 evaluation board uses a crystal manufactured by
Abracon (Part Number ABLS-24.576MHZ-8-L4Q-F-T), which
has a maximum ESR of 40 Ω, load capacitance of 8 pF, and
maximum shunt capacitance of 7 pF, which results in a gmCRITICAL
of 0.86 mA/V:
gmCRITICAL = 4 × ESRMAX × 1000 × (2 × π× fCLK(Hz))2× (C0+ CL)2
gmCRITICAL = 4 × 40 × 1000 × (2 × π× 24.576 × 106)2× (7 ×
10−12 + 8 × 10−12)2= 0.86
The gain of the crystal oscillator circuit in the ADE9000, gm,
provided in the data sheet is more than 5 times gmCRITICAL;
therefore, there is sufficient margin to start up this crystal.
Load Capacitor Calculation
Crystal manufacturers specify the combined load capacitance
across the crystal, CL. The capacitances in Figure 8 can be
described as follows:
•CP1and CP2: parasitic capacitances on the clock pins
formed due to printed circuit board (PCB) traces.
•Cin1and Cin2: internal capacitances of the CLKIN and
CLKOUT pins respectively.
•CL1and CL2: selected load capacitors to get the correct
combined CL for the crystal.
The internal pin capacitances, Cin1 and Cin2, are 4 pF each, as
shown in the data sheet. To find the values of CP1and CP2,
measure the capacitance on each of the clock pins of the PCB,
CLKIN and CLKOUT, respectively, with respect to the AGND
pin. If the measurement is done after soldering the IC to the
PCB, subtract out the 4 pF internal capacitance of the clock pins
to find the actual value of parasitic capacitance on each of the
crystal pins.
To select the appropriate capacitance value for the ceramic
capacitors, calculate CL1and CL2from the following equation:
CL = [(CL1+ CP1+ CIN1) × (CL2+ CP2+ CIN2)]/(CL1+
CP1+ CIN1 + CL2+ CP2+ CIN2) (1)
Select CL1and CL2such that the total capacitance on each clock
pins is
CL1+ CP1+ CIN1 = CL2+ CP2+ CIN2 (2)
Using Equation 1 and Equation 2, the values of CL1and CL2can
be calculated.
Load Capacitor Calculation Example
If a crystal with load capacitance specification of 8 pF is selected
and the measured parasitic capacitances from the PCB traces
are CP1 = CP2 = 2 pF, Equation 1 implies that
CL = [(CL1+ CP1+ CIN1) × (CL2+ CP2+ CIN2)]/(CL1+
CP1+ CIN1 + CL2+ CP2+ CIN2)
8 pF = [(CL1+ 2 pF + 4 pF) × (CL2+ 2 pF + 4 pF)]/(CL1+
2 pF + 4 pF + CL2+ 2 pF + 4 pF)
Assuming that CL1= CL2, to satisfy Equation 2,
8 pF = [(CL1+ 6 pF) × (CL1+ 6 pF)]/(CL1+ 6 pF + CL1+ 6 pF)
8 pF = [(CL1+ 6 pF) × (CL1+ 6 pF)]/[2 × (CL1+ 6 pF)]
8 pF = (CL1+ 6 pF)/2
Therefore, CL1= CL2= 10 pF.
Based on this example, 10 pF ceramic capacitors are selected for
CL1and CL2.

ADE9000 Technical Reference Manual UG-1098
Rev. 0 | Page 7 of 86
POWER MANAGEMENT
POWER MODES
The ADE9000 offers two operating modes, PSM0 and PSM3.
The entry into the power modes is controlled by the PM1 and
PM0 pins. These pins are checked continuously to determine
which operating mode to enter. If it is desired to place the
ADE9000 into a low power reset state, PSM3 can be used.
POWER-ON SEQUENCE
After power is applied to the VDD pin of the ADE9000 IC, the
device checks the state of the PM0 and PM1 pins to check the
power supply mode (see the Power Modes section for more
information). If in PSM0 mode (PM1 and PM0 = 00 or 01) and
the RESET pin is high, the AVDD and DVDD low dropout
regulators (LDOs) are turned on when VDD reaches 2.4 V to
2.6 V. If the RESET pin is low, the AVDD and DVDD LDOs are
not turned on. Note that there is a clamp that limits the current
used to charge the AVDD and DVDD LDOs to 17 mA per LDO.
When AVDD and DVDD are both above 1.3 V to 1.5 V and
VDD is above 2.4 V to 2.6 V, a 20 ms timer is started to allow
additional time for the supplies to come to their normal
potentials (VDD between 2.97 V and 3.6 V, AVDD at 1.9 V, and
DVDD at 1.7 V). After this timer has elapsed, the crystal
oscillator is started.
The RSTDONE interrupt is triggered 26 ms later, bringing the
IRQ1 pin low and setting the RSTDONE bit in the STATUS1
register. The RSTDONE bit being set indicates to the user that
the ADE9000 has finished its power-up sequence. The user can
now configure the IC via the serial peripheral interface (SPI).
After configuring the device, write the RUN register to start the
DSP so that it starts making measurements. Note that registers
from Address 0x000 through Address 0x0FF and Address 0x400
through Address 0x5FF are restored to their default values
during power-on. Registers from Address 0x200 through
Address 0x3FF are cleared within 500 μs from when the RUN
register value changes from 0x0000 to 0x0001. Also note that
the waveform buffer, Address 0x800 through Address 0xFFF, is
not cleared after reset.
In PSM3 mode, the AVDD and DVDD LDOs are not turned
on. The RSTDONE interrupt does not occur, and the SPI port is
not available
HOST CONFIGURES
IC VIA SPI AND THEN
WRITES RUN
REGISTER TO START
MEASUREMENTS
20ms0.5ms
0
VOLTAGE (V)
2.4V TO 2.6V
2.97V TO 3.63V
VDD
DVDD
~26ms
1.7V
AVDD1.9V
VREF
ADE9000
1.3 TO 1.5V
RSTDONE
INTERRUPT
TRIGGERED
CRYSTAL
OSCILLATOR
STARTS
POR TIMER
TURNED ON
AVDD, DVDD
LDO TURNED
ON
POWER APPLIED
TO IC
IN PSM0
15523-009
Figure 9. ADE9000 Power-On Sequence for PSM0
Table 4. Power Modes (PSM0 and PSM3)
PSMx Power Mode Description PM1 Pin PM0 Pin Functions Available SPI Available?
PSM0 Normal mode 0 0 or 1 All functions Yes
PSM3 Idle 1 1 None No

UG-1098 ADE9000 Technical Reference Manual
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BROWNOUT DETECTION
Power-on reset (POR) circuits monitor the VDD, AVDD, and
DVDD supplies. If AVDD or DVDD drops below 1.3 V to 1.5 V, o r
VDD drops below 2.4 V to 2.6 V, t h e I C is held in reset and the
power-on sequence begins again, waiting until AVDD and DVDD
are above 1.3 V to 1.5 V and VDD is above 2.4 V to 2.6 V before
starting the 20 ms POR timer. A RSTDONE interrupt on IRQ1
indicates when the ADE9000 can be reinitialized via the SPI.
RESET
If the RESET pin goes low for 1 µs or the SWRST bit is set in the
CONFIG1 register to initiate a software reset, the AVDD and
DVDD LDOs are turned off. The power-on sequence resumes
from the point where the AVDD and DVDD LDOs are turned on
(see the Power-On Sequence section for details). For applications
that require putting the ADE9000 into a low power reset state,
it is recommended to use PSM3, which consumes roughly 2 µA,
instead of holding the IC in reset with the RESET pin low, which
consumes 100 µA (see the data sheet for the exact current
consumption).
CHANGING POWER MODES
The state of the PM1 and PM0 pins is continuously monitored.
If the power mode changes from PSM0 to PSM3 (PM1 and
PM0 = 11) for 1 µs, the AVDD and DVDD LDOs are turned off.
When the power mode switches back to PSM0, the power-on
sequence resumes from the point where the AVDD and DVDD
LDOs are turned on.

ADE9000 Technical Reference Manual UG-1098
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MEASUREMENTS
CURRENT CHANNEL MEASUREMENT UPDATE
RATES
Table 5 indicates the registers that hold current channel
measurements and the rate at which they update.
Table 5. Current Channel Measurement Update Rates
Register
Name Description
Update
Rate
AI_SINC_DAT IA sinc4 filter output 32 ksps
BI_SINC_DAT IB sinc4 filter output 32 ksps
CI_SINC_DAT IC sinc4 filter output 32 ksps
NI_SINC_DAT IN sinc4 filter output 32 ksps
AI_LPF_DAT IA sinc4 + IIR LPF filter output fDSP = 8 ksps
BI_LPF_DAT IB sinc4 + IIR LPF filter output fDSP = 8 ksps
CI_LPF_DAT IC sinc4 + IIR LPF filter output fDSP = 8 ksps
NI_LPF_DAT IN sinc4 + IIR LPF filter output fDSP = 8 ksps
AI_PCF
Instantaneous current on IA
f
DSP
= 8 ksps
BI_PCF Instantaneous current on IB fDSP = 8 ksps
CI_PCF Instantaneous current on IC fDSP = 8 ksps
NI_PCF Instantaneous current on IN fDSP = 8 ksps
AIRMS Filtered-based total rms of IA fDSP = 8 ksps
BIRMS Filtered-based total rms of IB fDSP = 8 ksps
CIRMS Filtered-based total rms of IC fDSP = 8 ksps
NIRMS Filtered-based total rms of IN fDSP = 8 ksps
ISUMRMS Filtered rms of vector sum (AI_PCF +
BI_PCF + CI_PCF ± NI_PCF); see the
Neutral Current RMS, Vector Current
Sum section
fDSP = 8 ksps
IPEAK Peak current channel sample; see the
Peak Detection section
fDSP = 8 ksps
ANGLx_xxx Voltage to current or current to
current phase angle; see the Angle
Measurement section
CLKIN/24 =
1024 ksps
ADC_REDIRECT Multiplexer
The ADE9000 provides a multiplexer that allows any ADC
output to be redirected to any digital processing datapath.
By default, each modulator is mapped to its corresponding
datapath. For example, the IAP and IAN pins go into the IA
modulator, which is mapped to the IA digital processing
datapath. Write to the ADC_REDIRECT register to change the
ADC to digital channel mapping.
The redirection can be useful to simplify layout, depending on if
the ADE9000 is on the top or bottom of the PCB, by redirecting
the IA ADC output to the IC digital datapath and the IC ADC
output to the IA digital datapath. To redirect the IA and IC
ADC outputs, write IA_DIN = 010 and IC_DIN = 000 in the
ADC_REDIRECT register.
Alternatively, the VA voltage channel output can be used for all
three datapaths by writing VB_DIN = 101 and VC_DIN = 101
in the ADC_REDIRECT register.
The neutral current channel does not offer a zero-crossing output
or angle measurements. To calibrate the phase of the neutral
current NI_PCF signal, direct the neutral current ADC output
to, for example, the Phase B digital current channel and check
how its angles correspond to Phase A by writing IA_DIN = 111.
REFERENCE
Σ-Δ
MODULATOR
VIN
IA_DIN[2:0] AI_SINC_DAT AI_LPF_DAT
IA MODULATOR IA DIGITAL DATAPATH
IA_MOD
011
IB_MOD
IC_MOD
IN_MOD
VA_MOD
VB_MOD
VC_MOD
IA_MOD
000
001
010
100
101
110
111
15523-010
Figure 10. ADC_REDIRECT Modulator to Digital Datapath Multiplexing
Current Channel Gain, xIGAIN
There are many sources of gain error in an energy metering
system. The current sensor, including current transformer
burden resistors, may have some error. There is part to part gain
error in the ADE9000 device itself, and the voltage reference
may have some variation (see the data sheet for the device
specifications).
The ADE9000 provides a current gain calibration register so
that each metering device has the same current channel scaling.
The current channel gain varies with xIGAIN as shown in the
following equation:





+=
27
2
1xIGAIN GainChannel
Current
Use this equation to calculate the xIGAIN value for a given
current channel gain:
xIGAIN = ROUND((Current Channel Gain − 1) × 227
The current channel gain can be positive or negative.
For example, to gain the current channel up by 10% to 1.1,
xIGAIN = ROUND((1.1 − 1) × 227 = 13421773 =
0x00CC_CCCD
To gain it down by 10% to 0.9,
xIGAIN = ROUND((0.9 − 1) × 227 = −1 × 107=
0xFF33_3333
It is also possible to use the current channel gain register to
change the sign of the current channel, which can be useful if
the current sensor was installed backwards. To compensate for
this, use current channel gain = −1.
xIGAIN = ROUND((−1 − 1) × 227 = −268435456 =
0xF000_0000
If the multipoint phase and gain feature is used, it is recommended
to use the xIGAIN for the main correction, done at the nominal
current for the meter (see the Multipoint Phase/Gain Calibration
section for more information).

UG-1098 ADE9000 Technical Reference Manual
Rev. 0 | Page 10 of 86
Note that for a given phase,
|Current Channel Gain × Voltage Channel Gain ×
Power Gain| ≤ 3.75
IB Calculation Using ICONSEL
Write the ICONSEL bit in ACCMODE to calculate IB = −IA − IC.
This setting can help save the cost of a current transformer in some
3-wire delta configurations. See the Applying the ADE9000 to a
3-Wire Delta Service section for more information.
High-Pass Filter
A high-pass filter is provided to remove dc offsets for accurate
rms and energy measurements.
The ADE9000 high-pass filter on the current and voltage
channels is enabled by default. It can be disabled by writing the
DISPHPF bit in the CONFIG0 register equal to 1.
It is recommended to leave the high-pass filter enabled to
achieve the metering performance listed in the specifications
in the data sheet.
For some applications, it is desirable to increase the high-pass
filter corner, such as to improve performance when a Rogowski
coil current sensor is used.
The high-pass filter corner is selectable using the HPF_CRN bits
in the CONFIG2 register (see Table 6).
Table 6. HPF Corner Gain with 50 Hz Input Signal
HPF_CRN f−3 dB (Hz) HPF_GAIN Settling Time to 1% for DC Step (sec) Settling Time to 0.1% for DC Step (sec)
0 77.4 0.537 0.009 0.013
1 39.3 0.790 0.018 0.027
2 19.8 0.935 0.037 0.055
3 9.9 0.984 0.073 0.110
4 5.0 0.997 0.147 0.221
5 2.5 0.999 0.294 0.442
6 (default) 1.25 1.001 0.589 0.883
7 0.625 1.001 1.179 1.768