Analog Devices EVAL-ADAQ23876FMCZ User manual

User Guide | EVAL-ADAQ23876/EVAL-
ADAQ23878
UG-2023
Evaluating the ADAQ23876/ADAQ23878 16-/18-Bit, 15 MSPS, µModule Data Acquisition Solutions
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | 1 of 29
FEATURES
►Evaluation boards for ADAQ23876 and ADAQ23878, 16-/18-bit,
15 MSPS, µModule data acquisition solutions
►Versatile analog signal conditioning circuitry
►On-board reference, LDO, and power supply circuits
►PC software for control and data analysis of time and frequency
domain
►System demonstration platform-compatible (SDP-H1)
EVALUATION BOARD KIT CONTENTS
►EVAL-ADAQ23876FMCZ or EVAL-ADAQ23878FMCZ evaluation
board
EQUIPMENT NEEDED
►PC running Windows® 10 or higher
►SDP-H1 (EVAL-SDP-CH1Z) controller board
►Low noise, precision signal source (such as the SYS-2700 ser-
ies)
►Standard USB A to USB mini-B
►Band-pass filter suitable for 18-bit testing (value based on signal
frequency)
SOFTWARE NEEDED
►ADAQ23876 or ADAQ23878 ACE plugin
►SDP-H1 driver
GENERAL DESCRIPTION
The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ eval-
uation boards (see Figure 1) enable simplified evaluation of
the ADAQ23876 and ADAQ23878 15 MSPS, 16-/18-bit, high
speed, precision µModule® data acquisition solutions, respectively.
The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ dem-
onstrate the performance of the ADAQ23876 and ADAQ23878
µModules, respectively, and are versatile tools for a variety of
applications.
The ADAQ23876 and ADAQ23878 µModules combine multiple
common signal processing and conditioning blocks into devices
that include a low noise, fully differential analog-to-digital converter
(ADC) driver, a stable reference buffer, high resolution, 16-/18-bit,
15 MSPS successive approximation register (SAR) ADCs, and the
critical passive components necessary for optimum performance.
The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ inter-
face with a high speed system demonstration platform (SDP),
SDP-H1 (EVAL-SDP-CH1Z), via a 160-pin connector, as shown in
Figure 2.
For full details on the ADAQ23876 and ADAQ23878, see the
ADAQ23876 and ADAQ23878 data sheets, which must be con-
sulted in conjunction with this user guide when using the EVAL-
ADAQ23876FMCZ or EVAL-ADAQ23878FMCZ.
EVALUATION BOARD PHOTOGRAPH
Figure 1.
Analog Devices is in the process of updating documentation to provide terminology and language that is culturally appropriate. This is a process
with a wide scope and will be phased in as quickly as possible. Thank you for your patience.

User Guide EVAL-ADAQ23876/EVAL-ADAQ23878
TABLE OF CONTENTS
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Features................................................................ 1
Evaluation Board Kit Contents...............................1
Equipment Needed................................................1
Software Needed...................................................1
General Description...............................................1
Evaluation Board Photograph................................1
Evaluation Board Hardware...................................3
Setting Up the Evaluation Board ....................... 3
SDP-H1 Controller Board...................................3
Power Supplies.................................................. 3
Analog Inputs .................................................... 3
Link Configuration Options.................................4
Evaluation Board Connectors.............................5
Software Installation ............................................. 7
Installing the ACE Software................................7
Software Operation................................................9
Launching the Software......................................9
Exiting the Software..........................................11
Description of Analysis Window ...................... 11
Troubleshooting...................................................17
Connecting the EVAL-ADAQ23876FMCZ or
EVAL-ADAQ23878FMCZ and the SDP-H1
to the PC........................................................ 17
Verifying the Board Connection........................17
Disconnecting the EVAL-ADAQ23876FMCZ
or EVAL-ADAQ23878FMCZ...........................17
Board Layout Guidelines..................................17
Mechanical Stress ...........................................18
Evaluation Board Schematics and Silkscreens... 19
Ordering Information ...........................................27
Notes................................................................... 29
REVISION HISTORY
1/2022—Rev. 0 to Rev. A
Added EVAL-ADAQ23876FMCZ..................................................................................................................... 1
Changes to User Guide Title............................................................................................................................1
Change to Features Section............................................................................................................................ 1
Change to Software Needed Section...............................................................................................................1
Changes to General Description Section.........................................................................................................1
Changes to Figure 2........................................................................................................................................ 3
Changes to Software Installation Section........................................................................................................ 7
Changes to Launching the Software Section...................................................................................................9
12/2021—Revision 0: Initial Version

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EVALUATION BOARD HARDWARE
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Figure 2. Simplified Evaluation Block Diagram
SETTING UP THE EVALUATION BOARD
Figure 2 shows the simplified evaluation board block diagram of the
EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ connected
to the SDP-H1 controller board. The board consists of one µModule
(U1, ADAQ23878 or ADAQ23876), a choice of a 4.096 V reference
(U5, LTC6655) or 2.048V reference (U3, ADR4520), on-board pow-
er supplies to drive the necessary supply rails using the LTM8049
(U6), the ADP7118 (U4), the ADP7183 (U7), the LT3023 (U8), and
an 800 MHz clock distribution IC (U13). The user also has an option
to use the A2 and A3 amplifiers, such as the ADA4899-1, when
evaluating the ADAQ23876 or ADAQ23878.
SDP-H1 CONTROLLER BOARD
The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ use a
serial peripheral interface (SPI) and connect to the high speed
SDP-H1. The SDP-H1 requires power from a 12 V wall adapter.
The SDP-H1 has a Xilinx® Spartan 6 and an ADSP-BF527 process-
or with connectivity to the PC through a USB 2.0 high speed port.
The controller boards allow the configuration and capture of data on
the daughter boards from the PC via a USB.
The SDP-H1 has a field programmable gate array (FPGA) mezza-
nine card (FMC) low pin count (LPC) connector with full differential
low voltage differential signaling (LVDS) and singled-ended low
voltage complementary metal-oxide semiconductor (LVCMOS) sup-
port. The SDP-H1 also features the 160-pin connector, found on
the SDP-B, which exposes the Blackfin® processor peripherals.
This connector provides a configurable serial, parallel I2C and SPI,
and general-purpose input/output (GPIO) communications lines to
the attached daughter board for the functional description of the
on-board power supplies.
POWER SUPPLIES
By default, all necessary supply rails on the EVAL-
ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are powered by
a 3.3 V rail coming from the SDP-H1. The EVAL-ADAQ23876FMCZ
and EVAL-ADAQ23878FMCZ can be powered from an external
3.3 V supply applied using the JP9 solder link if desired (see
Table 2). The positive rails of the EVAL-ADAQ23876FMCZ and
EVAL-ADAQ23878FMCZ, 7 V (+VS), 5 V (VDD), and 2.5 V (VIO),
are generated from a combination of the power µModule, LTM8049
(U6), ADP7118 (U4), and a dual output low dropout (LDO) regula-
tor, LT3023 (U8). The negative rail of the EVAL-ADAQ23876FMCZ
and EVAL-ADAQ23878FMCZ, −2.0 V (−VS), is generated by a
combination of the power µModule, LTM8049 (U6), and ADP7183
(U7). Each supply rail has necessary decoupling capacitors placed
close to the device. A single ground plane is used on the board to
minimize the effect of high frequency noise interference.
Table 1. On-Board Power Supplies
Power Supply (V) Function
+7.5, −2.5 Supply rails using the LTM8049
+7 (default) VS+ rail using the LT3023
−2 (default) VS− rail using the ADP7183
+2.5 VIO rail using the ADP7118
+5 VDD rail using LT3023
ANALOG INPUTS
The Subminiature Version A (SMA) connectors (VIN+ and VIN−)
on the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are
used to provide analog inputs from a low noise, audio precision
signal source (such as the SYS-2700 or the SYS-x555 series).
There are two options available to feed analog inputs directly to the
ADA4899-1 and ADAQ23876 or ADAQ23878, as shown in Figure

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EVALUATION BOARD HARDWARE
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25. The optional amplifiers, ADA4899-1 (A2, A3), can be set up in a
unity-gain configuration driving the ADAQ23876 or ADAQ23878.
In a default configuration of the EVAL-ADAQ23876FMCZ and
EVAL-ADAQ23878FMCZ, an input signal via VIN+ and VIN can
be fed directly to the ADAQ23876 or ADAQ23878, respectively, by
bypassing A2 and A3.
The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are
factory configured to provide the appropriate input signal type, sin-
gle-ended or fully differential, and different gain/attenuation or input
range scaling. Table 2 lists the necessary jumper positions and link
options for different configurations. The default board configuration
presents a 4.096 V on the REFBUF pin and a buffered 2.048
V (midscale) of the fully differential ADC driver amplifier (FDA)'s
VCMO pin of the ADAQ23876 and ADAQ23878.
To evaluate dynamic performance, a fast Fourier transform (FFT),
integral nonlinearity (INL), differential nonlinearity (DNL), or time
domain (waveform or histogram) test can be performed by applying
a very low distortion ac source. For low input frequency testing
below 100 kHz, it is recommended to use a low noise, audio
precision signal source (such as the SYS-2700 series) with the
outputs set to balanced floating. A different precision signal source
can be used alternatively with additional band-pass filtering. The
filter bandwidth depends on input bandwidth of interest.
LINK CONFIGURATION OPTIONS
Multiple link options must be set correctly for the appropriate
operating setup before applying the power and signal to the EVAL-
ADAQ23876FMCZ or EVAL-ADAQ23878FMCZ. Table 2 shows the
default positions of the links for the EVAL-ADAQ23876FMCZ and
EVAL-ADAQ23878FMCZ.
Table 2. Link Options for the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ
Link Default Function Comment
JP3 Center to B FPGA CNV+ Change center to A when using ADC_PLL_CNV+.
JP4 Center to B FPGA CNV- Change center to A when using ADC_PLL_CNV−.
JP5 Center to A AMP+ Change center to B when using an external supply.
JP6 Center to A AMP− Change center to B when an using external supply. If configured to the single-
supply VS− to GND, remove both jumpers (JP6) and install R49 (0 Ω).
JP9 Center to A 3.3 V Change center to B when using an external 3.3 V supply.
P1 Tie Pin 2 and Pin 3
(connected to GND)
Two-lane digital output modes Digital input that enables two-lane output mode. Use this jumper to select either
single lane or two-lane data output mode. The default setting is Pin 2 and Pin 3.
The Pin 2 and Pin 3 setting clocks out all data on the DA± pin. The Pin 1 and Pin 2
setting clocks out data alternately on the DA± and DB± pins.
P2 No connect ADCIN− Negative input of an internal ADC. Extra capacitance can be added on this pin to
reduce the RC filter bandwidth. Optional for the ADAQ23876 and ADAQ23878.
P3 No connect ADCIN+ Positive input of an internal ADC. Additional capacitance can be added on this pin
to reduce the RC filter bandwidth. Optional for the ADAQ23876 and ADAQ23878.
P4 Tie Pin 1 and Pin 2 PDB_AMP Active low. Connect this pin to GND to power down the fully differential ADC driver.
Otherwise, connect it to VS+.
P5 Not applicable SDP-H1 FMC connector The EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ interface to the SDP-
H1 via a 160-pin connector.
P6 Tie Pin 1 and Pin 2 PDB_ADC Digital input that enables the power-down mode. When PDB_ADC is low, an
internal ADC core enters power-down mode, and all circuitry (including the LVDS
interface) shuts down. When PDB_ADC is high, the device operates normally.
Logic levels are determined by VIO.
P7 0 Ω installed −VS for the ADA4899-1 (A2, A3) Remove 0 Ω to use the external supply for the ADA4899-1 (A2, A3).
P8 0 Ω installed +VS for the ADA4899-1 (A2, A3) Remove 0 Ω to use the external supply for the ADA4899-1 (A2, A3).
P9 Tie Pin 1 and Pin 2, tie
Pin 5 and Pin 6
INx− Gain pin select. Refer to Table 3 for the different gain configurations.
P10 Tie Pin 1 and Pin 2, tie
Pin 5 and Pin 6
INx+ Gain pin select. Refer to Table 3 for the different gain configurations.

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EVALUATION BOARD HARDWARE
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EVALUATION BOARD CONNECTORS
The functional descriptions for all the connectors (including a
160-pin FMC connector used to interface with the SDP-H1) used
on the EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ are
listed in Table 4 and Table 5). There are several test points and
single in line (SIL) headers on the EVAL-ADAQ23876FMCZ and
EVAL-ADAQ23878FMCZ. These test points provide easy access
to on-board signals for troubleshooting and evaluation purposes.
Table 3 details the different gain positions for the links of the
EVAL-ADAQ23876FMCZ and EVAL-ADAQ23878FMCZ.
Figure 3. Gain = 0.37
Figure 4. Gain = 0.73
Figure 5. Gain = 0.87
Figure 6. Gain = 1.38
Figure 7. Gain = 2.25
Table 3. Gain Input Configuration
Gain Input Range (V) Input Signal on Pins Test Conditions
0.37 ±10 IN2+ IN2− Connect the OUT+, IN1−, OUT−, and IN1+ pins together (see Figure 3)
0.73 ±5 IN1+, IN1− Connect the OUT+, IN2−, OUT−, and IN2+ pins together (see Figure 4)
0.87 ±4.096 IN2+, IN2− Leave the IN1+ and IN1− pins floating (see Figure 5)
1.38 ±2.5 IN1+, IN1− Leave the IN2+ and IN2− pins floating (see Figure 6)
2.25 ±1.5 IN2+/IN1+, IN2−/IN1− Connect the IN2−, IN1−, IN2+, and IN1+ pins together (see Figure 7)
Table 4. On-Board Connectors
Connector Function
J1 CLKIN input
J2 EXT_CNV−
J3 External CLK input
J4 EXT_CNV+
VIN+ Analog input V+
VIN− Analog input V−
+3P3V External power supply
P5 SDP-H1 FMC connector

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EVALUATION BOARD HARDWARE
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Table 5. 160-Pin FMC Connector (P5) Details
Signals Function
OSC_CLK+ 100 MHz low jitter positive line of differential pair for carrying clock signals from the daughter board.
OSC_CLK− 100 MHz low jitter negative line of differential pair for carrying clock signals from the daughter board.
CLK± µModule CLK input signals connected to FPGA Bank 2.1, 2
CLK− µModule CLK input signals connected to FPGA Bank 2.1, 2
DCO+ Positive line of differential pair for carrying clock signals from the daughter board.
DCO− Negative line of differential pair for carrying clock signals from the daughter board.
FPGA_CNV+ User defined signals connected to FPGA Bank 2.1, 2
FPGA_CNV− User defined signals connected to FPGA Bank 2.1, 2
DA± User defined signals connected to FPGA Bank 2.1
DB± User defined signals connected to FPGA Bank 2.1
+3P3V_FMC 3.3 V (3 A) power supply to the daughter board.
SCL I2C clock line for reading FMC electronically erasable programmable read-only memory (EEPROM).
SDA I2C data line for reading FMC EEPROM.
GA0 I2C Geographical Address 0. Must be connected to Address Pin A1 of the FMC EEPROM.
GA1 I2C Geographical Address 1. Must be connected to Address Pin A0 of the FMC EEPROM.
3P3VAUX 3.3 V (20 mA) power supply for powering only the FMC EEPROM.
PG_C2M Active high signal indicating that the 12P0V, 3P3V, and VADJ power supplies are turned on.
CNV_EN User defined signals connected to FPGA Bank 2.1
1User defined signals with a P suffix can be used as the positive pin of the differential pair. User defined signals with an N suffix can be used as the negative pin of the
differential pair. For further information, see the VITA 57 specification.
2User defined signals with a CC suffix are the preferred signal lines on which to transmit clock signals from the controller board to the daughter board. These signal lines are
connected to global clock lines on the FPGA, but they can also be used to carry any other user defined signal. For further information, see the VITA 57 specification.

User Guide EVAL-ADAQ23876/EVAL-ADAQ23878
SOFTWARE INSTALLATION
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Before using the EVAL-ADAQ23876FMCZ or EVAL-
ADAQ23878FMCZ, download and install the Analysis, Control,
Evaluation (ACE) software from the ACE software page. Down-
load the ADAQ23876 or ADAQ23878 ACE plugin from the EVAL-
ADAQ23876FMCZ or EVAL-ADAQ23878FMCZ product page, re-
spectively, or from the plugin manager in ACE.
ACE is a desktop software application allowing the evaluation and
control of multiple evaluation systems across the Analog Devices,
Inc., product portfolio. The installation process consists of the ACE
software installation and the SDP-H1 driver installation.
To ensure that the evaluation system is properly recognized when
it is connected to the PC, install the ACE software and the
SDP-H1 driver before connecting the EVAL-ADAQ23876FMCZ or
EVAL-ADAQ23878FMCZ and the SDP-H1 to the USB port of the
PC.
INSTALLING THE ACE SOFTWARE
To install the ACE software, take the following steps:
1. Download the ACE software to a Windows-based PC.
2. Double click the ACEInstall.exe file to begin the installation.
By default, the software is saved to the following location:
C:\Program Files (x86)\Analog Devices\ACE.
3. A dialog box opens asking for permission to allow the program
to make changes to the PC. Click Yes to begin the installation
process.
4. In the ACE Setup window, click Next > to continue the installa-
tion, as shown in Figure 8.
Figure 8. Evaluation Software Install Confirmation
5. Read the software license agreement and click I Agree (see
Figure 9).
Figure 9. License Agreement
6. Click Browse... to choose the installation location and then click
Next (see Figure 10).
Figure 10. Choose Installation Location
7. Select the PreRequisites checkbox to include the installation of
the SDP-H1 driver. Click Install (see Figure 11).

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SOFTWARE INSTALLATION
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Figure 11. Choose Components
8. The Windows Security window opens (see Figure 12). Click
Install. The installation is in progress. No action is required
(see Figure 13).
Figure 12. Windows Security Window
Figure 13. Installation in Progress
9. When the installation is complete, click Next > (see Figure 14),
and then click Finish to complete the installation process.
Figure 14. Installation Complete

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SOFTWARE OPERATION
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LAUNCHING THE SOFTWARE
When the EVAL-ADAQ23876FMCZ or EVAL-ADAQ23878FMCZ
and SDP-H1 are properly connected to the PC, launch the ACE
software by taking the following steps:
1. From the Start menu, select All Programs > Analog Devices
> ACE > ACE.exe to open the ACE software main shown
in Figure 15. The ADAQ23876 Board or ADAQ23878 Board
icon appears in the Attached Hardware section, depending
on which evaluation board is connected. Note that Figure
15 through Figure 23 show the ACE software with the EVAL-
ADAQ23878FMCZ connected.
2. If the EVAL-ADAQ23876FMCZ or EVAL-ADAQ23878FMCZ
is not connected to the USB port via the SDP-H1 when
the software is launched, the ADAQ23876 Board or
ADAQ23878 Board icon does not appear in the Attached
Hardware section. Connect the EVAL-ADAQ23876FMCZ or
EVAL-ADAQ23878FMCZ and SDP-H1 to the USB port of the
PC and wait a few seconds, then continue following these
instructions.
3. Double click the ADAQ23876 Board or ADAQ23878 Board
icon to open the board view window.
4. Double click the ADAQ23876 or ADAQ23878 chip icon in the
board view window to open the chip view window shown in
Figure 16.
5. Click Software Defaults and then click Apply Changes to
apply the default settings to the ADAQ23876 or ADAQ23878.
6. Click Proceed to Analysis in the chip view window to open the
analysis view window shown in Figure 17.
Figure 15. ACE Software Main Window

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SOFTWARE OPERATION
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Figure 16. Chip View
Figure 17. Analysis View