Analog Devices EVAL-ADFS5758SDZ User manual

EVAL-ADFS5758SDZ User Guide
UG-1688
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Evaluating the ADFS5758 Single-Channel, 16-Bit Current/Voltage Output DAC,
Functional Safety Approved for Unipolar Current Output
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 20
FEATURES
Full featured evaluation board for the ADFS5758
On-board 2.5 V ADR4525 reference
On-board ADP1031-1 isolated PMU with integrated SPI
signal isolation channels
ACE software for control
EVALUATION KIT CONTENTS
EVAL-ADFS5758SDZ evaluation board
EQUIPMENT NEEDED
EVAL-SDP-CS1Z board
Bench top power supply and connector cables
DOCUMENTS NEEDED
ADFS5758 data sheet
ACE User Manual
SOFTWARE NEEDED
ACE software for control
GENERAL DESCRIPTION
This user guide describes the evaluation board for the ADFS5758.
The ADFS5758 is a functional safety approved, single-channel,
voltage and current output, digital-to-analog converter (DAC)
with on-chip dynamic power control (DPC) to minimize package
power dissipation.
For full details, refer to the ADFS5758 data sheet. Consult the
data sheet when using the EVAL-ADFS5758SDZ. The
configuration of the various link options is explained in the
Evaluation Board Hardware section. The installation of the
companion software is described in the Installing the ACE
Software and ADFS5758 Plugins section.
The EVAL-ADFS5758SDZ, as shown in Figure 1, requires the
EVAL-SDP-CS1Z board. The EVAL-ADFS5758SDZ interfaces
to the USB port of the PC via the EVAL-SDP-CS1Z board. The
analysis, control, evaluation (ACE) software allows simplified
programming of the ADFS5758, and is available with the
EVAL-ADFS5758SDZ evaluation board.
EVAL-ADFS5758SDZ EVALUATION BOARD PHOTOGRAPH
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Figure 1.

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TABLE OF CONTENTS
Features .............................................................................................. 1
Evaluation Kit Contents................................................................... 1
Equipment Needed........................................................................... 1
Documents Needed.......................................................................... 1
Software Needed ............................................................................... 1
General Description......................................................................... 1
EVAL-ADFS5758SDZ Evaluation Board Photograph................. 1
Revision History ............................................................................... 2
Evaluation Board Hardware............................................................ 3
Power Supplies .............................................................................. 3
Serial Communication................................................................. 3
ADFS5758 Reference ................................................................... 3
ADFS5758 Address Pins.............................................................. 3
ADP1031-1 Power Good............................................................. 3
Software Quick Start Procedures.................................................... 5
Installing the ACE Software and ADFS5758 Plugins .............. 5
Initial Setup ....................................................................................5
ADFS5758 Block Diagram and Functions.....................................7
Initial Configuration.....................................................................9
DC-to-DC Converter Settings.....................................................9
Setting the DAC Output............................................................ 10
Writing to the ADC Configuration Register .......................... 10
Updating Diagnostic Results .................................................... 10
Example Configuration Sequences.......................................... 11
ACE Tool Views.............................................................................. 12
Macro Tool .................................................................................. 12
Register Debugger Tool ............................................................. 12
Events Tool .................................................................................. 12
Evaluation Board Schematics and Artwork................................ 13
Ordering Information.................................................................... 18
Bill of Materials........................................................................... 18
REVISION HISTORY
6/2020—Revision 0: Initial Version

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EVALUATION BOARD HARDWARE
POWER SUPPLIES
The EVAL-ADFS5758SDZ evaluation board contains the
ADP1031-1 power management unit (PMU), which generates
three of four power supply inputs required by the ADFS5758:
AVDD1 (+26.7 V), AVDD2 (+5.15 V), and AVSS (−15.4 V) device.
VLOGIC is the fourth power supply required by the ADFS5758.
The JP11 link provides the 3.3 V supply to the VLOGIC input via
the VLDO output of the ADFS5758. The AVDD2 input can be
connected to the AVDD1 input via the JP12 link if the VOUT2
supply from the ADP1031-1 is not in use. See Table 1 for link
options and the default link positions.
The EVAL-ADFS5758SDZ evaluation board operates with a
power supply range from −33 V on AVSS to +33 V on AVDD1,
with a maximum voltage of 60 V between the two rails. AVDD2
requires a voltage between 5 V and 33 V. The VDPC+ pin of the
ADFS5758 can be driven by AVDD1 via the JP6 link. The JP6 link
bypasses the dc-to-dc circuitry.
SERIAL COMMUNICATION
The SDP-S system demonstration platform handles commu-
nication to the EVAL-ADFS5758SDZ via the PC. By default, the
SDP-S board handles the serial port interface (SPI) commu-
nication, controls the RESET and LDAC pins, and monitors the
FAULT pin of the ADFS5758.
The EVAL-ADFS5758SDZ evaluation board can disconnect
from the SDP-S board and drive the digital signals from an
external source by removing the appropriate links on the P10
link. The option to tie the RESET and LDAC pins to high or low
levels can be accessed through the S2 switch and JP4 link.
ADFS5758 REFERENCE
The ADFS5758 can use its internal reference or an external
reference. The external reference on board is the ADR4525 and
is powered by either the AVDD2 generated from ADP1031-1 or
the VLDO generated by the ADFS5758. JP5 selects which voltage
reference is to be used by the ADFS5758.
ADFS5758 ADDRESS PINS
The ADFS5758 address pins (AD0 and AD1) are used in
conjunction with the ADFS5758 address bits within the SPI
frame to determine which ADFS5758 device is being addressed
by the system controller. AD0 and AD1 can be configured
through JP7 and JP8.
ADP1031-1 POWER GOOD
PWRGD is an active high signal that indicates when the
ADP1031-1 outputs have reached the desired output voltage.
The DS1 light emitting diode (LED) lights up when the power-
good signal is low, indicating an error on the ADP1031-1
voltage outputs.
Table 1. EVAL-ADFS5758SDZ Link Option Functions
Link Default Link Position Function
JP1 B Position A connects the AVSS pin to ground for the unipolar supply option (current output only).
Position B selects the VOUT3 voltage of the ADP1031-1.
JP2 Inserted Connects the VLOGIC pin of the ADFS5758 to the SVDD1 pin of the ADP1031-1.
JP3 A Position A selects the 3.3 V output from the SDP-S to the MVDD pin of the ADP1031-1.
Position B selects the 3.3 V input via the EXT+3.3V_ header to the MVDD pin of the ADP1031-1.
JP4 A Position A connects the LDAC pin to GND. Position B connects the LDAC pin to the VLOGIC pin.
JP5 A Position A selects VOUT2 of the ADP1031-1 as the input voltage to the ADR4525.
Position B selects the VLDO pin as the input voltage to the ADR4525.
JP6 Not inserted Shorts the VDPC+ pin to the AVDD1 pin, bypassing the positive dc-to-dc circuitry.
JP7 A Position A connects the AD0 pin to ground. Position B connects the AD0 pin to the VLOGIC pin.
JP8 A Position A connects the AD1 pin to ground. Position B connects the AD1 pin to the VLOGIC pin.
JP9 Not inserted Connects the return signal to ground.
JP10 B Position A selects the REFOUT pin of the ADFS5758 as the input to the REFIN pin of the ADFS5758.
Position B selects the ADR4525 output as the input to the REFIN pin.
JP11 Inserted Connects the 3.3 V output of the VLDO pin to the VLOGIC pin.
JP12 A Position A selects VOUT2 of the ADP1031-1 as the input voltage to the AVDD2 pin.
Position B selects the AVDD1 pin as the input voltage to the AVDD2 pin.
JP13 Inserted Connects VOUT1 of the ADP1031-1 to the AVDD1 pin.
P10 Inserted Provides options to disconnect from the SDP-S board and to drive digital signals from an external source.
See Table 2 for the specific link options.
S2 Left In the left position, this link connects the RESET pin to the VLOGIC pin.
Middle (default) In the middle position (default), this link controls the RESET pin via the SDP-S board.
Right In the right position, this link connects the RESET pin to ground.

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Table 2. Link Options for the P2_ Header (All Links are Inserted by Default)
Pin No. Position Function
1, 2 Inserted Connects the FAULT signal from the SDP-S to the MGPO3 pin on the ADP1031-1.
Not inserted
Disconnects the FAULT signal from the SDP-S to the MGPO3 pin on the ADP1031-1.
3, 4 Inserted Connects the RESET signal from the SDP-S to the MGPI2 pin on the ADP1031-1.
Not inserted
Disconnects the RESET signal from the SDP-S to the MGPI2 pin on the ADP1031-1.
5, 6 Inserted Connects the LDAC signal from the SDP-S to the MGPI1 pin on the ADP1031-1.
Not inserted
Disconnects the LDAC signal from the SDP-S to the MGPI1 pin on the ADP1031-1.
7, 8 Inserted Connects the SCLK signal from the SDP-S to the MCK pin on the ADP1031-1.
Not inserted Disconnects the SCLK signal from the SDP-S to the MCK pin on the ADP1031-1.
9, 10 Inserted Connects the SDO signal from the SDP-S to the MI pin on the ADP1031-1.
Not inserted Disconnects the SDO signal from the SDP-S to the MI pin on the ADP1031-1.
11, 12 Inserted Connects the SDI signal from the SDP-S to the MO pin on the ADP1031-1.
Not inserted Disconnects the SDI signal from the SDP-S to the MO pin on the ADP1031-1.
13, 14 Inserted Connects the SYNC signal from the SDP-S to the MSS pin on the ADP1031-1.
Not inserted
Disconnects the SYNC signal from the SDP-S to the MSS pin on the ADP1031-1.
15, 16 Inserted Connects the PWRGD signal from the SDP-S to the PWRGD pin on the ADP1031-1.
Not inserted Disconnects the PWRGD signal from the SDP-S to the PWRGD pin on the ADP1031-1.

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SOFTWARE QUICK START PROCEDURES
INSTALLING THE ACE SOFTWARE AND ADFS5758
PLUGINS
The EVAL-ADFS5758SDZ software uses the Analog Devices, Inc.,
ACE software. For instructions on the use of the ACE software,
see the www.analog.com/ACE product page.
When the installation completes, the EVAL-ADFS5758SDZ
evaluation board plugin window appears when the ACE
software opens (see Figure 2).
22209-002
Figure 2. EVAL-ADFS5758SDZ Evaluation Board Plugin Window After
Opening the ACE Software
INITIAL SETUP
To set up the EVAL-ADFS5758SDZ, take the following steps:
1. Connect a USB cable to the PC and then to the SDP-S
board.
2. Connect the SDP-S board to the EVAL-ADFS5758SDZ.
The PC recognizes the EVAL-ADFS5758SDZ.
3. Power up the EVAL-ADFS5758SDZ with the relevant
power supplies.
4. If not opened already, open the ACE software. The
EVAL-ADFS5758SDZ appears in the Attached Hardware
pane.
22209-003
Figure 3. EVAL-ADFS5758SDZ Plugin Not Installed
5. When setting up the evaluation board for the first time, the
EVAL-ADFS5758SDZ plugin may need to be installed. If
the plugin appears as shown in Figure 6, go to Step 7. If the
plugin appears as shown in Figure 3, click the button that is
marked in red in Figure 3. After clicking this button, the
popup window shown in Figure 4 appears. Click Yes.
22209-004
Figure 4. Installing Plugin Popup Window
6. A new window appears, as shown in Figure 5. Navigate to
the Board.ADFS5758 plugin and click Install Selected. The
EVAL-ADFS5758SDZ plugin installs and displays, as
shown in Figure 6.
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Figure 5. Manage Plug-ins Window
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Figure 6. Attached Hardware Pane with EVAL-ADFS5758SDZ Connection

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7. Double-click EVAL-ADFS5758SDZ to open the ADFS5758
block diagram. The INITIAL CONFIGURATION pane
appears on the left side of the window. Several register
settings can be configured in this pane and are written to the
device in the appropriate order. The DIG_DIAG_STATUS,
RESET_OCCURRED, and CAL_MEM_UNREFRESHED
LED indicators in the window illuminate red by default.
Writing the initial configuration values clears these error
flags. If the device is power cycled, or if the USB cable is
disconnected and reconnected while the ACE software is
open, contact with the EVAL-ADFS5758SDZ can be lost. If
contact is lost, click the System tab, click the USB symbol
on the SDP-S Controller, and then click Acquire to
communicate with the EVAL-ADFS5758SDZ.
22209-007
Figure 7. ADFS5758 Block Diagram in the ACE Software

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ADFS5758 BLOCK DIAGRAM AND FUNCTIONS
The ADFS5758 ACE block diagram, as shown in Figure 8,
appears similar to the block diagram shown in the ADFS5758
data sheet for simplified correlation of the functions on the
EVAL-ADFS5758SDZ evaluation board with the descriptions
given in the ADFS5758 data sheet.
A full description of each block and register setting is available
in the ADFS5758 data sheet. The full window ADFS5758 block
diagram, with labels, is shown in Figure 8. Table 3 describes the
functionality of each block.
22209-008
Figure 8. ADFS5758 ACE Block Diagram with Labels
Table 3. ADFS5758 Block Diagram Label Functions (See Figure 8)
Label Function Description
A To apply any changes made to the block diagram or to register values in the memory map to the device, click Apply Changes.
B To read back all of the registers of the device, click Read All.
C Click Reset Chip to reset the ADFS5758. The Reset Chip button has the same functionality as the software reset of the ADFS5758.
D Click Diff to show the registers that are different from the data stored on the device. This function shows what has changed since
the last time the registers were read.
E Click Software Defaults to load the software defaults of the device. These values are not written to the hardware. Click Apply
Changes (Label A in Figure 8) to write the software default values to the hardware.
F Click to view the memory map side by side with the block diagram.
G The AD0 and AD1 check boxes set the device under test (DUT) address of the device and must correspond to the JP12 and JP14
links on the hardware. A selected box represents a high state. A cleared box represents a low state.
H If the /RESET box is selected, the SDP-S sets the RESET pin high. Otherwise, the SDP-S pulls RESET low.
I If the /LDAC box is selected, the SDP-S sets the LDAC pin high. Otherwise, the SDP-S pulls LDAC low.
J The ACE plugin monitors the FAULT pin. If the FAULT pin is low, the /FAULT indicator LED illuminates red.
K The VI_OUT field displays the calculated output at the VIOUT pin and displays if the output is in volts, milliamperes, or is high
impedance (high-Z).
L1 to
L15
The graphical user interface (GUI) access for several registers. Popup menus, dropdown menus, and hexadecimal text fields are
available in the GUI to configure several registers of the ADFS5758. To write the changes to the device, click Apply Changes (Label
A). The functions within the GUI that control various registers (Label L1 through Label L15 in Figure 8) are described in Table 4.
M The Calibration Memory Refresh button initiates a write to the key register to perform a calibration memory refresh.
N The SW LDAC button initiates a write to the key register to perform a software LDAC command.
O The NOP Command button initiates a write to Address 0x00 for a no operation (NOP) command.
P The Configure ADC button writes the data selected in the ADC Config pane (Label L15) to the ADC configuration register.

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Label Function Description
Q The Two Stage Readback Select pane initiates two-stage readback through the two-stage readback select register. Click
Readback to initiate a write to the two-stage readback select register and issue a NOP command.
R In the DIGITAL DIAGNOSTIC RESULTS pane, click Update and Readback Digital Diagnostic Result button to trigger a write 1 to
clear operation and initiate a readback from the digital diagnostic results register.
S In the ANALOG DIAGNOSTIC RESULTS pane, click Update and Readback Analog Diagnostic Result button to trigger a write 1
to clear operation and initiate a readback from the analog diagnostic results register.
T If the HART_EN box is checked, the HART_EN bit = 1 in the General-Purpose Configuration 1 register.
U Click Proceed to Memory Map to open the ADFS5758 memory map (see Figure 9).
V Click Example Sequences to open the example sequences window (see Figure 15).
Table 4. Register Controls Accessible via the GUI (See Label L1 to L15 in Table 3 and in Figure 8)
Label Function Description
L1 The Diagnostic Configuration button opens the associated popup menu.
L2 When the GP Config button clicked, a popup menu appears.
L3 When the Key register menu is clicked, a dropdown list appears.
L4 When the Fault Pin Config button is clicked, a popup menu appears.
L5 When the WDT Config button is clicked, a popup menu appears.
L6 The Frequency Monitor text field displays the value in the frequency monitor when read.
L7 The Clear Code text field inserts a clear code value in hexadecimal format.
L8 The User Gain text field inserts a user gain value in hexadecimal format.
L9 The User Offset text field inserts a user offset value in hexadecimal format.
L10 The DAC Input Reg text field inserts the DAC value in hexadecimal format.
L11 The 16 Bit DAC block opens a popup menu when clicked.
L12 The DAC Output Reg control displays the hexadecimal value currently set in the DAC output register.
L13 The DC-DC Converter block opens the dc-to-dc configuration popup menu.
L14 The Status Register pane displays the contents of the status register including any ADC conversion result.
L15 The ADC Config pane contains a combination of dropdown menus and a text field to enter the ADC input data.

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22209-009
Figure 9. ADFS5758 Memory Map in the ACE Software
INITIAL CONFIGURATION
An initial configuration wizard is available when opening the
ADFS5758 plugin. The initial configuration wizard allows quick
configuration of the ADFS5758 and provides configuration of
the clock output in the general-purpose configuration register,
the dc-to-dc settings, the DAC configuration, and the DAC
input register. Clicking the Apply Changes button initiates the
configured settings in the order of the recommended power-up
sequence described in the ADFS5758 data sheet.
DC-TO-DC CONVERTER SETTINGS
If the VDPC+ pin is not tied directly to AVDD1, enable the dc-to-dc
converter for proper operation. This step must be completed
before configuring the DAC output. The DC-DC Configuration
popup menu, as shown in Figure 10, contains the dc-to-dc
settings required to configure the ADFS5758 output properly.
After the desired settings are selected, click the Close button
and then click Apply Changes.
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Figure 10. DC-DC Configuration Popup Menu

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SETTING THE DAC OUTPUT
To configure the DAC output, use the DAC Config Register
popup menu (see Figure 11). Click the 16 Bit DAC block in the
block diagram to display the DAC configuration register. Select
the appropriate settings, and then click Apply Changes. It is
recommended to disable the output until the correct value in
the DAC input register is written to the device.
To change the DAC voltage or current output level, write the
appropriate hexadecimal code to the DAC input register, and
then click Apply Changes. Click SW LDAC to issue a software
LDAC command, or pull the LDAC pin low to update the DAC
output register with the values in the DAC input register. Enable
the DAC output by checking the OUT_EN (Enable VI_OUT)
checkbox, and then click Apply Changes. The programmed
voltage or current is then reflected at the VIOUT pin.
22209-011
Figure 11. ADFS5758 DAC Config Register Popup Menu
WRITING TO THE ADC CONFIGURATION REGISTER
The procedure to set up and configure the ADC input node is
discussed in the ADFS5758 data sheet. For this reason, writing
to the ADC configuration register through the Apply Changes
function is disabled.
The dropdown list in the SEQUENCE_COMMAND pane
contains the list of available commands. The hexadecimal text
field in the SEQUENCE_DATA section is used in conjuction with
the SEQUENCE_COMMAND bits. The dropdown list in the
ADC IP SELECT section is used to select the desired input node
for the ADC to convert. Click Configure ADC to initiate a write
to the ADC configuration register. A register read must be
performed to see the ADC result in the status register.
22209-012
Figure 12. ADFS5758 ADC Configuration Register
UPDATING DIAGNOSTIC RESULTS
The ADFS5758 has a digital diagnostic results register and an
analog diagnostic results register, which contain error flags for
the on-chip digital and analog diagnostic features. Writing 1 to
the respective error flags updates the error flag status.
To update the digital and analog diagnostic results registers,
click Update and Readback Digital Diagnostic Result for digital
diagnostic results registers or Update and Readback Analog
Diagnostic Result for analog diagnostic results registers. These
buttons initiate the writing of a 1 to the selected error flag and
then read back the updated diagnostic result.
Figure 13 shows the digital diagnostic results register. Figure 14
shows the analog diagnostic results register.
22209-014
Figure 13. ADFS5758 DIGITAL DIAGNOSTIC RESULTS Register
22209-013
Figure 14. ADFS5758 ANALOG DIAGNOSTIC RESULTS Register