Analog Devices UG-284 User manual

Evaluation Board User Guide
UG-284
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
ADAU1373 Evaluation Board User Guide
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 24
PACKAGE CONTENTS
ADAU1373 evaluation board
5 V ac-to-dc power adapter
Evaluation board user guide
DOCUMENTS NEEDED
ADAU1373 data sheet
AN-1006 Application Note, Using the EVAL-ADUSB2EBZ
GENERAL DESCRIPTION
The ADAU1373 is a low power audio codec that supports stereo
record and playback. It provides eight single-ended or four
differential analog inputs with PGA for adjusting the gain. The
support for two stereo digital microphone inputs is provided so
that, in total, four digital microphones can be connected. In
addition, three serial digital audio in/out ports are provided
with ASRCs to support various sampling rates at the
input/output ports, allowing flexible system design.
The analog output side consists of line outputs, a headphone
output, a speaker output, and a receiver output. The two stereo
single-ended line level outputs are included, which can be
configured as two differential outputs. The headphone output is
stereo true-ground-centered with efficient Class-G architecture.
The efficient stereo filterless Class-D switching amplifier pro-
vides around 1 W stereo power for speakers. The differential
receiver amplifier can be used to connect the separate receiver
speaker.
The ADAU1373 evaluation board includes the complete
application circuit for the ADAU1373. The board is featured
with USBi connection to the SigmaStudio™ graphical develop-
ment tool running on a host PC, which is used to program the
ADAU1373.
Included in this user guide is a detailed description for the
ADAU1373 evaluation board. It is recommended that the
ADAU1373 data sheet be read along with this user guide. Full
details about the part are available in the ADAU1373 data sheet,
which provides more detailed information about the specifica-
tions, internal block diagrams, and application guidance for the
codec IC.

UG-284 Evaluation Board User Guide
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Package Contents.............................................................................. 1
Documents Needed.......................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Setting Up the Board—Quick Start................................................ 3
SigmaStudio Software Installation ............................................. 3
Hardware Setup, USBi.................................................................. 3
Powering the Board...................................................................... 3
Setting Up the Registers in SigmaStudio................................... 3
Evaluation Board Hardware.............................................................5
Power Supplies...............................................................................5
Digital Audio Interface and Digital Microphone Interface .....7
Analog Input and Output.............................................................9
Clock and Control Port ............................................................. 10
Evaluation Board Schematics and Artwork................................ 11
Ordering Information.................................................................... 20
Bill of Materials........................................................................... 20
Related Links................................................................................... 21
REVISION HISTORY
6/11—Revision 0: Initial Version

Evaluation Board User Guide UG-284
Rev. 0 | Page 3 of 24
SETTING UP THE BOARD—QUICK START
SigmaStudio SOFTWARE INSTALLATION
To install the SigmaStudio software, follow these steps:
1. Open the provided .zip file and extract the files to your PC.
Alternatively, insert the SigmaStudio CD into the PC
optical drive and locate the SigmaStudio folder on the CD.
2. If Microsoft .NET Framework Version 3.5 is not already
installed on the PC, install it by double-clicking
dotnetfx.exe.
3. Install SigmaStudio by double-clicking setup.exe and
following the prompts. A computer restart is not required.
HARDWARE SETUP, USBi
To set up the USBi hardware, follow these steps:
1. Plug the USBi ribbon cable into Header J23.
2. Connect the USB cable to your computer and to the USBi.
3. When prompted for drivers, follow these steps:
a) Select Install from a list or a specific location.
b) Select Search for the best driver in these locations.
c) Select the box for Include this location in the search.
The USBi driver is located in C:\Program Files\Analog
Devices Inc\Sigma Studio\USB drivers.
d) Click Next.
e) If prompted to choose a driver, select CyUSB.sys.
f) If the PC is running Windows® XP and you receive the
message that the software has not passed Windows
logo testing, click Continue Anyway.
POWERING THE BOARD
1. Plug the external dc power adapter into J34 to input 5 V dc
power to the board.
2. Short Jumpers J40, J33, J31, and J32 to select the on-board
LDO-generated voltages that are connected to SPKVDD,
HPVDD, AVDD, and DVDD, respectively.
3. Set Jumpers J43, J36, J39, J37, and J38 to select the required
voltage (1.8 V, 2.4 V, or 3.3 V) connected to each IOVDDx
(x = 1 to 5).
SETTING UP THE REGISTERS IN SigmaStudio
The codec is configured with SigmaStudio software. To set up
the registers in SigmaStudio, follow these steps:
1. Create a new project. Select New Project under the File
menu. The Hardware Configuration tab opens.
2. Click and drag an ADAU1373 cell and a USBi cell into the
blank work area.
3. Connect the USBi cell to the ADAU1373 cell by clicking
and dragging from the top blue output pin of the USBi cell
to the green input pin of the ADAU1373 cell. The window
should now resemble Figure 1.
4. In the IC 1 - ADAU1373_REVB_V1.13 tab, configure the
ADAU1373 registers by clicking the intuitive graphic user
interface (GUI) elements in the Input A to Input D,
Analog Input Signal Routing, and Mic Bias Control
sections to set up the proper datapath (see Figure 2).
The SigmaStudio software includes help information. Press the
F1 key to open the help window.
09899-001
Figure 1. Hardware Configuration Tab—USBi Connection

UG-284 Evaluation Board User Guide
Rev. 0 | Page 4 of 24
09899-002
Figure 2. Hardware Configuration Tab—Register Setup

Evaluation Board User Guide UG-284
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EVALUATION BOARD HARDWARE
POWER SUPPLIES
5V DC INPUT
IOVDD2
FOR
DAI B
IOVDD5
FOR
I
2
C/SPI
IOVDD1
FOR
DAI A
IOVDD4
FOR
DMIC
IOVDD3
FOR
DAI C
SPKVDD
HPVDD AVDD
DVDD
09899-003
Figure 3. Power Supply
The evaluation board requires an external 5 V dc power adapter
plugged into J34. This 5 V dc input drives the on-board LDOs
to generate 1.5 V, 1.8 V, 2.4 V, 3.3 V, or 3.6 V, which feeds into
the ADAU1373 and other on-board circuits. The power
supplies the ADAU1373 requires are listed in Table 1.
Table 1. ADAU1373 Power Supplies
Power Supply LDO Voltage
AVDD 1.8 V
HPVDD 1.8 V
SPKVDD 3.6 V
DVDD 1.5 V
IOVDD1 to IOVDD5 1.8 V, 2.4 V, or 3.3 V
If voltages other than the default LDO output are needed, external
power supplies can be used for this purpose. Each power supply
for the ADAU1373 has a set of jumpers to select the LDO
output or external power supply.
J31 is for AVDD power supply selection. The selection options
are shown in Table 2.
Table 2. J31
Jumper
Position Function
On On-board LDO-generated 1.8 V connected to AVDD
Off External power supply connected to Test Pin AVDD
and Test Pin GND
J33 is for HPVDD power supply selection. The selection table is
shown in Table 3.
Table 3. J33
Jumper
Position Function
On On-board LDO-generated 1.8 V connected to
HPVDD
Off External power supply connected to Test Pin HPVDD
and Test Pin GND
J32 is for DVDD power supply selection. The selection options
are shown in Table 4.
Table 4. J32
Jumper
Position Function
On On-board LDO-generated 1.5 V connected to DVDD
Off External power supply connected to Test Pin DVDD
and Test Pin GND
J40 is for SPKVDD power supply selection. The selection
options are shown in Table 5.
Table 5. J40
Jumper
Position Function
On On-board LDO-generated 3.6 V connected to
SPKVDD
Off External power supply connected to SPKVDD: J41
for SPKVDD and J42 for GND
J43 is for IOVDD1 power supply selection, which powers
Digital Audio Interface A. The selection options are shown in
Table 6.

UG-284 Evaluation Board User Guide
Rev. 0 | Page 6 of 24
Table 6. J43
Jumper
Position1Function
1-2 On-board LDO-generated 1.8 V connected to
IOVDD1
3-4 On-board LDO-generated 3.3 V connected to
IOVDD1
5-6 On-board LDO-generated 2.4 V connected to
IOVDD1
Off External power supply connected to
Test Pin IOVDD1 and Test Pin GND
1Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J36 is for IOVDD2 power supply selection, which powers digital
Audio Interface B. The selection options are shown in Table 7.
Table 7. J36
Jumper
Position1Function
1-2 On-board LDO-generated 1.8 V connected to
IOVDD2
3-4 On-board LDO-generated 3.3 V connected to
IOVDD2
5-6 On-board LDO-generated 2.4 V connected to
IOVDD2
Off External power supply connected to
Test Pin IOVDD2 and Test Pin GND
1Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J39 is for IOVDD3 power supply selection, which powers digital
Audio Interface C. The selection options are shown in Tabl e 8.
Table 8. J39
Jumper
Position1Function
1-2 On-board LDO-generated 1.8 V connected to
IOVDD3
3-4 On-board LDO-generated 3.3 V connected to
IOVDD3
5-6 On-board LDO-generated 2.4 V connected to
IOVDD3
Off External power supply connected to
Test Pin IOVDD3 and Test Pin GND
1Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J37 is for IOVDD4 power supply selection, which powers the
digital microphone interface. The selection options are shown
in Table 9.
Table 9. J37
Jumper
Position1Function
1-2 On-board LDO-generated 1.8 V connected to
IOVDD4
3-4 On-board LDO-generated 3.3 V connected to
IOVDD4
5-6 On-board LDO-generated 2.4 V connected to
IOVDD4
Off External power supply connected to
Test Pin IOVDD4 and Test Pin GND
1Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.
J38 is for IOVDD5 power supply selection, which powers the
I2C/SPI port. The selection options are shown in Table 10.
Table 10. J38
Jumper
Position1Function
1-2 On-board LDO-generated 1.8 V connected to
IOVDD5
3-4 On-board LDO-generated 3.3 V connected to
IOVDD5
5-6 On-board LDO-generated 2.4 V connected to
IOVDD5
Off External power supply connected to
Test Pin IOVDD5 and Test Pin GND
1Jumper Position x-y means Pin x and Pin y are connected together via a
jumper capacitor.

Evaluation Board User Guide UG-284
Rev. 0 | Page 7 of 24
DIGITAL AUDIO INTERFACE AND DIGITAL MICROPHONE INTERFACE
09899-004
DIGITAL AUDIO
INTERFACE A
DIGITAL MIC
INTERFACE 1
DIGITAL MIC
INTERFACE 2
DIGITAL AUDIO
INTERFACE B
DIGITAL AUDIO
INTERFACE C
Figure 4. Digital Audio Interface and Digital Microphone Interface
The evaluation board provides three digital audio interfaces
(J28 to J30) and two digital microphone interfaces (J44/J45
and J46/J47).
The pin definitions for J28, J29, and J30 are shown in Figure 5,
Figure 6, and Figure 7, respectively.
1
3
5
7
9
11
2
4
6
8
10
12
GND
GND
GND
GND
GND
GND
MCLK1
GPIO1
A_BCLK
A_LRC
A_DACDAT
A_ADCDAT
09899-016
12
Figure 5. Pin Definitions for J28
1
3
5
7
9
11
2
4
6
8
10
12
GND
GND
GND
GND
GND
GND
MCLK2
GPIO2
B_BCLK
B_LRC
B_DACDAT
B_ADCDAT
09899-017
12
Figure 6. Pin Definitions for J29
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
1
3
5
7
9
11
2
4
6
8
10
12
GND
GND
GND
GND
GND
GND
NC
GPIO3
C_BCLK
C_LRC
C_DACDAT
C_ADCDAT
09899-018
12
Figure 7. Pin Definitions for J30
The pin definitions for J44 are listed in Table 11.
Table 11. J44
Pin No. Signal
1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (high)
4 NC
5 DMIC_CLK
6 GND

UG-284 Evaluation Board User Guide
Rev. 0 | Page 8 of 24
The pin definitions for J45 are listed in Table 12.
Table 12. J45
Pin No. Signal
1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (low)
4 NC
5 DMIC_CLK
6 GND
The pin definitions for J46 are listed in Table 13.
Table 13. J46
Pin No. Signal
1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (high)
4 NC
5 DMIC_CLK
6 GND
The pin definitions for J47 are listed in Table 14.
Table 14. J47
Pin No. Signal
1 IOVDD4
2 DMIC_DATA1
3 LR_SEL (low)
4 NC
5 DMIC_CLK
6 GND

Evaluation Board User Guide UG-284
Rev. 0 | Page 9 of 24
ANALOG INPUT AND OUTPUT
09899-005
SPEAKER
OUTPUT
HEADPHONE
OUTPUT
ANALOG
OUTPUT 2
ANALOG
OUTPUT 1
EARPIECE
OUTPUT
A
NALOG
INPUT 1
A
NALOG
INPUT 2
A
NALO
G
INPUT 3
A
NALOG
INPUT 4
Figure 8. Analog Input and Output Interface
On the board, there are four analog inputs (J4, J5, J8, and J9).
Near each input, there is a three-way jumper that selects which
bias voltage is routed to this input pair. These jumpers are J2, J3,
J6, and J7. The configurations are shown in Figure 9, and the
definitions of these jumper configurations are listed in Table 15,
Table 16, Table 17, and Table 1 8, respectively.
MICB2
MICB1
MICB2
MICB1
09899-019
POSITIONA POSITION B
Figure 9. Configuration for Jumpers J2, J3, J6, and J7
Table 15. J2
Position Function
A Microphone Bias 1 connected to Analog Input 1
B Microphone Bias 2 connected to Analog Input 1
Table 16. J3
Position Function
A Microphone Bias 1 connected to Analog Input 2
B Microphone Bias 2 connected to Analog Input 2
Table 17. J6
Position Function
A Microphone Bias 1 connected to Analog Input 3
B Microphone Bias 2 connected to Analog Input 3
Table 18. J7
Position Function
A Microphone Bias 1 connected to Analog Input 4
B Microphone Bias 2 connected to Analog Input 4
On the board, there are two analog outputs (J10 and J11),
one earpiece output for mono differential signals (J18), one
headphone output (J12), and two pairs of speaker outputs
(J13/J14 and J15/J16).

UG-284 Evaluation Board User Guide
Rev. 0 | Page 10 of 24
CLOCK AND CONTROL PORT
09899-006
I
2
C/SPI
SELECTION
I
2
C ADDRESS
SELECTION
EXTERNAL I
2
C
ADAPTER
CONNECTOR
EXTERNAL
CLOCK
IMPUT
MCLK2
S
ELECTION
JUMPER
MCLK1
S
ELECTION
JUMPER
RESET
Figure 10. Clock and Control Port
There are two master clock input pins for the ADAU1373:
MCLK1 and MCLK2. For each master clock, there are three
clock sources that can be selected by Jumper 21 and Jumper 22.
09899-023
1
2
OSC SMA1
POSITIONA
PSI
A
1
2
OSC SMA1
POSITION B
PSI
A
1
2
OSC SMA1
POSITION C
PSI
A
Figure 11. Configuration for Jumpers 21 and 22
J21 is for MCLK1 selection. The position definitions are shown
Figure 11 and Table 19.
Table 19. J21
Jumper
Position Function
A Use an on-board 12.288 MHz oscillator as MCLK1.
B Use an external SMA clock input as MCLK1.
C Use an audio precision PSIA MCLK input connected
to J28 as MCLK1.
J22 is for MCLK2 selection. The position definitions are shown
in Figure 11 and Table 2 0.
Table 20. J22
Jumper
Position Function
A Use an on-board 12.288 MHz oscillator as MCLK2.
B Use an external SMA clock input as MCLK2.
C Use an audio precision PSIA MCLK input connected
to J29 as MCLK2.
J23 is for the external I2C/SPI controller (USBi board) connec-
tion. J24 selects the control port mode of the ADAU1373. The
position definitions of this jumper are shown in Table 21.
Table 21. J24
Jumper Position Function
On I2C mode
Off SPI mode
J25 selects the I2C device address of the ADAU1373. The
position definitions of this jumper are shown in Table 22.
Table 22. J25
Jumper Position Function
On I2C devices address = 0x1C.
Off I2C devices address = 0x1A.

Evaluation Board User Guide UG-284
Rev. 0 | Page 11 of 24
EVALUATION BOARD SCHEMATICS AND ARTWORK
CPVSS
SPKVDD
HPVDD
IOVDD5
CPVDD
CF2
CF1 CF2
CPVSS
CPVDD
AIN2P
AIN2N
AIN1P
AIN1N AIN3N
AIN3P AIN4P
AIN4N
MICB1 MICB2
INFB1
INFB2
LOUTP
LOUTN
ROUTP
ROUTN EPP EPN RSPKN RSPKP LSPKN LSPKP BSTEN
RHP
SGND LHP
CSB
MODE
GPIO1
SCL SDA
GPIO4
C_LRC
IOVDD3
B_ADCDAT C_ADCDAT
B_DACDAT
MCLK2
GPIO3 GPIO2
MCLK1
A_DACDAT
A_LRC A_BCLK
B_BCLK
IOVDD1
C_DACDAT
IOVDD2 B_LRC
C_BCLK
A_ADCDAT
DMIC1
DMIC2
DMICCLK
IOVDD4
CF1
SDB JACKDECT
DVDD
AVDD
SDB JACKDECT
VBAT
CPVDD
CPVSS
CF2
CF1
AIN2P
AIN2N
AIN1P
AIN1N AIN3N
AIN3P AIN4P
AIN4N
MICB1 MICB2
INFB1
INFB2
ROUTN
ROUTP
LOUTN LOUTP
EPP
EPN
RSPKN
RSPKP
LSPKN
LSPKP
BSTEN
RHP SGND
LHP
CSB MODE GPIO1 SCL SDA GPIO4
C_LRC
B_ADCDAT C_ADCDAT
B_DACDAT
MCLK2
GPIO3
A_ADCDAT
GPIO2
MCLK1
A_BCLK
A_DACDAT
A_LRC
B_BCLK
C_DACDAT
B_LRC
C_BCLK DMIC1 DMIC2 DMICCLK
SDB
JACKDECT
VBAT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IOVDD5
GND
IOVDD5
IOVDD1
GND
IOVDD2
GND
IOVDD3
GND
IOVDD4
GND
IOVDD5
AVDD
HPVDD
DVDD SPKVDD
C14 0.1uf C14 0.1uf
SW1SW1
1
3
2
4
C4 2.2uF C4 2.2uF
C9 0.1uf C9 0.1uf
C5 2.2uf C5 2.2uf
C13 10uf C13 10uf
R1
100K
R1
100K R2
100K
R2
100K
U1
ADAU1373_WLCSP
U1
ADAU1373_WLCSP
VMID
B9
MICB1
C8
LOUTP
C7 LOUTN D8
ROUTP
D7 ROUTN D9
AVDD1 A9
AGND2
F8
SGND
G7 RHP G9 LHP G8
CPVDD H9
HPVDD H8
CF1 J9
HPGND
J8
CF2 J7
CPVSS H7
EPP
H6 EPN
J6
SPKGND2
H5
LSPKP
J4 LSPKN J3
RSPKP
J2 RSPKN
H1
SPKVDD1 G1
B_DACDAT F6 B_ADCDAT E3
B_LRC E2
B_BCLK E4
A_DACDAT D5 A_ADCDAT D4
A_LRC D3
A_BCLK D2
DVDD B1
DGND1
A1
IOVDD3 E1
MCLK1 C2
GPIO3 F5
SCL C5
SDA C3
DMIC1 B4
JACKDECT G5
SDB G6
AIN1N
A8 AIN1P B8
C_BCLK F2
C_LRC F1
C_ADCDAT G3 C_DACDAT F3
AIN2P
B7 AIN2N A7
AIN3P
B6 AIN3N A6
AIN4P
B5 AIN4N A5
MICB2
C9
INFB1
E7
INFB2
E8
VBATSENSE
F9 BSTEN
G4
SPKVDD2 G2
GPIO2 E6
IOVDD2 F4
MCLK2 D1
IOVDD1 C1
DGND2
E5
GPIO1 D6
CSB B2
MODE A2
GPIO4 C4
IOVDD4 A3 IOVDD5 B3
DMIC2 C6
DMICCLK A4
SPKGND1
H4
SPKGND3
J1
AVDD2 E9
AGND1
F7
SPKVDD3 H2
SPKVDD4 H3
SPKGND4
J5
C11 0.1uf C11 0.1uf
C19 0.1uF C19 0.1uF
C18 0.1uF C18 0.1uF
C1 0.1uf C1 0.1uf C16 0.1uf C16 0.1uf
C8 2.2uF C8 2.2uF
C15 2.2uF C15 2.2uF
C10 2.2uf C10 2.2uf
J1J1
1 2
C12 0.1uf C12 0.1uf
C2 0.1uf C2 0.1uf C7 0.1uf C7 0.1uf
C3 2.2uf C3 2.2uf
C6 0.1uf C6 0.1uf
C17 1uf C17 1uf
09899-007
Figure 12. Schematic of the ADAU1373 Evaluation Board, ADAU1373 Chip

UG-284 Evaluation Board User Guide
Rev. 0 | Page 12 of 24
09899-008
AIN2N
AIN4P
AIN4N
MB1 MB2 MB1
MB2 MB1 MB2
AIN1P
AIN1N
AIN2P
AIN3P
AIN3N
MB1 MB2
AIN2P AIN2N
AIN1P
AIN1N
AIN3P AIN3N
AIN4P
AIN4N
MICB1 MICB2
GND
GND GND
GND
GND GND
GND
GND
GND
GND GND
GND
GND
C28 1uF C28 1uF
C37 220pF, NC C37 220pF, NC
TP57TP57
1
C36 1uF C36 1uF
C23 220pF, NC C23 220pF, NC
TP70 1
C33 220pF, NC C33 220pF, NC C29 220pF, NC C29 220pF, NC
R5 0R R5 0R
J9 AUDIOJACK J9 AUDIOJACK
1 2 3
TP63 1
C25 220pF, NC C25 220pF, NC
J6J6
11
22
33
R96 NC R96 NC
C24 1uF C24 1uF C32 1uF C32 1uF
J5 AUDIOJACK J5 AUDIOJACK
1 2 3
C35 220pF, NC C35 220pF, NC R99
NC R99 NC
R9 0R R9 0R
R4
2K2
R4
2K2
R3
2K2
R3
2K2
J8 AUDIOJACK J8 AUDIOJACK
1 2 3
J3J3
11
22
33
TP64 1
J2J2
11
22
33
TP58TP58
1
R12 0R R12 0R
C26 1uF C26 1uF C34 1uF C34 1uF
R10 0R R10 0R
TP69TP69 1
C22 1uF C22 1uF
R8 0R R8 0R
J4 AUDIOJACK J4 AUDIOJACK
1 2 3
R6 0R R6 0R
TP67
1
TP59
1
C30 1uF C30 1uF
C27 220pF, NC C27 220pF, NC
TP65
1
C31 220pF, NC C31 220pF, NC
TP62
1
C21 0.1uF C21 0.1uF
R7 0R R7 0R R11 0R R11 0R
TP68
1
R98 NC R98 NC
TP61
1
TP60
1
R97 NC R97 NC
C20 0.1uF C20 0.1uF
TP66
1
J7J7
11
22
33
Figure 13. Schematic of the ADAU1373 Evaluation Board—Line Input

Evaluation Board User Guide UG-284
Rev. 0 | Page 13 of 24
09899-009
ROUTN
LOUTN
INFB2
ROUTP
LOUTP
INFB1
RHP
LHP
SGND
INFB2
ROUTN LOUTN
INFB1
ROUTP LOUTP
SGND
RHP LHP
GND GND
GND
GND
GND GND
GND
R16 100K, NC
R14 100K, NC
R20 NC
TP75
1
TP73
1
R21 0R
TP74
1
TP80
1
TP78
1
R13 100K, NC
R19 0R
J10
AUDIOJACK
1 2 3
C42 2.2uF
R25 0R,NC
R17 0R
C44 NC
R18 0R
R15 100K, NC
J11
AUDIOJACK
J11
1 2 3
C40 1uF
C38 1uF
R22 NC C45
NC
TP76
1
R24 0R
C41 1uF
R23
0R
0R
C39 1uF
TP72
1
J12
AUDIOJACK
1 2
3
TP71
1
TP77
1
TP79
1
C43 2.2uF
Figure 14. Schematic of the ADAU1373 Evaluation Board—Line and Headphone Output

UG-284 Evaluation Board User Guide
Rev. 0 | Page 14 of 24
09899-010
RSPKP RSPKN
LSPKP
LSPKN
BSTEN
VBAT
EPN
EPP
VBAT
LSPKP LSPKN
RSPKP RSPKN
BSTEN
GND
GND GND GND
GND GND GND
GND
SPKVDD
GND
R27
NC
TP83
1
TP84
1
R33 0R
J14J14
1
C54 10uf
R32 0R
L2
0R
C50 1nF, NC
R30 NC
L5 2.2uH
R26 NC
C53 NC
J13J13
1
L3
0R
J18
11 2
2
J17
11 2
2
TP89
1
C46 NC
R28 NC R28 NC
C47 NC
L1
0R C49
1nF, NC
TP87
1
C48 1nF, NC
TP85
1
R31
100K
TP56 1 R29 NC
J16J16
1
TP86 1
TP81
1
TP82
1
C51 1nF, NC
TP88
1
C52 NC
J19
1 2
L4
0R
J15J15
1
Figure 15. Schematic of the ADAU1373 Evaluation Board—Speaker and Receiver Output

Evaluation Board User Guide UG-284
Rev. 0 | Page 15 of 24
09899-011
PSIA_MCLK1 SMA_CLK 112896M_CLK
MCLK1
MCLK2
PSIA_MCLK2
112896M_CLK
SMA_CLK
PSIA_MCLK1
MCLK1
PSIA_MCLK2
MCLK2
GND
3V3
GNDGND
3V3
IOVDD13V3
GND
GND 3V3
GND IOVDD1
IOVDD23V3
GND
GND IOVDD2
J21
1 3 5
2 4 6
U2
FXLP34P5X
VCCI 1
VCC 5
A
2
GND
3
Y4
J20
SMA
5 4 3 2 1
J22
1 3 5
2 4 6
TP93
1
C56 0.1uf
R34 NC
TP92
1
TP90
1
L6 600ZU3
12.288MHz
VDD
4
OE
1
OUT 3
GND 2
U4
FXLP34P5X
VCCI 1
VCC 5
A
2
GND
3
Y4
R36 NC
R37
0R
R38 100K
C57 0.1uf
TP91
1
C58 0.1uf
R39
0R
R35
0R
C55 0.1uf
Figure 16. Schematic of the ADAU1373 Evaluation Board—Clock

UG-284 Evaluation Board User Guide
Rev. 0 | Page 16 of 24
09899-012
MODE
GPIO4
DMIC1
DMCLK
DMIC2
DMCLK
DMICCLK
SCL SDA
DMIC1 DMIC2
MODE
CSB
GPIO4
3V3 IOVDD5
IOVDD5
IOVDD5
IOVDD4
GND
GND
IOVDD4
GND
IOVDD5
GND
IOVDD5
GND
IOVDD5
R1050R
Q2, NC
N-MOSFET
D
3
G1
S2
J44
CON1x6
1
1
2
2
3
3
4
4
5
5
6
6
R43
NC
TP99
1
R45
2K2
TP95
1
J24
1 2
R46 100K
Q3, NC
N-MOSFET
D
3
G1
S2
R40
NC
R1060R
J45
CON1x6
1
1
2
2
3
3
4
4
5
5
6
6
R49
2K2
R44
NC
TP100
1
J23
11 33 55 77 99
2
2
4
4
6
6
8
8
10
10
TP94
1
R1040R
J46
CON1x6
1
1
2
2
3
3
4
4
5
5
6
6
J25
12
Q1, NC
N-MOSFET
D
3
G1
S2
TP98
1
J47
CON1x6
1
1
2
2
3
3
4
4
5
5
6
6
R47
100K
TP96
1
R50
100K
TP97
1
R41
2K2
R52
0R
R51
100K
R48
NC
R42
NC
Figure 17. Schematic of the ADAU1373 Evaluation Board—I2C Port and Digital Microphone Interface

Evaluation Board User Guide UG-284
Rev. 0 | Page 17 of 24
09899-013
A_ADCDAT_J
GPIO1
PSIA_MCLK1
A_BCLK_J A_BCLK
A_LRC_J A_LRC
A_DACDAT A_ADCDAT
B_DACDAT B_ADCDAT
B_BCLK_J B_BCLK B_LRC_J
B_ADCDAT_J
GPIO2
PSIA_MCLK2
C_LRC
C_DACDAT C_ADCDAT
C_BCLK
C_LRC_J
C_ADCDAT_J
C_BCLK_J
GPIO3
B_LRC
A_BCLK A_LRC A_DACDAT
A_ADCDAT
GPIO1 GPIO2
B_BCLK B_LRC B_DACDAT B_ADCDAT
GPIO3 C_BCLK C_LRC C_DACDAT C_ADCDAT
PSIA_MCLK2
PSIA_MCLK1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IOVDD1
IOVDD3
IOVDD2
GND
R81 0R
TP109
1
TP121
1
C64 22pF
R58 0R
C69 22pF
R64 49R9
C63 22pF
J30
1 3 5 7 9
11
2 4 6 8
10 12
R80 49R9
C68 22pF
R62 0R
TP106
1
TP113
1
TP111
1
R72 0R
C62 22pF
C71 22pF
TP101
1
C66 22pF
J29J29
1 3 5 7 9 11
2 4 6 8
10 12
R70 49R9
R53 49R9
R69 49R9
TP108
1
TP102
1
TP114
1
R67 49R9
TP103
1
R79 49R9
C65 22pF
R57 0R
R65 0R
R78 0R
R54 49R9
R59 49R9
C70 22pF TP115
1
R73 100K
TP105
1
R56 100K
C61 22pF
TP116
1
R68 49R9
R75 49R9
TP117
1
TP110
1
R55 100K
R66 0R
R74
0R
TP120
1
TP107
1
C60 22pF
R77 49R9
J28J28
1 3 5 7
9
11
2 4 6 8
10 12
R63 49R9
TP118
1
C72 22pF
C67 22pF
R76 0R
R71 0R
R61 0R
TP119
1
TP104
1
R60 49R9
TP112
1
C59 22pF
Figure 18. Schematic of the ADAU1373 Evaluation Board—Digital Audio Interface

UG-284 Evaluation Board User Guide
Rev. 0 | Page 18 of 24
09899-014
AVDD
5V
5V
GND
DVDD
5V
GND
HPVDD
5V
GND GND
J33 12
TP125
1
J35
1 2
C77 0.1uF
C78 10uf
C73 10nF
C76 0.1uf
J31 12
R82
1K
C83 10nF
TP123
1
TP127
1
U5
ADP1715_1V8
GND0
5GND1 6GND2 7GND3 8
EN 1
IN 2
OUT 3
ADJ 4
R86
1K
1K
C79 10nF
D3
GREEN
C96 1nF
R87 10K
C82 10uf
R83
1K
TP122
1
L7
600Z
C84 0.1uf
R84 10K
Q6
MMBT3904
2 3
1
C74 0.1uF
R85 10K
C75 10uf
J34
PowerJack
3 2 1
J32 12
Q4
MMBT3904
2 3
1C80
0.1uf
U7
ADP1715_1V8
GND0
5
GND1
6
GND2
7
GND3
8
EN 1
IN 2
OUT 3
ADJ 4
Q5
MMBT3904
2 3
1
D1
GREEN
D2
GREEN
TP126
1
TP124
1
C81 0.1uF
U6
ADP1715_1V5
GND0
5
GND1
6
GND2
7
GND3
8
EN 1
IN 2
OUT 3
ADJ 4
Figure 19. Schematic of the ADAU1373 Evaluation Board—Power Supply

Evaluation Board User Guide UG-284
Rev. 0 | Page 19 of 24
09899-015
5V
GND
GND
3V3
5V
SPKVDD
GND
1V8
5V
1V8
3V3
IOVDD1 1V8
3V3
IOVDD2 1V8
3V3
IOVDD3 1V8
3V3
IOVDD4 1V8
3V3
IOVDD5
GND GND GND GND GND
2V4 2V4 2V4 2V4
GND
2V4
5V
2V4
TP142
1
U11
ADP1708
EN
1
GND
2
IN1
3IN2 4
ADJ 8
SENSE 7
OUT1 6 OUT2 5
PAD
9
R92
1K J41
1
R100
1K
R88
1K
R88
1K
C95 10uf
TP139
1
Q9
MMBT3904
2 3
1
TP132
1
Q10
MMBT3904
2 3
1
C93 0.1uF
C94 10uf
C91 10uf C91 10uf
R103 2K
TP138
1
Q7
MMBT3904
Q7
MMBT3904
2 3
1
J37 CON2x3
1 3 5
2 4 6
C89 0.1uF C89 0.1uF
D5
GREEN
D5
GREEN
TP145
1
TP128TP128
1
C92 10uf C92 10uf
J40
1 2
J39 CON2x3
1 3 5
2 4 6
Q8
MMBT3904
Q8
MMBT3904
2 3
1
J43 CON2x3
1 3 5
2
4
6
C88 10uf C88 10uf
TP140
1
C86 10uf C86 10uf
C98 10uf
TP130TP130
1
D6
GREEN
D6
TP135
1
TP137
1
TP143
1
U9
ADP1715_1V8
U9
ADP1715_1V8
GND0
5GND1 6GND2 7GND3 8
EN 1
IN 2
OUT 3
ADJ 4
R91 10K R91 10K
C100 0.1uF
C85 10nF C85 10nF
R94 10K
J42
1
R93 3.48K
J38 CON2x3
1 3 5
2 4 6
R90 10K R90 10K
R89
1K
R89
1K
TP134
1
U8
ADP1715_3V3
U8
ADP1715_3V3
GND0
5GND1 6GND2 7GND3 8
EN 1
IN 2
OUT 3
ADJ 4
R102 1K
TP141
1
R95
1k
U10
ADP1715_ADJ
GND0
5
GND1
6
GND2
7GND3 8
EN 1
IN 2
OUT 3
ADJ 4
TP131TP131
1
TP144
1
C90 10nF C90 10nF
R101 10K
TP136
1
C87 0.1uF C87 0.1uF
D4
GREEN
D4
GREEN
D7
GREEN
C97 10uf
TP133
1
J36 CON2x3
1 3 5
2 4 6
TP129TP129
1
Figure 20. Schematic of the ADAU1373 Evaluation Board—Power Supply

UG-284 Evaluation Board User Guide
Rev. 0 | Page 20 of 24
ORDERING INFORMATION
BILL OF MATERIALS
Table 23.
Qty Part Reference Description Manufacturer Part Number
9 C1, C11, C12, C14, C16, C2, C6, C7, C9 MLCC, 0.1 μF, 0402 Panasonic ECJ-0EX1C104K
3 C10, C3, C5, MLCC, 2.2 μF, 0603 Panasonic ECJ-1VB1A225K
13 C13, C54, C75, C78, C82, C86, C88, C91, C92,
C94, C95, C97, C98
MLCC, 10 μF, 0805 Panasonic ECJ-2FF1A106Z
1 C17 MLCC, 1 μF, 0402 Panasonic ECJ-0EB1A105M
12 C22, C24, C26, C28, C30, C32, C34, C36, C38,
C39, C40, C41
MLCC, 1 μF, 0603 Panasonic ECJ-1VB1A105K
21 C18, C19, C20, C21, C42, C43, C55, C56, C57,
C58, C74, C76, C77, C80, C81, C84, C87, C89,
C93, C96, C100
MLCC, 0.1 μF, 0603 Panasonic ECJ-1VB1H104K
3 C4, C8, C15 MLCC, 2.2 μF, 0402 Panasonic ECJ-0EB0J225M
6 C44, C45, C46, C47, C52, C53 Capacitor (open)
4 C48, C49, C50, C51 Capacitor (open)
8 C23, C25, C27, C29, C31, C33, C35, C37 Capacitor (open)
14 C59, C60, C61, C62, C63, C64, C65, C66, C67,
C68, C69, C70, C71, C72
Capacitor (open)
5 C73, C79, C83, C85, C90 MLCC, 10 nF, 0603 Panasonic ECJ-1VB1H103K
7 D1, D2, D3, D4, D5, D6, D7, LED, green Lumex SML-LXT0805GW-TR
8 J1, J19, J24, J25, J31, J32, J33, J40 Jumper, 2 mm pitch
7 J10, J11, J12, J4, J5, J8, J9 Stereo audio jack CUI SJ-3523-SMT
6 J13, J14, J15, J16, J41, J42 Binding post connector Johnson/Emerson 111-2223-001
3 J17, J18, J35 Jumper, 2.54 mm pitch
4 J2, J3, J6, J7 Header, 3-way (1 × 3)
1 J20 SMA header MULTICOMP 60-04 TGG
7 J21, J22, J36, J37, J38, J39, J43 Header, 6-way (2 × 3)
1 J23 Header, 10-way (2 × 5), polarized
3 J28, J29, J30 Header, 12-way (2 × 6)
1 J34 Power jack Switchcraft Inc. RAPC712
4 J44, J45, J46, J47 Header, 6-way (1 × 6)
4 L1, L2, L3, L4 Chip resistor, 0 Ω, 0805 Panasonic ERJ-6GEY0R00V
1 L5 Inductor (open)
2 L6, L7 Chip ferrite bead, 600 Ω at 100 MHz TDK MPZ1608S601A
3 Q1, Q2, Q3 N-MOSFET (open)
7 Q10, Q4, Q5, Q6, Q7, Q8, Q9 Transistor, NPN, SOT23 ON
Semiconductor
MMBT3904LT1G
11 R1, R2, R31, R38, R46, R47, R50, R51, R55, R56,
R73
Chip resistor, 100 kΩ, 0603 Panasonic ERJ-3EKF1003V
33 R10, R104, R105, R106, R11, R12, R17, R18,
R19, R21, R23, R24, R35, R37, R39, R5, R52,
R57, R58, R6, R61, R62, R65, R66, R7, R71, R72,
R74, R76, R78, R8, R81, R9
Chip resistor, 0 Ω, 0603 Panasonic ERJ-3GEY0R00V
9 R100, R102, R82, R83, R86, R88, R89, R92, R95 Chip resistor, 1 kΩ, 0603 Panasonic ERJ-3EKF1001V
7 R101, R84, R85, R87, R90, R91, R94 Chip resistor, 10 kΩ, 0603 Panasonic ERJ-3EKF1002V
1 R103 Chip resistor, 2 kΩ, 0603 Panasonic ERJ-3EKF2001V
4 R13, R14, R15, R16 Chip resistor (open)
18 R20, R22, R26, R27, R28, R29, R30, R34, R36,
R40, R42, R43, R44, R48, R96, R97, R98, R99
Chip resistor (open)
1 R25 Chip resistor (open)
5 R3, R4, R41, R45, R49 Chip resistor, 2.2 kΩ, 0603 Panasonic ERJ-3EKF2201V
2 R32, R33 Chip resistor, 0 Ω, 0805 Panasonic ERJ-6GEY0R00V