Analog Devices EVAL-ADP5020 User manual

Evaluation Board for Power Management
Unit for Imaging Modules
EVAL-ADP5020
Rev. 0
Evaluation boards are only intended for device evaluation and not for production purposes.
Evaluation boards are supplied “as is” and without warranties of any kind, express, implied, or
statutory including, but not limited to, any implied warranty of merchantability or fitness for a
particular purpose. No license is granted by implication or otherwise under any patents or other
intellectual property by application or use of evaluation boards. Information furnished by Analog
Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result
from its use. Analog Devices reserves the right to change devices or specifications at any time
without notice. Trademarks and registered trademarks are the property of their respective owners.
Evaluation boardsare not authorized to be used in life support devices or systems.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
Input voltage: 2.4 V to 5.5 V
Evaluates three regulators (Buck 1, Buck 2, and LDO)
USB to I2C interface translation
Jumpers for input current measurement of regulators
Supports EN, SYNC, and XSHTDWN pin interface
Evaluation software included
GENERAL DESCRIPTION
The evaluation system is composed of a motherboard and
a daughterboard. The motherboard provides the I2C® signals
from the computer USB port and generates the I/O voltages
and digital high and low signals for the daughterboard.
The motherboard features a 3.3 V regulator (VBOARD) a 3.7 V
regulator (VBATT) and a 2.0 V regulator (VDDIO). VDDIO is
the digital I/O voltage supplying the I2C interface and the control
pins. VBOARD is the motherboard logic supply while VBATT
provides power to the daughterboard. Jumpers on the top left
of the motherboard define whether the internal regulators are
supplied from the USB port or from external supplies connected to
J10. The VBUS line from the USB connector powers the mother-
board regulators when Jumper LK8 to Jumper LK10 are in the
USB position. Connector J10 provides supply voltages for the
motherboard and daughterboard when Jumper LK8 to Jumper
LK10 are in the EXT position.
The daughterboard contains numerous jumpers, LEDs, and test
points for easy evaluation and monitoring of the board.
MOTHERBOARD AND DAUGHTERBOARD LAYOUT
07794-001
Figure 1.

EVAL-ADP5020
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TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Motherboard and Daughterboard Layout..................................... 1
Revision History ............................................................................... 2
Software Installation......................................................................... 3
USB Driver Installation.................................................................... 5
Evaluation Board Software .............................................................. 6
Quick Start..................................................................................... 6
Using the Software........................................................................ 8
View/Modify Register Settings ................................................... 8
Program/Run Turn-On Sequence............................................ 10
Program/Run Turn-Off Sequence............................................ 10
Registers Commands ................................................................. 10
Register Command Options ..................................................... 11
Load/Save Registers Configuration.......................................... 12
Additional Commands.............................................................. 12
Warni ng ....................................................................................... 12
History ......................................................................................... 12
Evaluation Board Overview .......................................................... 13
Motherboard ............................................................................... 13
Daughterboard............................................................................ 14
Evaluation Board Schematics........................................................ 16
Motherboard Schematics .......................................................... 16
Daughterboard Schematic......................................................... 18
PCB Layout. ................................................................................ 19
Ordering Information.................................................................... 21
Bill of Materials........................................................................... 21
Ordering Guide .......................................................................... 22
ESD Caution................................................................................ 22
REVISION HISTORY
5/09—Revision 0: Initial Version

EVAL-ADP5020
Rev. 0 | Page 3 of 24
SOFTWARE INSTALLATION
1. Before starting the software installation, make sure that the
ADP5020 adapter board is not connected to the PC USB port.
2. The application software is a compiled LabVIEW™ program
requiring the LabVIEW 8.5 run-time engine to be installed
on the PC. Download the LabVIEW run-time engine from
National Instruments.
3. After installation, reboot the PC to complete the operation
if necessary. Note that if the PC already has LabVIEW
installed, this step is not needed.
4. Launch the file Setup.exe. When the dialog box shown in
Figure 2 appears, click Next > to continue.
07794-002
Figure 2. ADP5020 Evaluation Software Setup
5. Click Ye s to accept the license agreement.
07794-003
Figure 3. License Agreement
6. Click Next > to install the files to the default destination
folder or click Browse…to choose a different file.
07794-004
Figure 4. Choose Destination Location
7. Click Next > to continue with the installation.
07794-005
Figure 5. Setup Type

EVAL-ADP5020
Rev. 0 | Page 4 of 24
8. Click Next > to install the program to the default
program folder.
07794-006
Figure 6. Select Program Folder
9. Wait while the program installs.
07794-007
Figure 7. Setup Status
10. Click Finish to complete the installation.
07794-008
Figure 8. InstallShield Wizard Complete

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USB DRIVER INSTALLATION
1. Plug the ADP5020 board into the computer using the USB
cable provided with the evaluation kit. Once the system recog-
nizes the board, the dialog box shown in Figure 9 appears.
2. Click Next > to install the driver.
07794-009
Figure 9. Found New Hardware Wizard
3. Click Continue Anyway and then Finish to complete the
driver installation.
07794-010
Figure 10. Hardware Installation
4. Open the Device Manager and check that the USB driver is
installed properly.
07794-011
Figure 11. Check Driver Installation
When the USB cable is connected to a PC port different from
the one used to install the driver, the PC device driver may ask
to install the driver again for that specific port. If this happens,
follows the same steps described in the USB driver installation.

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EVALUATION BOARD SOFTWARE
QUICK START
Make sure that the software and the USB driver are installed as
described in the Software Installation and USB Driver Installation
sections. Connect the board as shown in Figure 12. Upon
connecting the USB cable, the D19, D20, and D21 indicators
light up, indicating that the supplies are connected.
Click the Start button, located at the bottom left-hand corner of
your desktop. Select All Programs, then Analog Devices, then
ADP5020 Evaluation Software, and then ADP5020 Evaluation
SW to load the software. If the program starts correctly and the
board is detected, the ADP5020 graphical user interface (GUI)
appears as shown in Figure 13.
The program default settings are as follows:
•All registers initialized to zero.
•Software turn-on sequence is: Buck 1 first, Buck 2 second,
LDO third. Delay between activations is 1000 ms.
•Software turn-off sequence is: LDO first, Buck 2 second,
Buck 1 third. Delay between activations is 1000 ms.
•Regs Refresh check box is cleared (status registers are not
read periodically).
•Refresh delay is 1000 ms.
•Smart Update check box is selected (any change to the
registers control triggers a write operation to the device).
•Verify after write check box is selected (a write operation
is followed by a read for verification).
INSTALL
DAUGHTERBOARD
07794-012
CONNECT USB MINI B
CABLE
USB
OPTIONAL SIGNAL
GENERATOR (SYNC)
D21 D19D20
ACTIVATION
INDICATORS
EN/GPIO
LDO ON
BUCK2
BUCK1
XSHTDWN
Figure 12. ADP5020 Board Connections

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CLOSE
APPLICATION
07794-013
READ DEVICE
REGISTERS
WRITE DEVICE
REGISTERS
VIEW/MODIFY
REGISTERS
CREATE
SOFTWARE
SEQUENCING
ENABLE CONTEXT HELP
STOP
APPLICATION
Figure 13. ADP5020 GUI

EVAL-ADP5020
Rev. 0 | Page 8 of 24
USING THE SOFTWARE
1
2
3
1. VIEW/MODIFY REGISTER SETTINGS.
2. PROGRAM/RUN SOFTWARE TURN-ON SEQUENCE.
3. PROGRAM/RUN SOFTWARE TURN-OFF SEQUENCE.
4. REGISTERS COMMANDS.
5. REGISTERS COMMANDS OPTIONS.
6. LOAD/SAVE REGISTERS CONFIGURATION.
5
6
4
07794-014
Figure 14. Evaluation Board Software
Before running the software, ensure that the board is plugged
into the computer USB port (the VBATT OKAY, VDDIO
OKAY, and VOBARD OKAY LEDs on the motherboard should
light up).
Install the ADP5020 evaluation software as described in the
Quick Start section. Failure to detect the adapter board prompts
an error message, as shown in Figure 15. If this occurs, check
the connection and restart the program.
07794-015
Figure 15. Board Detection Failure
VIEW/MODIFY REGISTER SETTINGS
The USER REGISTERS section of the GUI window displays
the ADP5020 register settings (following a Read Registers
operation) and allows you to modify the current values. To
facilitate operation, all the possible device configurations are
listed in the drop-down boxes. You c an select the desired value,
then program the device by clicking the Write Registers button.
If the Smart Update check box is selected (default condition),
as soon as a register value is changed, the application sends a
programming command for that specific register without the
need to click the Write Registers button. When the Smart
Update check box is cleared, data is written to the device only
after clicking the Write Registersbutton.
The Buck 1 Vout Sel.drop-down box allows you to change the
Buck 1 regulator output voltage to one of the following settings:
2.5 V, 2.8 V, 2.9 V, 3.0 V, 3.2 V, 3.3 V, or 3.7 V. The default value
is 3.3 V. This box corresponds to BK1_VSEL, Bits[2:0] in the
BUCK1_VSEL register (Address 0x01).
The Buck 2 Vout Selection drop-down box allows you to change
the Buck 2 regulator output voltage to one of the following
settings: 1.1 V, 1.2 V, 1.3 V, 1.4 V, 1.5 V, 1.6 V, 1.7 V, or 1.8 V.
The default value is 1.2 V. This box corresponds to BK2_VSEL,
Bits[7:4] in the BUCK2_LDO_VSEL register (Address 0x02).

EVAL-ADP5020
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The LDO Vout Selection drop-down box allows you to change
the LDO regulator output voltage to one of the following settings:
1.8 V, 1.9 V, 2.0 V, 2.1 V, 2.2 V, 2.3 V, 2.4 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V,
2.9 V, 3.0 V, 3.1 V, 3.2 V, or 3.3 V. The default value is 1.8 V. This
box corresponds to LDO_VSEL, Bits[3:0] in the BUCK2_
LDO_VSEL register (Address 0x02).
The Buck 1 Control check box activates, if selected, or deactivates,
if cleared, the Buck 1 regulator. This check box corresponds to
BK1_EN, Bit[7] in the REG_CONTROL_STATUS register
(Address 0x03).
The Buck 2 Control check box activates, if selected, or deactivates,
if cleared, the Buck 2 regulator. This check box corresponds to
BK2_EN, Bit[6] in the REG_CONTROL_STATUS register
(Address 0x03).
The LDO Control check box activates, if selected, or deactivates,
if cleared, the LDO regulator. This check box corresponds to
LDO_EN, Bit[5] in the REG_CONTROL_STATUS register
(Address 0x03).
The Enable All Regulators check box activates, if selected, or
deactivates, if cleared, all regulators available. This check box
corresponds to EN_ALL, Bit[4] in the REG_CONTROL_STATUS
register (Address 0x03).
The XSHTDWN on Buck 1 check box allows you to mask the
Buck 1 power-good (PGOOD) signal, if selected, or to control
the power-good signal, if cleared, to generate the XSHTDWN
signal. This check box corresponds to BK1_XSHTDN, Bit[3] in
the OPERATIONAL_CONTROL register (Address 0x04).
The XSHTDWN on Buck 2 check box allows you to mask the
Buck 2 power-good (PGOOD) signal, if selected, or to control
the power-good signal, if cleared, to generate the XSHTDWN
signal. This check box corresponds to BK2_XSHTDN, Bit[2] in
the OPERATIONAL_CONTROL register (Address 0x04).
The XSHTDWN on LDO check box allows you to mask the
LDO power-good (PGOOD) signal, if selected, or to control
the power-good signal, if cleared, to generate the XSHTDWN
signal. This check box corresponds to LDO_XSHTDN, Bit[1]
in the OPERATIONAL_CONTROL register (Address 0x04).
The Force XSHTDWN check box, if cleared, forces the XSHTDN
pin level to Logic 0; if selected, the XSHTDN logic level depends
on the power-good (PGOOD) status of the regulators. This check
box corresponds to FORCE_XS, Bit[0] in the REG_CONTROL_
STATUS register (Address 0x03).
The Buck 1 PGOOD check box shows the power-good status
for the Buck 1 regulator. If the check box is selected, the Buck 1
regulator is operating correctly; if cleared, it indicates that the
Buck 1 regulator is either not activated or in a failing condition.
This check box corresponds to BK1_PGOOD, Bit[3] in the
REG_CONTROL_STATUS register (Address 0x03).
The Buck 2 PGOOD check box shows the power-good status
for the Buck 2 regulator. If the check box is selected, the Buck 2
regulator is operating correctly; if cleared, it indicates that the
Buck 2 regulator is either not activated or in a failing condition.
This check box corresponds to BK2_PGOOD, Bit[2] in the
REG_CONTROL_STATUS register (Address 0x03).
The LDO PGOOD check box shows the power-good status for
the LDO regulator. If the check box is selected, the LDO regula-
tor is operating correctly; if cleared, it indicates that the LDO
regulator is either not activated or in a failing condition. This
indicator corresponds to LDO_PGOOD, Bit[1] in the REG_
CONTROL_STATUS register (Address 0x03).
The Thermal Shutdown check box shows the status for the
thermal shutdown (TSD) protection. If the check box is selected,
the device is in a TSD condition; if cleared, it indicates that the
device is operating normally. This check box corresponds to TSD,
Bit[0] in the OPERATIONAL_CONTROL register (Address 0x04).
When this check box is selected (set to 1), you must clear this
check box, then write this bit back to the device to clear a TSD
condition. Make sure to clear the Regs Refresh check box to
override this indicator. If the Regs Refresh option is enabled
(check box is selected), the periodic refresh writes back the TSD
indicator and you will not be able to clear the TSD bit. You must
not write this indicator (that is, you must not click the Write
Registersbutton ) while the Thermal Shutdown check box is
selected (set to 1) because this forces a TSD condition and the
regulators, if enabled, stops working.
The EN/GPIO Options drop-down box allows you to program
the function associated with the EN/GPIO pin to one of the follow-
ing settings: input high impedance, output low, or output high.
This box corresponds to ENO_DRV, Bit[0], and ENO_HIZ_BAR,
Bit[1], in the EN_CONTROL register (Address 0x05).
The SYNC Options drop-down box allows you to program the
function associated with the SYNC pin to one of the following
settings: internal clock, external dc-coupled 9.6 MHz clock,
external dc-coupled 19.2 MHz clock, external ac-coupled
9.6 MHz clock, or external ac-coupled 19.2 MHz clock. This
box corresponds to SYNC_9P6, Bit[6], and SYNC_19P2, Bit[5],
in the OPERATIONAL_CONTROL register (Address 0x04).
The DEVICE REVISION box shows the major and minor
revision, and the specific device option. It is not possible to alter
the values in this box because it is a hard-coded value in the
device. This box corresponds to MAJ, Bits[7:5], MIN, Bits[4:2],
and OPT, Bits[1:0], in the revision register (Address 0x00).
To read or write the device register in bit or byte format as
shown in the device memory map (see the ADP5020 data
sheet), you can open the registers map utility by clicking the
Registers MAP button. See the Registers Commands section
for additional information.

EVAL-ADP5020
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PROGRAM/RUN TURN-ON SEQUENCE
The TURN ON SEQUENCE section of the GUI window allows
you to create and run simple activation patterns for the available
regulators, mimicking the desired regulator sequence needed for a
specific application. The First Regulator option button allows you
to turn on the first regulator and R1 to R2 Delay allows you to
program the delay between the first and second regulator from
1 ms to 10 sec. The Second Regulator option button allows you
to turn on the second regulator, and R2 to R3 Delay allows you to
program the delay between the first and second regulator from
1 ms to 10 sec. Finally, the Third Regulator option button allows
you to turn on the third and last regulator. It is not possible to select
more than one regulator under each regulator box (for example,
you cannot select both Buck 2 and Buck 1 under First Regulator).
However, if the application requires more than one regulator to be
turned on at the same time, set the R1 to R2 Delay time to 0 ms,
then select another regulator under Second Regulator. If all three
regulators must be activated at the same time, set the R2 to R3
Delay time to 0 ms, then select the third regulator under Third
Regulator.
Click the Start TON Sequence button to run the programmed
pattern. Once the pattern is sent to the ADP5020 in the daughter-
board, the Regs are OFF indicator changes to Regs are ON and
lights up.
07794-016
Figure 16. Turn-On Sequence Example
Figure 16 shows a sequencing example where the first regulator
activated is Buck 1. After one second, Buck 2 is activated. After
another second, the LDO turns on. The XSHTDWN signal
becomes high 1 ms after the last regulator (LDO in this example).
This delay is hardcoded in the ADP5020 and cannot be changed.
The software automatically sets the XSHTDN masking bit if the
regulators are set to None. Although unnecessary, it is possible
to create a sequence where all the regulators are set to None (that
is, all disabled).
Once a sequence is started, you can verify the PGOOD and TSD
device status (under Buck 1 PGOOD, Buck 2 PGOOD, LDO
PGOOD, and Thermal Shutdown) in the USER REGISTER
section of the GUI. If the option Regs Refresh is enabled (that
is, the check box is selected), the status of PGOOD and TSD is
updated automatically at the rate programmed under the Refresh
Rate box.
Note that the timing used for the sequencing uses the PC internal
clock with 1 ms resolution. In addition, there are time lags due to
the program execution and communication with the adapter
board. Therefore, timing precision may be affected, especially for
short durations, and may vary from PC to PC.
PROGRAM/RUN TURN-OFF SEQUENCE
The turn-off sequence follows the same indications provided for
the turn-on sequence except that the operation is executed in
reverse order.
REGISTERS COMMANDS
The Read Registers button, when clicked, reads all the ADP5020
internal registers (Addresses 0x00 to Address 0x05) and updates
the USER REGISTERS section with the new values.
The Write Registers button, when clicked, writes the current
registers values set in the USER REGISTERS section into the
ADP5020 volatile memory. If the Verify after write check box is
selected, the program reads back the programmed registers and
compares the device values with the set values (buffer). If one or
more errors are detected, a message appears, indicating the
registers at fault. Figure 17 shows a verification error example.
07794-017
Figure 17. Verification Error
The Clear Regs button, when clicked, sets the registers to 0.
A message appears requesting confirmation to continue (click
YES) with the operation or abort it (click NO), leaving the
registers unchanged.
07794-018
Figure 18. Register Clearing Confirmation

EVAL-ADP5020
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The Registers MAP button, when clicked, activates another
method to read and write the ADP5020 registers, as shown in
Figure 19.
The register values, previously set, are transferred into the Register
MAP window. You h ave the choice to modify the registers bitwise
by clicking the desired bit position. The bit value then switches
from 0 to 1, or vice versa. It is not possible to change the values
for the grayed bits. The register values can also be changed by
entering a hexadecimal value in the text box for the respective
register (for example, 4C is entered for Register 0x00 in Figure 19).
The Hex/Dec button allows you to change the data format of
the register values from hexadecimal to decimal, or vice versa.
Binary and Byte controls are intercommunicating; therefore,
changes to one control are automatically reflected in the other.
The Rand Wbuttons next to each register allow reading or writing
a specific device address, and the Read ALL and Wr i te ALL
buttons allows you to read or write the entire register map from
or to the ADP5020 under evaluation. The OK/Fail indicator
next to these two buttons shows the operation result. Click EXIT
to return in the main window. The modified registers are then
transferred automatically into the USER REGISTER section of
the GUI window.
The register map utility does not have the Smart Update
option; therefore, a new value is written into the ADP5020
following a write operation (by clicking the Wor Write ALL
buttons).
REGISTER COMMAND OPTIONS
The Regs Refresh check box, when selected, enables the
program to read the device statuses periodically. The refresh
time is programmable in the Refresh Rate box from 100 ms to
10 sec. The registers read during the refresh are Register 0x00, the
revision register, Register 0x03 (BK1_PGOOD, BK2_PGOOD,
and LDO_PGOOD), and Register 0x04 (TSD), providing a real-
time indication of the device functionality. If a thermal shutdown
event is detected, you must disable the register refresh option
(clear the Regs Refresh check box) to clear the TSD flag. The
Access blue indicator, when lit up, indicates that the refresh
operation is taking place.
The Smart Update check box, when selected, enables the pro-
gram to automatically write an ADP5020 register when a USER
REGISTER option has been changed. This avoids the need to click
the Write Registers button every time a value is changed. The
Smart Update check box must be cleared if you want to control the
write operations.
07794-019
Figure 19. Register MAP Utility

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LOAD/SAVE REGISTERS CONFIGURATION
The software program allows saving a specific register configura-
tion and loading it back into the USER REGISTERS section.
The Save Config button, when clicked, opens the file utility
where you can specify the directory and file name to save. The
default extension is *.dat.Maintaining this convention is recom-
mended. If the file does not exist, it is created; if the file already
exists, it is overwritten.
07794-020
Figure 20. Save Configuration
The Load Config button, when clicked, opens the file utility
where you can specify the directory and file name to load.
The default extension is *.dat. If you choose to cancel the
operation, an error message appears (see Figure 21). Click
Continue to abort the operation.
07794-021
Figure 21. Load/Save Error Message
ADDITIONAL COMMANDS
The INFO button, when clicked, provides information regarding
the software revision number and other release notes.
The EXIT button, when clicked, stops the program, leaving the
window active and open. To terminate the program completely,
click the close button (X) on the upper right corner of the applica-
tion window.
On-line help is available by selecting Show Context Help from the
Help menu, or by pressing CTRL + H. Moving the pointer over a
control option or indicator displays information related to it in the
context help window.
WARNING
Upon starting the ADP5020 application, a dedicated firmware
is loaded into the adapter board processor (Cypress IC). This
firmware is needed for the operation of the USB adapter and
communication with the ADP5020 daughterboard. If the evalua-
tion board is not connected through the USB cable, an error
message, as indicated in Figure 15, appears on the screen. This
indicates that the firmware was not loaded into the adapter
board. If this happens, check the USB connection and ensure
that Jumper LK10 is in the USB position. The firmware is loaded
in volatile memory inside the Cypress processor; therefore, if
power is removed or the USB cable is disconnected, the firmware
is lost. If this happens, close the application, connect the adapter
board, and then launch the ADP5020 application again to
reload the firmware.
It is recommended to always stop the program (click the EXIT
button) before removing the USB cable.
HISTORY
Whenever a command is issued (both read and write), it is
recorded in the History dialog box shown in Figure 22.
To display the History dialog box, click the History button on
the bottom right corner of the software GUI (see Figure 14). To
clear the history, click Clear History.
You can copy and paste the history into a file for future
evaluation purposes.
07794-022
Figure 22. History

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EVALUATION BOARD OVERVIEW
MOTHERBOARD
EXTERNAL
SUPPLIES USB
CONNECTOR
INT/EXT SUPPLIES
JUMPER SELECTION
VBATT LED
INDICATOR
VDDIO LED
INDICATOR
VBOARD LED
INDICATOR
SYNC PIN
SELECTION
EXTERNAL
FREQUENCY
ON SYNC PIN
CONNECTOR
EN PIN EXTERNAL
FORCING LEVEL
XSHTDWN
STATUS LED
ADP5020 TEST-POINTS
DAUGHTERBOARD
CONNECTORS
EN/GPIO
STATUS LED
BUCK2 REGULATOR
ACTIVATION LED
LDO REGULATOR
ACTIVATION LED
BUCK1 REGULATOR
ACTIVATION LED
07794-023
Figure 23. Motherboard
The ADP5020 motherboard provides the interface signals to the
ADP5020 power management IC. These include the SDA and
SCL lines for I2C, or the control line voltages for the hardware
interface modes (EN/GPIO, SYNC, and XSHTDWN).
The Cypress Semiconductor Corporation CY7C68013A
provides the USB interface and I2C signals. The selected I2C
frequency is 100 kHz. The M24C64R serial EEPROM provides
the USB address of the board. The interface voltage is selected
with the VBOARD header on the board and is set to 3.3 V by
default.
Typically, the daughterboard is inserted directly into the 2 × 20-pin
header of the motherboard. For temperature measurements,
however, it may be necessary to use an extension cable to connect
the motherboard and the daughterboard because the Cypress
CY7C68013A is not rated at −40°C. The 8-pin Header J10 on
the top of the motherboard can be used to connect external
supplies.
The VBATT OKAY, VDDIO OKAY, and VBOARD OKAY LEDs
located at the top left of the board lights up when the board is
powered from the USB cable, or when external supplies are
connected to J10 and Jumper LK8 to Jumper LK10 are set in the
EXT position. It is possible to choose several supply combinations.
For example, VBOARD, which supplies the motherboard ICs, can
be provided from the USB while VDDIO and VBATT are provided
externally. The motherboard contains three LDOs generating
the default supply voltage, as indicated in Table 1.
Table 1. Power Supply Options
Supply Line
LK8 to LK10 in
USB Position
LK8 to LK10 in EXT
Position
VBATT Internal: 3.7 V External: 2.3 V to 5.5 V
VDDIO Internal: 2.0 V External: 1.7 V to 3.6 V
VBOARD Internal: 3.3 V External: 2.7 V to 3.6 V
Jumper LK11 defines the forcing level for the EN/GPIO pin.
With the jumper in the low position, the EN/GPIO pin is forced
to logic low. With the jumper in the high position, the EN/GPIO
pin is forced to logic high. The VDDIO supply line determines
the logic level.
Jumper LK12 selects the clock mode for the SYNC pin. With the
jumper in the GND position, the SYNC pin is tied to ground. With
the jumper in the EXT position, an external frequency can be
applied to the SYNC pin through Connector SM2. The logic level
of the clock signal must be referred to the VDDIO supply level.

EVAL-ADP5020
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DAUGHTERBOARD
The ADP5020 evaluation daughterboard is designed to quickly
evaluate key parameters of the ADP5020 IC. The board layout
footprint is extended so that parts can be exchanged easily, and
headers are available to measure currents using a current probe
or ammeter.
Connect a power supply or Li-Ion battery with 2 A capability
to VBATT. Up to 1.8 A (nominal) can be drawn from the
battery; therefore, short thick cables are recommended to
minimize the IR drops. A high current can cause a big IR drop,
and VBATT can be low enough to put the part into UVLO.
INPUT SUPPLIES
AND REGULATORS
OUTPUTS
VDD2 INPUT
SELECTION
AND CURRENT
MEASUREMENT
VDD1 INPUT
CURRENT
MEASUREMENT
LOOP
MEASUREMENT PORT
EN/GPIO SELECTION
FORCED INTERNALLY
OR EXT.
I/OS SIGNALS
AND KELVIN
MEASUREMENTS
07794-026
IF JP1 IS IN INT
POSITION JP4
SELECTS EN/GPIO
TO VDDIO OR GND
REMOVE FILTER
ON VDDA
VDD3 INPUT SELECTION AND
CURRENT MEASUREMENT VDD3 INPUT SOURCE
SELECTION (EXT VDD3 OR +VO1)
Figure 24. Daughterboard

EVAL-ADP5020
Rev. 0 | Page 15 of 24
Quiescent Current Measurement
The ADP5020 has separated supply lines for Buck 1 (VDD1), Buck 2
(VDD2) and LDO (VDD3), in addition to the analog circuit supply
(VDDA). The IDD1 current can be measured using a current loop
across LK12. IDD2 can be measured using a current loop across
JP3 Position 1 to JP3 Position 2. IDD3 can be measured using a
current loop across JP5 Position 1 to JP5 Position 2. IDDA can be
measured using a current loop across JP10. R4 must be removed.
Regulator Switching Nodes
The Buck 1 switching frequency can be measured on TP25 (SW1).
TP21 is a local power ground that can be used to con-nect the
scope probe to minimize the switching noise pickup.
Buck 2 switching frequency can be measured on TP22. TP24 is a
local power ground that can be used to connect the scope probe to
minimize the switching noise pickup.
Kelvin Measurements
The input and output voltages are routed to Connector J6 using
Kelvin connections, meaning that the point of measurement is
directly on the capacitor pads. This minimizes the measurement
error due to IR drop from the trace resistance. Table 2 and Table 3
show the signals available on Connector J6 and Connector J5,
respectively.
Power Board from USB Port Only
To power the board via the USB without using an external
supply, short Jumper LK10 on the motherboard (USB position).
Avoid exceeding the 500 mA current limit of the USB.
Table 2. Measurement Signals on J6
Signal J6 Pins Description
EN/GPIO 20 EN/GPIO pin from IC
VDDIO 19 ADP5020 logic supply
SYNC 18 External frequency
SDA 17 I2C bidirectional line
SCL 16 I2C clock line
XSHTDWN 15 XSHTDN pin from IC
+VO2S, VO2S 14, 13 Buck 2 output voltage (+/−)
+VD2S, −VD2S 12, 11 Buck 2 input voltage (+/−)
+VD1S,−VD1S 10, 9 Buck 1 input voltage (+/−)
+VO3S, −VO3S 8, 7 LDO output voltage (+/−)
+VD3S, −VD3S 6, 5 LDO input voltage (+/−)
+VO1S, −VO1S 4, 3 Buck 1 output voltage (+/−)
GND 2 Ground plane and digital grounds
Table 3. Measurement Signals on J5
Signal J5 Pins Description
VDDA 20 Analog supply input
+VDA, −VDA 19, 13 VDDA input voltage (+/−)
+VO2 18, 17 Buck 2 output positive voltage
−VO2 16, 15 Buck 2 output negative voltage
VDD2 14 Buck 2 input voltage
VDD1A, VDD1B 12, 11 Buck 1 input voltage
+VO3 10, 9 LDO output voltage (+)
−VO3 8 LDO output voltage (−)
−VO1 6, 5 Buck 1 output voltage (−)
+VO1 4, 3 Buck 1 output voltage (+)
VDD3 2 LDO input voltage
GND 7, 1 Ground plane and digital grounds

EVAL-ADP5020
Rev. 0 | Page 16 of 24
EVALUATION BOARD SCHEMATICS
MOTHERBOARD SCHEMATICS
07794-024
USB_VBATT
USB_VDDIO
EXT_VDDIO
EXT_VBATT
D+
D-
EXT_VBOARD
USB_VBOARD
VBATT
VDDIO
VBOARD
VBOARD VBOARD
VBOARD
VBOARD
VBOARD
VBOARD
VBOARD
VBOARD
VBOARD
VBOARD
VDDIO
VDDIO SDA
SCL
VBOARD
+VBB -VBB
+VBK -VBK
+VLDO
-VLDO XSHTDWN
VBATT
VDDIO
EN/GPIO
SYNC
SDA
SCL
AGND
ForceEN
3.68V
1.8V
3.3V
Connectors to Daughterboard
ower Ground & Digital round must be manually onnected in the Layout. his will make initial lacement and routing asier to figure out.
PGNDDGND
URGENT*
1208
Tanya may have a different one than this
Mouser p/ nMouser p/n
JP1
USB-miniB
JP1
USB-miniB
VDD 1
D- 2
D+ 3
ID 4
GND 5
MS1
6MS2
7MS3
8MS4
9
X7
10 X8
11
R15
680
R15
680
C18 2.2uF
C18 2.2uF
R22 100k R22 100k
C17
2.2 uF
C17
2.2 uF
C14 2.2uF
C14 2.2uF
R18
680
R18
680
C19
2.2 uF
C19
2.2 uF
R26 31.6k R26 31.6k
C11 100nF
C11 100nF
C24
2.2 uF
C24
2.2 uF
C16 6.2pF C16 6.2pF
Y1 CRYSTAL24
Y1 CRYSTAL24
1 3
4
2
C27 0.1uF
C27 0.1uF
C10 6.2pF
C10 6.2pF
R20
46.4K46.4K
R20
Input Voltage Sensing Output Voltage
Sensing
Regulators Input
Regulator Outputs
Host Interface
M1
ADP5020_Daughter
Input Voltage Sensing Output Voltage
Sensing
Regulators Input
Regulator Outputs
Host Interface
M1
ADP5020_Daughter
VDD1A
12A VDD1B
11A
VDD2
14A
VDD3
2A
VDDA
20A
VDD_IO
19B
SDA
17B
SCL
16B
EN/GPIO
20B
+VD1S10B
-VD1S9B
+VD2S12B
-VD2S11B
+VD3S6B
-VD3S5B
SYNC
18B
+VDA 19A
-VDA 13A
+VO1A 3A
-VO1A 5A
+VO2A 17A
-VO2A 15A
+VO3A 10A
-VO3 8A
+VO1S 4B
-VO1S 3B
+VO2S 14B
-VO2S 13B
+VO3S 8B
-VO3S 7B
XSHTDWN 15B
FSW1_TP20 1
FSW2_TP25 2
FSW3_TP22 3
AGND 1B
GND1
1A
GND2
7A
+VO3B 9A
GND4
2B
-VO2B 16A
+VO2B 18A
-VO1B 6A
+VO1B 4A
U8
M24AA64-R
U8
A0
A1
A2
VSS SDA
SCL
WP
VCC
R19 100k
R19 100k
U4
CY7C68013A
U4
RDY0/SLRD
1
RDY1/SLWR
2
AVCC1
3
XTALOUT
4
XTALIN
5
AGND1
6
AVCC2
7
D+
8
D-
9
AGND2
10
VCC1
11
GND1
12
IFCLK
13
RES
14
SCL
15
SDA
16
VCC2
17
PB0/FD0
18
PB1/FD1
19
PB2/FD2
20
PB3/FD3
21
PB4/FD4
22
PB5/FD5
23
PB6/FD6
24
PB7/FD7
25
GND2
26
VCC3
27
GND3
28
CTL0 29 CTL1 30
CTL2 31
VCC4 32
PA0/INT1 33 PA1/INT1 34
PA3/*WU2 36
PA4/FIFOADR0 37
PA5/FIFOADR1 38
PA6/*PKTEND 39
PA7/*FLAG 40
GND4 41
RESET 42
PA2/*SLOE 35
VCC543
*WAKEUP 44
PD0/FD8 45
PD1/FD9 46
PD2/FD9 47
PD3/FD10 48
PD4/FD11 49
PD5/FD12 50
PD6/FD13 51
PD7/FD14 52
GND553
CLKOUT 54
VCC655
GND656
PAD PAD
C20
2.2 uF
C20
2.2 uF
C7 0.1uF
C7 0.1uF
C15
2.2 uF
C15
2.2 uF
R27 10k R27 10k
C9 0.1uF
C9 0.1uF
C26 0.1uF
C26 0.1uF
LK8
2 Way Link
LK8
2 Way Link
1 3
2
C8
10uF
C8
10uF
R28 2.2k R28 2.2k
C25 47 uF C25 47 uF
D24 CG0603MLC-05E
652-CG0603MLC-05E
D24 CG0603MLC-05E
652-CG0603MLC-05E
U7
ADP1715/16
U7
ADP1715/16
EN
1IN
2OUT
3ADJ/SS/TRK 4GND4 5
GND3 6
GND2 7
GND1 8
U5
ADP1715/16
U5
ADP1715/16
EN
1IN
2OUT
3ADJ/SS/TRK
4GND4 5
GND3 6
GND2 7
GND1 8
R23
15.4K15.4K
R23 R24
10k R24 10k
D20
LED
D20
LED
D23 CG0603MLC-05E
652-CG0603MLC-05E
D23 CG0603MLC-05E
652-CG0603MLC-05E
LK9 2 Way Link LK9 2 Way Link
1 3
2
C22 0.1uF C22 0.1uF
R29 2.2k R29 2.2k
J10
CON4
J10
CON4
1 2 3 4
C23
2.2 uF
C23
2.2 uF
C21
0.1uF
C21
0.1uF
C28
0.1uF
R16
47
R16
47
U6
ADP1715/16
U6
ADP1715/16
EN
1IN
2OUT
3ADJ/SS/TRK
4GND4 5
GND3 6
GND2 7 GND1 8
D19
LED
D19
LED
R25 10k R25 10k
R21 10k R21 10k
C12 0.1uF C12 0.1uF
C13 100nF C13 100nF
D21
LED
D21
LED
R17 100k
R17 100k
LK10 2 Way Link LK10 2 Way Link
1 3
2
Figure 25. Motherboard Schematic—Main Section

EVAL-ADP5020
Rev. 0 | Page 17 of 24
07794-025
VBOARD
VBOARD
VBOARD
VBOARD
VBOARD
+VBB
+VLDO
+VBK
XSHTDWN
VBOARD
VDDIO
EN/GPIO
VBOARD
SYNC
+VBB -VBB
+VBK -VBK +VLDO -VLO XSHTDWN
AGND
ForceEN
EXT FREQ.
EN = High EN = Low
Buck-Boost ON
LDO ON
Buck ON
XSHTDWN = High
9.6MHz/19.2MHz Ext. Frequency
EN/GPIO = High
+ VOUT_BB - VOUT_BB + VOUT_BK - VOUT_BK
+ VOUT_LDO - VOUT_LDO XSHTDWN
PGND
AGND
R3
680
R3
680
LK12
2 Way Link
LK12
2 Way Link
13
2
R37
10K R37 10K
TP10TP10
1
SM2
CLR
SM2
CLR 2
1
345
D9 LED
D9 LED
LK11
2 Way Link
LK11
2 Way Link
1 3
2
R1
680
R1
680
TP9TP9
1
R30
1M
R30
1M
R13
680
R13
680
C1
10uF
C1
10uF
R34
1M
R34
1M
R31
1M
R31
1M
TP2TP2
1
TP4TP4
1
+
-
U113
ADCMP600
+
-
U113
ADCMP600
3 4
1
5
2
R33
2.2K
R33
2.2K
G
S D
Q3
FDN335N
G
S D
Q3
FDN335N
C2
0.1uF
C2
0.1uF
TP5TP5
1
G
S
D
Q4
FDN335N
G
S
D
Q4
FDN335N
D1
LED
D1
LED
R36
0
R36
0
D22
BAT54TW-7-F
D22
BAT54TW-7-F
A1 1
A2 2
A3 3
K3
4K2
5K1
6
G
S D
Q6
FDN335N
G
S D
Q6
FDN335N
D7 LED
D7 LED
TP3TP3
1
R32 1M R32 1M
R35
1M
R35
1M
C3
10uF
C3
10uF
D5 LED D5 LED
TP6TP6
1
R7 680
R7 680
G
S
D
Q5
FDN335N
G
S
D
Q5
FDN335N
C4
0.1uF
C4
0.1uF
TP7TP7
1
TP8TP8
1
D4
LED
D4
LED
R5 680 R5 680
G
S
D
Q7
FDN335N
G
S
D
Q7
FDN335N
Figure 26. Motherboard Schematic—Interface Section

EVAL-ADP5020
Rev. 0 | Page 18 of 24
DAUGHTERBOARD SCHEMATIC
07794-027
XSHTDWN
+VO1 +VO1
+VO2
+VO2S
+VO3
VDDA
VDD1A
+VO1S
-VO1S
+VO2
-VO2S
VDD1B
VDD2
VDD3
+VD1S
-VD1S
SDA
SCL SYNC
EN/GPIO
+VD2S
-VD2S
VDDIO
-VO1 -VO1
-VO2
-VO2
-VO3
+VD3S
+VDA
-VDA
-VD3S
+VO1
+VO2
+VO1
+VO3
-VO3 -VO1
-VO1
-VO2
-VD1S
EN/GPIO SYNC
VDDIO
VDDA
VDD2
VDD1A VDD1B
VDD3
+VDA
+VO2S
-VO2S
+VO1S
-VO1S
XSHTDWN
-VO3S +VO3S
SDA SCL
+VD1S
-VO3S
+VO3S
-VD3S +VD3S
+VD2S
-VD2S
-VDA
+VO2
-VO2
+VO3
TP5TP5
1
TP20TP20
1
C6
2.2UF
C6
2.2UF
C1110UFC1110UF
TP3 TP3
1
LK12LK12
12
R2
10K
R2
10K
L2 2.2uHL2 2.2uH
BUCK1BUCK2LDO
U1
ADP5020_LFCSP
BUCK1BUCK2LDO
U1
ADP5020_LFCSP
VOUT1A 15
SW1 17
PGND1 16
VOUT1B 14
SW2 20
VOUT2 2
PGND2 1
VANA 12
XSHTDWN 10
AGND
4
DGND
6
VDDA
3
VDD1
18
VDD2
19
VDD3
13
VDD_IO
9
SDA
7
SCL
8
SYNC
5
EN/GPIO
11
J5
HEADER 10X2
J5
HEADER 10X2
2
4
6
8
10
12
14 16
18
20
1
3
5
7
9
11
13
15
17
19
JP1
INTF
JP1
INTF
11
22
33
C3 4.7UF
C3 4.7UF
JP3
INTF
JP3
INTF
11 22
33
L3 2.2uHL3 2.2uH
L1 2.2uH
L1 2.2uH
C4 1UF C4 1UF
R5
49.9
R5
49.9
R1
10K
R1
10K
C8 1UF C8 1UF
LK10LK10
12
TP25TP25
1
LK13LK13
12
C2 10UF C2 10UF
JP5 INTF
JP5 INTF
1
12
23
3
TP4TP4
1
TP24 TP24
1
TP21TP21
1
C9
1UF1UF
C9
R4
10
R4
10
JP4 INTF JP4 INTF
11
22
33
J6
HEADER 10X2
J6
HEADER 10X2
2 4
6
8
10
12
14
16
18
20
1
3
5
7
9
11 13
15
17 19
C7
2.2UF
C7
2.2UF
C5
10UF
C5
10UF
LK15 LK15
12
C10
1UF
TP22TP22
1
Figure 27. Daughterboard Schematic

EVAL-ADP5020
Rev. 0 | Page 19 of 24
PCB LAYOUT
Evaluation Board Layout
07794-028
Figure 28. Top Layer
07794-029
Figure 29. Inner Layer 1
07794-030
Figure 30. Inner Layer 2
07794-031
Figure 31. Bottom Layer

EVAL-ADP5020
Rev. 0 | Page 20 of 24
Motherboard Layout
07794-032
Figure 32. Top Layer
07794-033
Figure 33. Inner Layer 1
07794-034
Figure 34. Inner Layer 2
07794-035
Figure 35. Bottom Layer