Analog Devices ADV7610 Installation manual

Hardware User Guide
UG-438
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Advantiv ADV7610 HDMI Receiver Functionality and Features
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 184
SCOPE
This user guide provides a detailed description of the Advantiv® ADV7610 HDMI® receiver functionality and features.
DISCLAIMER
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
ADV7610
DPLL
CEC
CONTROLLER
5V DETECT
AND HPD
CONTROLLER
CONTROL
INTERFACE
I
2
C
XTALP P0 TO P7
P8 TO P15
I2S0 TO I2S3
P16 TO P23
LLC
LRCLK
SCLK/INT2*
MCLK/INT2*
HS
VS/FIELD/ALSB
DE
INT1
INT2*
XTALN
RXA_5V
HPA_A/INT2*
EDID
REPEATER
CONTROLLER
PLL
EQUALIZER EQUALIZER HDCP
ENGINE
HDCP
EEPROM DATA
PREPROCESSOR
AND COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
BACKEND
COLOR SPACE
CONVERSION
PACKET
PROCESSOR
PACKET/
INFOFRAME
MEMORY
HDMI
PROCESSOR
DDCA_SDA
DDCA_SCL
RXA_0±
RXA_2±
RXA_1±
SCL
SDA
CEC
RXA_C±
CONTROL
AND DATA
A
B
C
AUDIO OUTPUT FORMATTER OUTPUT FORMATTER
INTERRUPT
CONTROLLER
(INT1, INT2)
*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2.
AUDIO
PROCESSOR
MUTE
12
12
12
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TABLE OF CONTENTS
Scope .................................................................................................. 1
Disclaimer.......................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Using the ADV7610 Hardware User Guide .................................. 4
Number Notations........................................................................ 4
Register Access Conventions ...................................................... 4
Acronyms and Abbreviations ..................................................... 4
Field Function Descriptions........................................................ 6
References...................................................................................... 6
Introduction to the ADV7610 ........................................................ 7
HDMI Receiver............................................................................. 7
Component Processor ................................................................. 7
Main Features of ADV7610 ........................................................ 7
Pin Configuration and Function Descriptions......................... 9
Global Control Registers ............................................................... 11
ADV7610 Revision Identification............................................ 11
Power-Down Controls ............................................................... 11
Global Pin Control ..................................................................... 13
Primary Mode and Video Standard ............................................. 18
Primary Mode and Video Standard Controls......................... 18
HDMI Decimation Modes ........................................................ 20
Primary Mode and Video Standard Configuration for HDMI
Free Run....................................................................................... 20
Recommended Settings for HDMI Inputs.............................. 21
Pixel Port Configuration................................................................ 23
Pixel Port Output Modes........................................................... 23
LLC Controls............................................................................... 24
DLL on LLC Clock Path ............................................................ 24
HDMI Receiver............................................................................... 26
+5 V Cable Detect ...................................................................... 26
Hot Plug Assert........................................................................... 27
E-EDID/Repeater Controller.................................................... 29
E-EDID Data Configuration..................................................... 29
Transitioning of Power Modes.................................................. 30
Structure of Internal E-EDID ................................................... 30
TMDS Equalization.................................................................... 31
Port Selection .............................................................................. 31
TMDS Clock Activity Detection .............................................. 31
HDMI/DVI Status Bits .............................................................. 32
Video 3D Detection ................................................................... 32
TMDS Measurement.................................................................. 33
Deep Color Mode Support........................................................ 34
Video FIFO.................................................................................. 34
Pixel Repetition .......................................................................... 36
HDCP Support ........................................................................... 37
HDMI Synchronization Parameters ........................................ 41
Audio Control and Configuration ........................................... 46
Audio FIFO ................................................................................. 48
Audio Packet Type Flags ........................................................... 49
Audio Output Interface ............................................................. 51
MCLKOUT Setting .................................................................... 57
Audio Channel Mode ................................................................ 57
Audio Muting.............................................................................. 58
Audio Clock Regeneration Parameters ................................... 62
Channel Status ............................................................................ 63
Packets and InfoFrames Registers............................................ 67
Packet Registers .......................................................................... 74
Customizing Packet/InfoFrame Storage Registers................. 78
Repeater Support........................................................................ 79
Interface to DPP Section ........................................................... 86
Pass Through Mode ................................................................... 87
Color Space Information Sent to the DPP and CP Sections 88
Status Registers ........................................................................... 88
HDMI Section Reset Strategy................................................... 91
HDMI Packet Detection Flag Reset......................................... 91
Data Preprocessor and Color Space Conversion and Color
Controls ........................................................................................... 92
Color Space Conversion Matrix ............................................... 92
Color Controls .......................................................................... 101
Component Processor ................................................................. 103
Introduction to the Component Processor........................... 103
Clamp Operation...................................................................... 103
CP Gain Operation .................................................................. 105
CP Offset Block ........................................................................ 109
AV Code Block ......................................................................... 110
CP Data Path for HDMI Modes............................................. 112
Sync Processed by CP Section ................................................ 115
CP Output Synchronization Signal Positioning................... 122
CP HDMI Controls.................................................................. 134

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Free Run Mode ......................................................................... 134
CP Status ................................................................................... 138
CP Core Bypassing .................................................................... 138
Consumer Electronics Control................................................... 139
Main Controls........................................................................... 139
CEC Transmit Section ............................................................. 140
CEC Receive Section................................................................ 142
Antiglitch Filter Module.......................................................... 147
Typical Operation Flow........................................................... 148
Low Power CEC Message Monitoring .................................. 151
Interrupts....................................................................................... 153
Interrupt Architecture Overview ........................................... 153
Interrupt Pins............................................................................ 156
Description of Interrupt Bits .................................................. 159
Additional Explanations.......................................................... 160
Register Access and Serial Ports Description............................174
Main I2C Port.............................................................................174
DDC Ports..................................................................................177
Appendix A ....................................................................................178
PCB Layout Recommendations ..............................................178
Power Supply Bypassing...........................................................178
Digital Outputs (Data and Clocks).........................................178
Digital Inputs.............................................................................179
XTAL and Load Cap Value Selection.....................................179
Appendix B ....................................................................................180
Recommended Unused Pin Configurations .........................180
Appendix C ....................................................................................182
Pixel Output Formats ...............................................................182
REVISION HISTORY
2/13—Revision 0: Initial Version

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USING THE ADV7610 HARDWARE USER GUIDE
NUMBER NOTATIONS
Table 1.
Notation Description
Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V).
0xNN Hexadecimal (base-16) numbers are preceded by the prefix‘0x’.
0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’.
NN Decimal (base-10) are represented using no additional prefixes or suffixes.
REGISTER ACCESS CONVENTIONS
Table 2.
Mode Description
R/W
Memory location has read and write access.
R Memory location is read access only. A read always returns 0 unless otherwise specified.
W Memory location is write access only.
ACRONYMS AND ABBREVIATIONS
Table 3.
Acronym/Abbreviation Description
ACP Audio content protection.
AGC Automatic gain control.
Ainfo HDCP register. Refer to digital content protection documentation in the References section.
AKSV HDCP transmitter key selection vector. Refer to digital content protection documentation in the References section.
An 64-bit pseudo-random value generated by HDCP cipher function of Device A.
AP Audio output pin.
AVI Auxiliary video information.
BCAPS HDCP register. Refer to digital content protection documentation in the References section.
BKSV HDCP receiver key selection vector. Refer to digital content protection documentation in the References section.
CP Component processor.
CSC
Color space converter/conversion.
DDR Double data rate.
DE Data enable.
DLL Delay locked loop.
DPP Data preprocessor.
DVI Digital visual interface.
EAV End of active video.
EMC Electromagnetic compatibility.
EQ Equalizer.
HD
High definition.
HDCP High bandwidth digital content protection.
HDMI High bandwidth multimedia interface.
HDTV High definition television.
HPA Hot plug assert.
HPD Hot plug detect.
HSync Horizontal synchronization.
IC Integrated circuit.
ISRC International standard recording code.
I2S Inter IC sound.
I2C Inter integrated circuit.

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Acronym/Abbreviation Description
KSV Key selection vector.
LLC Line locked clock.
LSB Least significant bit.
L-PCM Linear pulse coded modulated.
Mbps
Megabit per second.
MPEG Moving picture expert group.
ms Millisecond.
MSB Most significant bit.
NC No connect.
OTP One-time programmable.
Pj’ HDCP enhanced link verification response. Refer to digital content protection documentation in the References section.
Ri’ HDCP link verification response. Refer to digital content protection documentation in the References section.
Rx Receiver.
SAV Start of active video.
SDR Single data rate.
SHA-1 Refer to HDCP documentation.
SMPTE Society of Motion Picture and Television Engineers.
SOG Sync on green.
SOY Sync on Y.
SPA Source physical address.
SPD Source production descriptor.
STDI
Standard detection and identification.
TMDS Transition minimized differential signaling.
Tx Transmitter.
VBI Video blanking interval.
VSync Vertical synchronization.
XTAL Crystal oscillator.

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FIELD FUNCTION DESCRIPTIONS
Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit
name, a short function description, the I2C map, the register location within the I2C map, and a detailed description of the field.
The detailed description consists of:
•For a readable field, the values the field can take
•For a writable field, the values the field can be set to
Example Field Function Description
This section provides an example of a field function table followed by a description of each part of the table.
PRIM_MODE[3:0], IO Map, Address 0x01[3:0].
A control to select the primary mode of operation of the decoder.
Function
PRIM_MODE[3:0] Description
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Reserved
0101 HDMI-Comp
0110 (default) HDMI-GR
0111 to 1111 Reserved
In this example
•The name of the field is PRIM_MODE and it is four bit long.
•Address 0x01 is the I2C location of the field in big endian format (MSB first, LSB last).
•The address is followed by a detailed description of the field.
•The first column of the table lists values the field can take or can be set to. These values are in binary format if not preceded by 0x or
in hexadecimal format if preceded by 0x.
•The second column describes the function of each field for each value the field can take or can be set to. Values are in binary format.
REFERENCES
CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006.
Digital Content Protection (DCP) LLC, High-Bandwidth Digital Content Protection System, Revision 1.4, July 8, 2009.
HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010.
ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating
at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998.

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INTRODUCTION TO THE ADV7610
The ADV7610 is a high quality, single input, high definition multimedia interface (HDMI®) receiver. It incorporates an HDMI receiver
that supports all mandatory HDMI 1.4a 3D TV formats up to 1080 p60@8-bit. It integrates a CEC controller that supports the capability
discovery and control (CDC) feature.
The ADV7610 has an audio output port for the audio data extracted from the HDMI stream. The receiver has an advanced mute
controller that prevents audible extraneous noise in the audio output.
Fabricated in an advanced CMOS process, the ADV7610 is provided in a 6 mm × 6 mm, 76-ball surface-mount chip-scale package BGA,
RoHS-compliant package and is specified over the −40°C to +85°C temperature range.
HDMI RECEIVER
The ADV7610 HDMI receiver incorporates equalization of the HDMI data signals to compensate for the losses inherent in HDMI and
DVI cabling, especially at longer lengths and higher frequencies. The equalizer is highly effective and is capable of equalizing for long
cables to achieve robust receiver performance.
With the inclusion of high-bandwidth digital content protection (HDCP), displays can receive encrypted video content. The HDMI
interface of the ADV7610 allows a video receiver to authenticate, decrypt encoded data and renew that authentication during
transmission, as specified by the HDCP v1.4 protocol.
The ADV7610 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including super
audio CD (SACD) via direct stream digital (DSD and high bit rate (HBR) are supported by the ADV7610. The HDMI receiver has
advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output.
COMPONENT PROCESSOR
The component processor (CP) is located behind the HDMI receiver. It processes the video data received from the HDMI receiver. The
CP section provides color adjustment features, such as brightness, saturation, and hue. The color space conversion (CSC) matrix allows
the color space to be changed as required. The standard detection and identification (STDI) block allows the detection of video timings.
MAIN FEATURES OF ADV7610
HDMI Receiver
•HDMI 1.4a features supported
•3D HDMI 1.4a video format support
•Full colorimetry, including sYCC601, Adobe RGB, Adobe YCC601, and xvYCC extended gamut color
•CEC 1.4-compatible
•HDCP v1.4-compliant receiver
•Supports all display resolutions up to UXGA 60 Hz 8-bit
•Supports multichannel audio with sampling frequency up to 192 kHz
•Programmable front-end equalization for long cable lengths
•Audio mute for removing extraneous noise
•Programmable interrupt generator to detect HDMI packets
•Internal EDID support
•Repeater support
Component Video Processing
•An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb
•Provides color controls, such as saturation, brightness, hue, and contrast
•STDI block that enables format detection
•Free run output mode provides stable timing when no video input is present

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Video Output Formats
•Double data rate (DDR) 8-/12-bit 4:2:2 YCrCb.
•DDR supported only up to 50 MHz (an equivalent to data rate clocked with 100 MHz clock in SDR mode)
•Pseudo DDR (CCIR-656 type stream) 8-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P
•SDR 16-/24-bit 4:2:2 YCrCb for all standards
•SDR 24-bit 4:4:4 YCrCb/RGB for all HDMI standards
•DDR 24-bit 4:4:4 RGB
Additional Features
•HS, VS, FIELD, and DE output signals with programmable position, polarity, and width
•Numerous interrupt sources available for the INT1 and INT2 interrupt request output pins, available via one of the selected pins, that
is, SCLK/INT2, MCLK/INT2, or HPA_A/INT2
•Temperature range of −40°C to +85°C
•6 mm × 6 mm, 76-ball surface-mount chip-scale package BGA

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Ball No. Mnemonic Type Description
D4, D5, D6, E4,
F4, G4, G5, G6
GND Ground Ground.
A1 HPA_A/INT2 Miscellaneous digital A dual function pin that can be configured to output a hot plug assert signal (for
HDMI Port A) or an Interrupt 2 signal.
G1, G2 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
B1, B2 TVDD Power Terminator Supply Voltage (3.3 V).
F7, G7, J10, K10 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
A10, B10, D7, E7
DVDD
Power
Digital Core Supply Voltage (1.8 V).
A4 PVDD Power PLL Supply Voltage (1.8 V).
C2 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface.
C1 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface.
D2 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface.
D1 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface.
E2 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface.
E1 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.
F2 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
F1 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface.
H1 P23 Digital video output Video Pixel Output Port.
H2 P22 Digital video output Video Pixel Output Port.
A
B
C
D
E
F
G
J
H
K
1 3 458910
267
HPA_A/
INT2 DDCA_SCL PVDD XTALN MCLK/
INT2 SCLK/
INT2 DVDD
RXA_5V XTALP INT1
TVDD DDCA_SDA CEC CS SCL LRCLK DVDD
TVDD RESET SDA
RXA_C+ I2S3 I2S1
RXA_C–
RXA_0+ GND GND I2S2 I2S0
RXA_0– GND DVDD
RXA_1+ GND VS/
FIELD/
ALSB DE
RXA_1– DVDD
RXA_2+ GND HS P0
RXA_2– DVDDIO
CVDD GND GND P1 P2
CVDD GND DVDDIO
P23 P3 P4
P22
P21 P16 P15 P13 P7 P5 DVDDIO
P18 P11 P9
P20 P17 LLC P14 P8 P6 DVDDIO
P19 P12 P10
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Ball No. Mnemonic Type Description
J1 P21 Digital video output Video Pixel Output Port.
K1 P20 Digital video output Video Pixel Output Port.
K2 P19 Digital video output Video Pixel Output Port.
J2 P18 Digital video output Video Pixel Output Port.
K3
P17
Digital video output
Video Pixel Output Port.
J3 P16 Digital video output Video Pixel Output Port.
K4 LLC Digital video output Line-Locked Output Clock for the Pixel Data (Range = 13.5 MHz to 162.5 MHz).
J4 P15 Digital video output Video Pixel Output Port.
K5 P14 Digital video output Video Pixel Output Port.
J5 P13 Digital video output Video Pixel Output Port.
K6 P12 Digital video output Video Pixel Output Port.
J6 P11 Digital video output Video Pixel Output Port.
K7 P10 Digital video output Video Pixel Output Port.
J7 P9 Digital video output Video Pixel Output Port.
K8
P8
Digital video output
Video Pixel Output Port.
J8 P7 Digital video output Video Pixel Output Port.
K9 P6 Digital video output Video Pixel Output Port.
J9 P5 Digital video output Video Pixel Output Port.
H10 P4 Digital video output Video Pixel Output Port.
H9
P3
Digital video output
Video Pixel Output Port.
G10 P2 Digital video output Video Pixel Output Port.
G9 P1 Digital video output Video Pixel Output Port.
F10 P0 Digital video output Video Pixel Output Port.
E10 DE Miscellaneous digital Data enable (DE) is a signal that indicates active pixel data.
F9 HS Digital video output Horizontal Synchronization Output Signal.
E9 VS/FIELD/ALSB Digital input/output Vertical Synchronization Output Signal. FIELD is a field synchronization output
signal in all interlaced video modes. VS or FIELD can be configured for this pin.
The ALSB allows selection of the I2C address.
D10, C10,
D9, C9
I2S0 to I2S3 Miscellaneous digital Audio Output Pins. Pins can be configured to output S/PDIF digital audio output
(S/PDIF) or I2S.
A9 SCLK/INT2 Miscellaneous digital A dual function pin that can be configured to output an audio serial clock or an
Interrupt 2 signal.
B9 LRCLK Miscellaneous digital Audio Left/Right Clock.
A8 MCLK/INT2 Miscellaneous digital A dual function pin that can be configured to output an audio master clock or an
Interrupt 2 signal.
B8 SCL Miscellaneous digital I2C Port Serial Clock Input Pin. SCL is the clock line for the control port.
B7
SDA
Miscellaneous digital
I
2
C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
A7 INT1 Miscellaneous digital Interrupt. This pin can be active low or active high. When status bits change, this
pin is triggered. The events that trigger an interrupt are under user configuration.
B6 RESET Miscellaneous digital System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7610 circuitry.
A6 XTALP Miscellaneous
analog
Input Pin for a 28.63636 MHz Crystal, or an External 1.8 V, 28.63636 MHz Clock
Oscillator Source to Clock the ADV7610.
A5 XTALN Miscellaneous
analog
Crystal Input. Input pin for 28.63636 MHz crystal.
B4 CEC Digital input/output Consumer Electronic Control Channel.
B5 CS Miscellaneous digital Chip Select. Pulling this line up causes I2C state machine to ignore I2C transmission.
A3
DDCA_SCL
HDMI input
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
B3 DDCA_SDA HDMI input HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
A2 RXA_5V HDMI input 5 V Detect Pin for Port A in the HDMI Interface.