Analog Devices ADV7610 Installation manual

Hardware User Guide
UG-438
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Advantiv ADV7610 HDMI Receiver Functionality and Features
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.Rev. 0 | Page 1 of 184
SCOPE
This user guide provides a detailed description of the Advantiv® ADV7610 HDMI® receiver functionality and features.
DISCLAIMER
Information furnished by Analog Devices, Inc., is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use.
Specifications are subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
ADV7610
DPLL
CEC
CONTROLLER
5V DETECT
AND HPD
CONTROLLER
CONTROL
INTERFACE
I
2
C
XTALP P0 TO P7
P8 TO P15
I2S0 TO I2S3
P16 TO P23
LLC
LRCLK
SCLK/INT2*
MCLK/INT2*
HS
VS/FIELD/ALSB
DE
INT1
INT2*
XTALN
RXA_5V
HPA_A/INT2*
EDID
REPEATER
CONTROLLER
PLL
EQUALIZER EQUALIZER HDCP
ENGINE
HDCP
EEPROM DATA
PREPROCESSOR
AND COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
BACKEND
COLOR SPACE
CONVERSION
PACKET
PROCESSOR
PACKET/
INFOFRAME
MEMORY
HDMI
PROCESSOR
DDCA_SDA
DDCA_SCL
RXA_0±
RXA_2±
RXA_1±
SCL
SDA
CEC
RXA_C±
CONTROL
AND DATA
A
B
C
AUDIO OUTPUT FORMATTER OUTPUT FORMATTER
INTERRUPT
CONTROLLER
(INT1, INT2)
*INT2 CAN BE ONLY OUTPUT ON ONE OF THE PINS: SCLK/INT2, MCLK/INT2, OR HPA_A/INT2.
AUDIO
PROCESSOR
MUTE
12
12
12
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TABLE OF CONTENTS
Scope .................................................................................................. 1
Disclaimer.......................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Using the ADV7610 Hardware User Guide .................................. 4
Number Notations........................................................................ 4
Register Access Conventions ...................................................... 4
Acronyms and Abbreviations ..................................................... 4
Field Function Descriptions........................................................ 6
References...................................................................................... 6
Introduction to the ADV7610 ........................................................ 7
HDMI Receiver............................................................................. 7
Component Processor ................................................................. 7
Main Features of ADV7610 ........................................................ 7
Pin Configuration and Function Descriptions......................... 9
Global Control Registers ............................................................... 11
ADV7610 Revision Identification............................................ 11
Power-Down Controls ............................................................... 11
Global Pin Control ..................................................................... 13
Primary Mode and Video Standard ............................................. 18
Primary Mode and Video Standard Controls......................... 18
HDMI Decimation Modes ........................................................ 20
Primary Mode and Video Standard Configuration for HDMI
Free Run....................................................................................... 20
Recommended Settings for HDMI Inputs.............................. 21
Pixel Port Configuration................................................................ 23
Pixel Port Output Modes........................................................... 23
LLC Controls............................................................................... 24
DLL on LLC Clock Path ............................................................ 24
HDMI Receiver............................................................................... 26
+5 V Cable Detect ...................................................................... 26
Hot Plug Assert........................................................................... 27
E-EDID/Repeater Controller.................................................... 29
E-EDID Data Configuration..................................................... 29
Transitioning of Power Modes.................................................. 30
Structure of Internal E-EDID ................................................... 30
TMDS Equalization.................................................................... 31
Port Selection .............................................................................. 31
TMDS Clock Activity Detection .............................................. 31
HDMI/DVI Status Bits .............................................................. 32
Video 3D Detection ................................................................... 32
TMDS Measurement.................................................................. 33
Deep Color Mode Support........................................................ 34
Video FIFO.................................................................................. 34
Pixel Repetition .......................................................................... 36
HDCP Support ........................................................................... 37
HDMI Synchronization Parameters ........................................ 41
Audio Control and Configuration ........................................... 46
Audio FIFO ................................................................................. 48
Audio Packet Type Flags ........................................................... 49
Audio Output Interface ............................................................. 51
MCLKOUT Setting .................................................................... 57
Audio Channel Mode ................................................................ 57
Audio Muting.............................................................................. 58
Audio Clock Regeneration Parameters ................................... 62
Channel Status ............................................................................ 63
Packets and InfoFrames Registers............................................ 67
Packet Registers .......................................................................... 74
Customizing Packet/InfoFrame Storage Registers................. 78
Repeater Support........................................................................ 79
Interface to DPP Section ........................................................... 86
Pass Through Mode ................................................................... 87
Color Space Information Sent to the DPP and CP Sections 88
Status Registers ........................................................................... 88
HDMI Section Reset Strategy................................................... 91
HDMI Packet Detection Flag Reset......................................... 91
Data Preprocessor and Color Space Conversion and Color
Controls ........................................................................................... 92
Color Space Conversion Matrix ............................................... 92
Color Controls .......................................................................... 101
Component Processor ................................................................. 103
Introduction to the Component Processor........................... 103
Clamp Operation...................................................................... 103
CP Gain Operation .................................................................. 105
CP Offset Block ........................................................................ 109
AV Code Block ......................................................................... 110
CP Data Path for HDMI Modes............................................. 112
Sync Processed by CP Section ................................................ 115
CP Output Synchronization Signal Positioning................... 122
CP HDMI Controls.................................................................. 134

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Free Run Mode ......................................................................... 134
CP Status ................................................................................... 138
CP Core Bypassing .................................................................... 138
Consumer Electronics Control................................................... 139
Main Controls........................................................................... 139
CEC Transmit Section ............................................................. 140
CEC Receive Section................................................................ 142
Antiglitch Filter Module.......................................................... 147
Typical Operation Flow........................................................... 148
Low Power CEC Message Monitoring .................................. 151
Interrupts....................................................................................... 153
Interrupt Architecture Overview ........................................... 153
Interrupt Pins............................................................................ 156
Description of Interrupt Bits .................................................. 159
Additional Explanations.......................................................... 160
Register Access and Serial Ports Description............................174
Main I2C Port.............................................................................174
DDC Ports..................................................................................177
Appendix A ....................................................................................178
PCB Layout Recommendations ..............................................178
Power Supply Bypassing...........................................................178
Digital Outputs (Data and Clocks).........................................178
Digital Inputs.............................................................................179
XTAL and Load Cap Value Selection.....................................179
Appendix B ....................................................................................180
Recommended Unused Pin Configurations .........................180
Appendix C ....................................................................................182
Pixel Output Formats ...............................................................182
REVISION HISTORY
2/13—Revision 0: Initial Version

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USING THE ADV7610 HARDWARE USER GUIDE
NUMBER NOTATIONS
Table 1.
Notation Description
Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V).
0xNN Hexadecimal (base-16) numbers are preceded by the prefix‘0x’.
0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’.
NN Decimal (base-10) are represented using no additional prefixes or suffixes.
REGISTER ACCESS CONVENTIONS
Table 2.
Mode Description
R/W
Memory location has read and write access.
R Memory location is read access only. A read always returns 0 unless otherwise specified.
W Memory location is write access only.
ACRONYMS AND ABBREVIATIONS
Table 3.
Acronym/Abbreviation Description
ACP Audio content protection.
AGC Automatic gain control.
Ainfo HDCP register. Refer to digital content protection documentation in the References section.
AKSV HDCP transmitter key selection vector. Refer to digital content protection documentation in the References section.
An 64-bit pseudo-random value generated by HDCP cipher function of Device A.
AP Audio output pin.
AVI Auxiliary video information.
BCAPS HDCP register. Refer to digital content protection documentation in the References section.
BKSV HDCP receiver key selection vector. Refer to digital content protection documentation in the References section.
CP Component processor.
CSC
Color space converter/conversion.
DDR Double data rate.
DE Data enable.
DLL Delay locked loop.
DPP Data preprocessor.
DVI Digital visual interface.
EAV End of active video.
EMC Electromagnetic compatibility.
EQ Equalizer.
HD
High definition.
HDCP High bandwidth digital content protection.
HDMI High bandwidth multimedia interface.
HDTV High definition television.
HPA Hot plug assert.
HPD Hot plug detect.
HSync Horizontal synchronization.
IC Integrated circuit.
ISRC International standard recording code.
I2S Inter IC sound.
I2C Inter integrated circuit.

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Acronym/Abbreviation Description
KSV Key selection vector.
LLC Line locked clock.
LSB Least significant bit.
L-PCM Linear pulse coded modulated.
Mbps
Megabit per second.
MPEG Moving picture expert group.
ms Millisecond.
MSB Most significant bit.
NC No connect.
OTP One-time programmable.
Pj’ HDCP enhanced link verification response. Refer to digital content protection documentation in the References section.
Ri’ HDCP link verification response. Refer to digital content protection documentation in the References section.
Rx Receiver.
SAV Start of active video.
SDR Single data rate.
SHA-1 Refer to HDCP documentation.
SMPTE Society of Motion Picture and Television Engineers.
SOG Sync on green.
SOY Sync on Y.
SPA Source physical address.
SPD Source production descriptor.
STDI
Standard detection and identification.
TMDS Transition minimized differential signaling.
Tx Transmitter.
VBI Video blanking interval.
VSync Vertical synchronization.
XTAL Crystal oscillator.

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FIELD FUNCTION DESCRIPTIONS
Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit
name, a short function description, the I2C map, the register location within the I2C map, and a detailed description of the field.
The detailed description consists of:
•For a readable field, the values the field can take
•For a writable field, the values the field can be set to
Example Field Function Description
This section provides an example of a field function table followed by a description of each part of the table.
PRIM_MODE[3:0], IO Map, Address 0x01[3:0].
A control to select the primary mode of operation of the decoder.
Function
PRIM_MODE[3:0] Description
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Reserved
0101 HDMI-Comp
0110 (default) HDMI-GR
0111 to 1111 Reserved
In this example
•The name of the field is PRIM_MODE and it is four bit long.
•Address 0x01 is the I2C location of the field in big endian format (MSB first, LSB last).
•The address is followed by a detailed description of the field.
•The first column of the table lists values the field can take or can be set to. These values are in binary format if not preceded by 0x or
in hexadecimal format if preceded by 0x.
•The second column describes the function of each field for each value the field can take or can be set to. Values are in binary format.
REFERENCES
CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006.
Digital Content Protection (DCP) LLC, High-Bandwidth Digital Content Protection System, Revision 1.4, July 8, 2009.
HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010.
ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating
at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998.

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INTRODUCTION TO THE ADV7610
The ADV7610 is a high quality, single input, high definition multimedia interface (HDMI®) receiver. It incorporates an HDMI receiver
that supports all mandatory HDMI 1.4a 3D TV formats up to 1080 p60@8-bit. It integrates a CEC controller that supports the capability
discovery and control (CDC) feature.
The ADV7610 has an audio output port for the audio data extracted from the HDMI stream. The receiver has an advanced mute
controller that prevents audible extraneous noise in the audio output.
Fabricated in an advanced CMOS process, the ADV7610 is provided in a 6 mm × 6 mm, 76-ball surface-mount chip-scale package BGA,
RoHS-compliant package and is specified over the −40°C to +85°C temperature range.
HDMI RECEIVER
The ADV7610 HDMI receiver incorporates equalization of the HDMI data signals to compensate for the losses inherent in HDMI and
DVI cabling, especially at longer lengths and higher frequencies. The equalizer is highly effective and is capable of equalizing for long
cables to achieve robust receiver performance.
With the inclusion of high-bandwidth digital content protection (HDCP), displays can receive encrypted video content. The HDMI
interface of the ADV7610 allows a video receiver to authenticate, decrypt encoded data and renew that authentication during
transmission, as specified by the HDCP v1.4 protocol.
The ADV7610 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including super
audio CD (SACD) via direct stream digital (DSD and high bit rate (HBR) are supported by the ADV7610. The HDMI receiver has
advanced audio functionality, such as a mute controller, that prevents audible extraneous noise in the audio output.
COMPONENT PROCESSOR
The component processor (CP) is located behind the HDMI receiver. It processes the video data received from the HDMI receiver. The
CP section provides color adjustment features, such as brightness, saturation, and hue. The color space conversion (CSC) matrix allows
the color space to be changed as required. The standard detection and identification (STDI) block allows the detection of video timings.
MAIN FEATURES OF ADV7610
HDMI Receiver
•HDMI 1.4a features supported
•3D HDMI 1.4a video format support
•Full colorimetry, including sYCC601, Adobe RGB, Adobe YCC601, and xvYCC extended gamut color
•CEC 1.4-compatible
•HDCP v1.4-compliant receiver
•Supports all display resolutions up to UXGA 60 Hz 8-bit
•Supports multichannel audio with sampling frequency up to 192 kHz
•Programmable front-end equalization for long cable lengths
•Audio mute for removing extraneous noise
•Programmable interrupt generator to detect HDMI packets
•Internal EDID support
•Repeater support
Component Video Processing
•An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb
•Provides color controls, such as saturation, brightness, hue, and contrast
•STDI block that enables format detection
•Free run output mode provides stable timing when no video input is present

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Video Output Formats
•Double data rate (DDR) 8-/12-bit 4:2:2 YCrCb.
•DDR supported only up to 50 MHz (an equivalent to data rate clocked with 100 MHz clock in SDR mode)
•Pseudo DDR (CCIR-656 type stream) 8-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P
•SDR 16-/24-bit 4:2:2 YCrCb for all standards
•SDR 24-bit 4:4:4 YCrCb/RGB for all HDMI standards
•DDR 24-bit 4:4:4 RGB
Additional Features
•HS, VS, FIELD, and DE output signals with programmable position, polarity, and width
•Numerous interrupt sources available for the INT1 and INT2 interrupt request output pins, available via one of the selected pins, that
is, SCLK/INT2, MCLK/INT2, or HPA_A/INT2
•Temperature range of −40°C to +85°C
•6 mm × 6 mm, 76-ball surface-mount chip-scale package BGA

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Ball No. Mnemonic Type Description
D4, D5, D6, E4,
F4, G4, G5, G6
GND Ground Ground.
A1 HPA_A/INT2 Miscellaneous digital A dual function pin that can be configured to output a hot plug assert signal (for
HDMI Port A) or an Interrupt 2 signal.
G1, G2 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
B1, B2 TVDD Power Terminator Supply Voltage (3.3 V).
F7, G7, J10, K10 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
A10, B10, D7, E7
DVDD
Power
Digital Core Supply Voltage (1.8 V).
A4 PVDD Power PLL Supply Voltage (1.8 V).
C2 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface.
C1 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface.
D2 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface.
D1 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface.
E2 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface.
E1 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.
F2 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
F1 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface.
H1 P23 Digital video output Video Pixel Output Port.
H2 P22 Digital video output Video Pixel Output Port.
A
B
C
D
E
F
G
J
H
K
1 3 458910
267
HPA_A/
INT2 DDCA_SCL PVDD XTALN MCLK/
INT2 SCLK/
INT2 DVDD
RXA_5V XTALP INT1
TVDD DDCA_SDA CEC CS SCL LRCLK DVDD
TVDD RESET SDA
RXA_C+ I2S3 I2S1
RXA_C–
RXA_0+ GND GND I2S2 I2S0
RXA_0– GND DVDD
RXA_1+ GND VS/
FIELD/
ALSB DE
RXA_1– DVDD
RXA_2+ GND HS P0
RXA_2– DVDDIO
CVDD GND GND P1 P2
CVDD GND DVDDIO
P23 P3 P4
P22
P21 P16 P15 P13 P7 P5 DVDDIO
P18 P11 P9
P20 P17 LLC P14 P8 P6 DVDDIO
P19 P12 P10
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Ball No. Mnemonic Type Description
J1 P21 Digital video output Video Pixel Output Port.
K1 P20 Digital video output Video Pixel Output Port.
K2 P19 Digital video output Video Pixel Output Port.
J2 P18 Digital video output Video Pixel Output Port.
K3
P17
Digital video output
Video Pixel Output Port.
J3 P16 Digital video output Video Pixel Output Port.
K4 LLC Digital video output Line-Locked Output Clock for the Pixel Data (Range = 13.5 MHz to 162.5 MHz).
J4 P15 Digital video output Video Pixel Output Port.
K5 P14 Digital video output Video Pixel Output Port.
J5 P13 Digital video output Video Pixel Output Port.
K6 P12 Digital video output Video Pixel Output Port.
J6 P11 Digital video output Video Pixel Output Port.
K7 P10 Digital video output Video Pixel Output Port.
J7 P9 Digital video output Video Pixel Output Port.
K8
P8
Digital video output
Video Pixel Output Port.
J8 P7 Digital video output Video Pixel Output Port.
K9 P6 Digital video output Video Pixel Output Port.
J9 P5 Digital video output Video Pixel Output Port.
H10 P4 Digital video output Video Pixel Output Port.
H9
P3
Digital video output
Video Pixel Output Port.
G10 P2 Digital video output Video Pixel Output Port.
G9 P1 Digital video output Video Pixel Output Port.
F10 P0 Digital video output Video Pixel Output Port.
E10 DE Miscellaneous digital Data enable (DE) is a signal that indicates active pixel data.
F9 HS Digital video output Horizontal Synchronization Output Signal.
E9 VS/FIELD/ALSB Digital input/output Vertical Synchronization Output Signal. FIELD is a field synchronization output
signal in all interlaced video modes. VS or FIELD can be configured for this pin.
The ALSB allows selection of the I2C address.
D10, C10,
D9, C9
I2S0 to I2S3 Miscellaneous digital Audio Output Pins. Pins can be configured to output S/PDIF digital audio output
(S/PDIF) or I2S.
A9 SCLK/INT2 Miscellaneous digital A dual function pin that can be configured to output an audio serial clock or an
Interrupt 2 signal.
B9 LRCLK Miscellaneous digital Audio Left/Right Clock.
A8 MCLK/INT2 Miscellaneous digital A dual function pin that can be configured to output an audio master clock or an
Interrupt 2 signal.
B8 SCL Miscellaneous digital I2C Port Serial Clock Input Pin. SCL is the clock line for the control port.
B7
SDA
Miscellaneous digital
I
2
C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
A7 INT1 Miscellaneous digital Interrupt. This pin can be active low or active high. When status bits change, this
pin is triggered. The events that trigger an interrupt are under user configuration.
B6 RESET Miscellaneous digital System Reset Input. Active low. A minimum low reset pulse width of 5 ms is
required to reset the ADV7610 circuitry.
A6 XTALP Miscellaneous
analog
Input Pin for a 28.63636 MHz Crystal, or an External 1.8 V, 28.63636 MHz Clock
Oscillator Source to Clock the ADV7610.
A5 XTALN Miscellaneous
analog
Crystal Input. Input pin for 28.63636 MHz crystal.
B4 CEC Digital input/output Consumer Electronic Control Channel.
B5 CS Miscellaneous digital Chip Select. Pulling this line up causes I2C state machine to ignore I2C transmission.
A3
DDCA_SCL
HDMI input
HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
B3 DDCA_SDA HDMI input HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
A2 RXA_5V HDMI input 5 V Detect Pin for Port A in the HDMI Interface.

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GLOBAL CONTROL REGISTERS
The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of
the ADV7610.
ADV7610 REVISION IDENTIFICATION
RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only)
Chip revision code.
Function
RD_INFO[15:0] Description
0x2051 = Final Silicon ADV7610 ADV7610
POWER-DOWN CONTROLS
Primary Power-Down Controls
POWER_DOWN is the main power-down control. It is the main control for power-down Mode 0 and Mode 1. See the Power-Down
Modes section for more details.
POWER_DOWN, IO, Address 0x0C[5]
A control to enable power-down mode. This is the main I2C power-down control.
Function
POWER_DOWN Description
0
Chip operational
1 (default) Enables chip power down
Secondary Power-Down Controls
The following controls allow various sections of the ADV7610 to be powered down.
It is possible to stop the clock to the CP to reduce power for a power-sensitive application. The CP_PWRDN bit enables this power-save
mode. The HDMI block is not affected by this power-save mode. This allows the use of limited HDMI, STDI monitoring features while
reducing the power consumption. For full processing of the HDMI input, the CP core needs to be powered up.
CP_PWRDN, IO, Address 0x0C[2]
A power-down control for the CP core.
Function
CP_PWRDN Description
0 (default) Powers up clock to CP core.
1 Powers down clock to CP core. HDMI block not affected by this bit.
XTAL_PDN
XTAL_PDN allows the user to power down the XTAL clock in the following sections:
•STDI blocks
•Free run synchronization generation block
•I2C sequencer block, which is used for the configuration of the gain, clamp, and offset
•CP and HDMI section
The XTAL clock is also provided to the HDCP engine, EDID, and the repeater controller within the HDMI receiver. The XTAL clock
within these sections is not affected by XTAL_PDN.
XTAL_PDN, IO, Address 0x0B[0]
A power-down control for the XTAL in the digital blocks.
Function
XTAL_PDN Description
0 (default) Powers up XTAL buffer to digital core
1 Powers down XTAL buffer to digital core

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CORE_PDN
CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections:
•CP block
•Digital section of the HDMI block
CORE_PDN, IO, Address 0x0B[1]
A power-down control for the DPP, CP core, and digital sections of the HDMI core.
Function
CORE_PDN Description
0 (default) Powers up CP and digital sections of HDMI block
1 Powers down CP and digital section of HDMI block
Power-Down Modes
The ADV7610 supports the following power-down modes:
•Power-Down Mode 0
•Power-Down Mode 1
Table 5 shows the power-down and normal modes of ADV7610.
Table 5. Power-Down Modes
POWER_DOWN Bit CEC_POWER_UP Bit CEC EDID Power-Down Mode
0 0 Disabled Enabled Power-Down Mode 0
0 1 Enabled Enabled Power-Down Mode 1
1 0 Disabled Enabled1Normal mode
1 1 Enabled Enabled1Normal mode
1Dependent on the values of EDID_X_ENABLE_CPU and EDID_X_ENABLE for the HDMI port (where X is A).
Power-Down Mode 0
In Power-Down Mode 0, selected sections and pads are kept active to provide EDID and +5 V antiglitch filter functionality.
In Power-Down Mode 0, the sections of the ADV7610 are disabled except for the following blocks:
•I2C slave section.
•EDID/repeater controller.
•EDID ring oscillator.
The ring oscillator provides a clock to the EDID/repeater controller (refer to the E-EDID/Repeater Controller section) and the +5 V
power supply antiglitch filter. The clock output from the ring oscillator runs at approximately 50 MHz.
The following pads only are enabled in Power-Down Mode 0:
•I2C pads
•SDA
•SCL
•+5 V pads
•RXA_5V
•HPA_A
•DDC pads
•DDCA_SCL
•DDCA_SDA
•Reset pad RESET
Power-Down Mode 0 is initiated through a software (I2C register) configuration.

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Entering Power-Down Mode 0 via Software
The ADV7610 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This
method allows an external processor to put the system in which the ADV7610 is integrated into standby mode. In this case, the CP and
HDMI cores of the ADV7610 are kept powered up from the main power (for example, ac power) and set in or out of power-down Mode 0
through the POWER_DOWN bit.
Power-Down Mode 1
Power-Down Mode 1 is enabled when the following conditions are met:
•POWER_DOWN bit is set to 1
•CEC section is enabled by setting CEC_POWER_UP to 1
Power-Down Mode 1 provides the same functionality as Power-Down Mode 0, with the addition of the following sections:
•XTAL clock
•CEC section
•Interrupt controller section
The following pads are enabled in Power-Down Mode 1:
•Same pads as enabled in Power-Down Mode 0
•CEC pad
•INT1 and INT2 interrupt pads
The internal EDID is also accessible through the DDC bus for Port A in Power-Down Mode 0 and Power-Down Mode 1.
GLOBAL PIN CONTROL
Reset Pin
The ADV7610 can be reset by a low reset pulse on the reset pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the
low pulse before an I2C write is performed to the ADV7610.
Reset Controls
MAIN_RESET, IO, Address 0xFF[7] (Self-Clearing)
Main reset where I2C registers are reset to their default values.
Function
MAIN_RESET Description
0 (default) Normal operation
1 Applies main I2C reset
Tristate Output Drivers
PA D S _ P DN , IO, Address 0x0C[0]
A power-down control for pads of the digital output s. When enabled, the pads are tristated and the input path is disabled. This control
applies to the DE, HS, VS/FIELD/ALSB, INT1, and LLC pads and to the P0 to P23 pixel pads.
Function
PADS_PDN Description
0 (default) Powers up pads of digital output pins
1 Powers down pads of digital output pins
DDC_PWRDN[7:0], Addr 68 (HDMI), Address 0x73[7:0]
A power-down control for DDC pads.
Function
DDC_PWRDN[7:0] Description
0 (default) Powers up DDC pads
1 Powers down DDC pads

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TRI_PIX
This bit allows the user to tristate the output driver of pixel outputs. Upon setting TRI_PIX, the pixel output P[23:0] is tristated.
TRI_PIX, IO, Address 0x15[1]
A control to tristate the pixel data on the pixel pins, P[23:0].
Function
TRI_PIX Description
0 Pixel bus active
1 (default) Tristates pixel bus
Tristate LLC Driver
TRI_LLC, IO, Address 0x15[2]
A control to tristate the output pixel clock on the LLC pin.
Function
TRI_LLC Description
0 LLC pin active
1 (default) Tristates LLC pin
Tristate Synchronization Output Drivers
The following output synchronization signals are tristated when TRI_SYNCS is set:
•VS/FIELD/ALSB
•HS
•DE
The drive strength controls for these signals are provided via the DR_STR_SYNC bits. The ADV7610 does not support tristating via a
dedicated pin.
TRI_SYNCS, IO, Address 0x15[3]
Synchronization output pins tristate control. The synchronization pins under this control are HS, VS/FIELD/ALSB, and DE.
Function
TRI_SYNCS Description
0 Sync output pins active
1 (default) Tristates sync output pins
Tristate Audio Output Drivers
TRI_AUDIO, IO Map, Address 0x15[4]
TRI_AUDIO allows the user to tristate the drivers of the following audio output signals:
•AP
•SCLK/INT2
•LRCLK
•MCLK/INT2
The drive strength for the output pins can be controlled by the DR_STR[1:0] bits. The ADV7610 does not support tristating via a
dedicated pin.
TRI_AUDIO, IO, Address 0x15[4]
A control to tristate the audio output interface pins (AP).
Function
TRI_AUDIO Description
0
Audio output pins active
1 (default) Tristates audio output pins

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Drive Strength Selection
DR_STR
It may be desirable to strengthen or weaken the drive strength of the output drivers for electromagnetic compatibility (EMC)
and crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes.
The drive strength DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization signals:
•DE
•HS
•VS/FIELD
The DR_STR[1:0] drive strength bits affect output drivers for the following output pins:
•P[23:0]
•AP
•SCLK
•SDA
•SCL
The drive strength DR_STR_CLK[1:0] bits affect output driver for LLC line.
DR_STR[1:0], IO, Address 0x14[5:4]
A control to set the drive strength of the data output drivers.
Function
DR_STR[1:0] Description
00 Reserved
01 Medium low (2×)
10 (default) Medium high (3×)
11
High (4×)
DR_STR_CLK[1:0], IO, Address 0x14[3:2]
A control to set the drive strength control for the output pixel clock out signal on the LLC pin.
Function
DR_STR_CLK[1:0] Description
00 Reserved
01 Medium low (2×) for LLC up to 60 MHz
10 (default) Medium high (3×) for LLC from 44 MHz to 105 MHz
11 High (4×) for LLC greater than 100 MHz
DR_STR_SYNC[1:0], IO, Address 0x14[1:0]
A control to set the drive strength of the synchronization pins, HS, VS/FIELD/ALSB, and DE.
Function
DR_STR_SYNC[1:0] Description
00 Reserved
01
Medium low (2×)
10 (default)
Medium high (3×)
11 High (4×)
Output Synchronization Selection
VS_OUT_SEL, IO, Address 0x06[7]
A control to select the VSync or FIELD signal to be output on the VS/FIELD/ALSB pin.
Function
VS_OUT_SEL Description
0 Selects FIELD output on VS/FIELD/ALSB pin
1 (default) Selects VSync output on VS/FIELD/ALSB pin

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F_OUT_SEL, IO, Address 0x05[4]
A control to select the DE or FIELD signal to be output on the DE pin.
Function
F_OUT_SEL Description
0 (default) Selects DE output on DE pin
1
Selects FIELD output on DE pin
Output Synchronization Signals Polarity
INV_LLC_POL, IO Map, Address 0x06, [0]
The polarity of the pixel clock provided by the ADV7610 via the LLC pin can be inverted using the INV_LLC_POL bit. Note that this
inversion affects only the LLC output pin. The other output pins are not affected by INV_LLC_POL.
Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of the downstream
devices processing the output data of the ADV7610. It is expected that these parameters must be matched regardless of the type of video
data that is transmitted. Therefore, INV_LLC_POL is designed to be mode independent.
INV_LLC_POL, IO, Address 0x06[0]
A control to select the polarity of the LLC.
Function
INV_LLC_POL Description
0 (default) Does not invert LLC
1
Inverts LLC
The output synchronization signals HS, VS/FIELD/ALSB, and DE can be inverted using the following control bits:
•INV_HS_POL
•INV_VS_POL
•INV_F_POL
INV_HS_POL, IO, Address 0x06[1]
A control to select the polarity of the HS signal.
Function
INV_HS_POL Description
0 (default) Negative polarity HS
1 Positive polarity HS
INV_VS_POL, IO, Address 0x06[2]
A control to select the polarity of the VS/FIELD/ALSB signal.
Function
INV_VS_POL Description
0 (default) Negative polarity VS/FIELD/ALSB
1 Positive polarity VS/FIELD/ALSB
INV_F_POL, IO, Address 0x06[3]
A control to select the polarity of the DE signal.
Function
INV_F_POL Description
0 (default) Negative FIELD/DE polarity
1 Positive FIELD/DE polarity

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Digital Synthesizer Controls
The ADV7610 features two digital encoder synthesizers that generate the following clocks:
•Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent
to HDMI streams. The output of the LLC pin is either this pixel clock or a divided down version, depending on the datapath
configuration. It takes less than one video frame for this synthesizer to lock.
•Audio DPLL: this clock synthesizer generates the audio clock. As per HDMI specifications, the incoming HDMI clock is divided
down by CTS and then multiplied up by N. This audio clock is used as the main clock in the audio stream section. The output of
MCLK represents this clock. It takes less than 5 ms after a valid ACR packet for this synthesizer to lock.
Crystal Frequency Selection
The ADV7610 supports 27.0, 28.63636, 24.576, and 24.0 MHz frequency crystals. The control described here allows selection of crystal
frequency.
XTAL_FREQ_SEL[1:0], IO, Address 0x04[2:1]
A control to set the XTAL frequency.
Function
XTAL_FREQ_SEL[1:0] Description
00 27 MHz
01 (default) 28.63636 MHz
10 24.576 MHz
11
24.0 MHz

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PRIMARY MODE AND VIDEO STANDARD
Setting the primary mode and choosing a video standard are the most fundamental settings when configuring the ADV7610. There
are two primary modes for the ADV7610: HDMI-component and HDMI-graphic modes. The appropriate mode should be set with
PRIM_MODE[3:0].
In HDMI modes, the ADV7610 can receive and decode HDMI or DVI data throughout the DVI/HDMI receiver front end. Video data
from the HDMI receiver is routed to the CP block while audio data is available on the audio interface. One of these modes is enabled by
selecting either the HDMI-component or the HDMI-graphics primary mode.
Note: The HDMI receiver decodes and processes any applied HDMI stream irrespective of the video resolution. However, many primary
mode and video standard combinations can be used to define how the decoded video data routed to the DPP and CP blocks is processed.
This allows for free run features and data decimation modes that some systems may require.
If free run and decimation are not required, it is recommended to set the following configuration for HDMI mode:
•PRIM_MODE[3:0]: 0x06
•VID_STD[5:0]: 0x02
PRIMARY MODE AND VIDEO STANDARD CONTROLS
PRIM_MODE[3:0], IO, Address 0x01[3:0]
A control to select the primary mode of operation of the decoder. Setting the appropriate HDMI mode is important for free run mode to
work properly. This control is used with VID_STD[5:0].
Function
PRIM_MODE[3:0] Description
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Reserved
0101 HDMI component
0110 (default) HDMI graphics
0111 to 1111 Reserved
VID_STD[5:0], IO, Address 0x00[5:0]
Sets the input video standard mode. Configuration is dependent on PRIM_MODE[3:0]. Setting the appropriate mode is important for
free run mode to work properly.
Function
VID_STD[5:0] Description
000010 Default value
PRIM_MODE[3:0] should be used with VID_STD[5:0] to select the required video mode. These controls are set according to Table 6.
Table 6. Primary Mode and Video Standard Selection
PRIM_MODE[3:0] VID_STD[5:0]
Code Description Processor Code Input Video Output Resolution Comment
0000 Reserved xxxxxx Reserved Reserved
0001 Reserved xxxxxx Reserved Reserved
0010 Reserved xxxxxx Reserved Reserved
0100 Reserved xxxxxx Reserved Reserved
0011
Reserved
xxxxxx
Reserved
Reserved

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PRIM_MODE[3:0] VID_STD[5:0]
Code Description Processor Code Input Video Output Resolution Comment
0101 HDMI-COMP
(Component video)
CP 000000 SD 1×1 525i 720 × 480 HDMI receiver support
CP 000001 SD 1×1 625i 720 × 576
CP 000010 SD 2×1 525i 720 × 480
CP 000011 SD 2×1 625i 720 × 576
000100 Reserved Reserved
000101 Reserved Reserved
000110 Reserved Reserved
000111 Reserved Reserved
001000 Reserved Reserved
001001 Reserved Reserved
CP 001010 PR 1×1 525p 720 × 480
CP
001011
PR 1×1 625p
720 × 576
CP 001100 PR 2×1 525p 720 × 480
CP 001101 PR 2×1 625p 720 × 576
001110 Reserved Reserved
001111 Reserved Reserved
010000 Reserved Reserved
010001 Reserved Reserved
010010 Reserved Reserved
CP 010011 HD 1×1 1280 × 720
CP 010100 HD 1×1 1920 × 1080
CP 010101 HD 1×1 1920 × 1035
CP 010110 HD 1×1 1920 × 1080
CP 010111 HD 1×1 1920 × 1152
011000 Reserved Reserved
CP 011001 HD 2×1 720p 1280 × 720
CP 011010 HD 2×1 1125 1920 × 1080
CP 011011 HD 2×1 1125 1920 × 1035
CP 011100 HD 2×1 1250 1920 × 1080
CP 011101 HD 2×1 1250 1920 × 1152
CP 011110 HD 1×1 1920 × 1080
CP 011111 HD 1×1 1920 × 1080
0110 HDMI-GR
(Graphics)
CP 000000 SVGA 800 × 600 @ 56 HDMI receiver support
CP 000001 SVGA 800 × 600 @ 60
CP 000010 SVGA 800 × 600 @ 72
CP 000011 SVGA 800 × 600 @ 75
CP 000100 SVGA 800 × 600 @ 85
CP 000101 SXGA 1280 × 1024 @ 60
CP 000110 SXGA 1280 × 1024 @ 75
000111 Reserved Reserved
CP 001000 VGA 640 × 480 @ 60
CP 001001 VGA 640 × 480 @ 72
CP 001010 VGA 640 × 480 @ 75
CP 001011 VGA 640 × 480 @ 85
CP 001100 XGA 1024 × 768 @ 60
CP 001101 XGA 1024 × 768 @ 70
CP
001110
XGA
1024 × 768 @ 75
CP 001111 XGA 1024 × 768 @ 85
01xxxx Reserved
0111 Reserved xxxxxx Reserved Reserved
1000 Reserved xxxxxx Reserved Reserved
1001 Reserved xxxxxx Reserved Reserved

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PRIM_MODE[3:0] VID_STD[5:0]
Code Description Processor Code Input Video Output Resolution Comment
1010 Reserved xxxxxx Reserved Reserved
1011 Reserved xxxxxx Reserved Reserved
1100 Reserved xxxxxx Reserved Reserved
1101 Reserved xxxxxx Reserved Reserved
1110 Reserved xxxxxx Reserved Reserved
1111 Reserved xxxxxx Reserved Reserved
V_FREQ
This control is set to allow free run to work correctly (refer to Table 7).
V_FREQ[2:0], IO, Address 0x01[6:4]
A control to set vertical frequency.
Function
V_FREQ[2:0] Description
000 (default) 60 Hz
001 50 Hz
010 30 Hz
011 25 Hz
100 24 Hz
101 Reserved
110 Reserved
111 Reserved
HDMI DECIMATION MODES
Some of the modes defined by VID_STD have an inherent 2×1 decimation. For these modes, the main clock generator and the decim-
ation filters in the DPP block are configured automatically. This ensures the correct data rate at the input to the CP block. Refer to the
Data Preprocessor and Color Space Conversion and Color Controls section for more information on the automatic configuration of the
DPP block.
The ADV7610 correctly decodes and processes any incoming HDMI stream with the required decimation, irrespective of its video
resolution:
•In 1×1 mode (that is, without decimation), as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode
without decimation.
For example:
•Set PRIM_MODE to 0x5 and VID_STD to 0x00
•Set PRIM_MODE to 0x5 and VID_STD to 0x13
•Set PRIM_MODE to 0x6 and VID_STD to 0x02
•In 2×1 decimation mode, as long the PRIM_MODE and VID_STD registers are programmed for any HDMI mode with 2×1
decimation. For example:
•Set PRIM_MODE to 0x5 and VID_STD to 0x0C
•Set PRIM_MODE to 0x5 and VID_STD to 0x19
Note: Decimating the video data from an HDMI stream is optional and should be performed only if it is required by the downstream
devices connected to the ADV7610.
PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN
If free run is enabled in HDMI mode, PRIM_MODE[3:0] and VID_STD[5:0] specify the input resolution expected by the ADV7610 (for
free run Mode 1) and/or the output resolution to which the ADV7610 free runs (for free run Mode 0 and Mode 1). Refer to the Free Run
Mode section for additional details on the free run feature for HDMI inputs and to HDMI_FRUN_MODE.