Analog Devices ADV7850 User manual

ADV7850
Fast Switching 4:1 HDMI 1.4 Receiver
With 3D-Comb Decoder and Digitizer
HARDWARE
MANUAL
Rev. A
May 2012

ADV7850
Rev. A May 2012
2
TABLE OF CONTENTS
1INTRODUCTION TO ADV7850 HARDWARE MANUAL................................................................................................ 11
1.1 DESCRIPTION OF THE HARDWARE MANUAL...................................................................................................................................... 11
1.2 COPYRIGHT INFORMATION.................................................................................................................................................................. 11
1.3 DISCLAIMER........................................................................................................................................................................................... 11
1.4 TRADEMARK AND SERVICE MARK NOTICE......................................................................................................................................... 11
1.5 NUMBER NOTATIONS ........................................................................................................................................................................... 11
1.6 REGISTER ACCESS CONVENTIONS ....................................................................................................................................................... 11
1.7 ACRONYMS AND ABBREVIATIONS ....................................................................................................................................................... 11
1.8 CONTROL DESCRIPTION ....................................................................................................................................................................... 13
1.9 REFERENCES........................................................................................................................................................................................... 14
2INTRODUCTION ................................................................................................................................................................. 15
2.1 ANALOG FRONT END............................................................................................................................................................................ 15
2.2 STANDARD DEFINITION PROCESSOR ................................................................................................................................................... 16
2.3 HDMI RECEIVER .................................................................................................................................................................................. 16
2.4 COMPONENT PROCESSOR..................................................................................................................................................................... 16
2.5 AUDIO CODEC .................................................................................................................................................................................... 17
2.6 MAIN FEATURES OF ADV7850............................................................................................................................................................ 17
2.6.1 Analog Front End .............................................................................................................................................................. 17
2.6.2 HDMI Receiver.................................................................................................................................................................. 17
2.6.3 Composite and S-Video Processing................................................................................................................................... 17
2.6.4 Component Video Processing............................................................................................................................................ 18
2.6.5 RGB Graphics Processing .................................................................................................................................................. 18
2.6.6 Audio CODEC................................................................................................................................................................... 18
2.6.7 Additional Features........................................................................................................................................................... 18
2.7 FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................................... 19
2.8 PIN DESCRIPTION.................................................................................................................................................................................. 20
3GLOBAL CONTROL REGISTERS........................................................................................................................................ 29
3.1 ADV7850 REVISION IDENTIFICATION................................................................................................................................................ 29
3.2 POWER-DOWN CONTROLS ................................................................................................................................................................... 29
3.2.1 Primary Power-down Controls ......................................................................................................................................... 29
3.2.2 Secondary Power-down Controls...................................................................................................................................... 29
3.2.3 Power-down Mode ............................................................................................................................................................ 30
3.2.4 EDID Support in Power-off Mode.................................................................................................................................... 31
3.2.5 ADC Power-down Control................................................................................................................................................ 32
3.2.6 DDC and VGA Pins Power Down .................................................................................................................................... 33
3.3 RESET CONTROLS AND GLOBAL PIN CONTROLS................................................................................................................................. 33
3.3.1 Reset Pin ............................................................................................................................................................................ 33
3.3.2 Reset Controls .................................................................................................................................................................... 33
3.3.3 Tristate Pins....................................................................................................................................................................... 34
3.3.4 ADC Phase Control ........................................................................................................................................................... 34
3.4 ADC-HDMI SIMULTANEOUS MODE.................................................................................................................................................. 34
4PRIMARY MODE AND VIDEO STANDARD .................................................................................................................... 36
4.1 PRIMARY MODE AND VIDEO STANDARD CONTROLS ........................................................................................................................ 36
4.1.1 Setting the Vertical Frequency .......................................................................................................................................... 40
4.2 STANDARD CONFIGURATION FOR SDP-HDMI AUDIO SIMULTANEOUS MODE............................................................................. 40
4.3 PRIMARY MODE AND VIDEO STANDARD CONFIGURATION FOR HDMI FREE RUN ....................................................................... 41

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5ANALOG FRONT END......................................................................................................................................................... 42
5.1 ADC SAMPLING CLOCK ....................................................................................................................................................................... 42
5.2 ADCS AND VOLTAGE CLAMPS ............................................................................................................................................................ 42
5.2.1 Analog Input Hardware Configuration............................................................................................................................ 42
5.2.2 Clamp Operation............................................................................................................................................................... 43
5.2.3 SDP Clamp Operation....................................................................................................................................................... 43
5.3 ANALOG INPUT MUXING ..................................................................................................................................................................... 45
5.3.1 Analog Input Routing Recommendation.......................................................................................................................... 45
5.4 AUTOMATIC INPUT MUXING SELECTION ........................................................................................................................................... 46
5.5 MANUAL INPUT MUXING OVERVIEW................................................................................................................................................. 47
5.5.1 Manual Input Muxing ...................................................................................................................................................... 47
5.6 VIDEO OUTPUT MUX........................................................................................................................................................................... 49
5.7 SYNC1-3 INPUT CONTROL.................................................................................................................................................................. 50
5.7.1 Automatic Synchronization Configuration...................................................................................................................... 51
5.7.2 Manual Synchronization Configuration .......................................................................................................................... 51
5.8 SYNCHRONIZATION SLICERS ................................................................................................................................................................ 52
5.8.1 Synchronization Filter Stage ............................................................................................................................................. 52
5.8.2 Sync Stripper Slice Level .................................................................................................................................................... 53
5.8.3 D-Terminal Connector...................................................................................................................................................... 53
5.8.4 TRI 1-8 Input Resistor Selection ....................................................................................................................................... 53
5.8.5 Trilevel Input Controls...................................................................................................................................................... 54
5.8.6 Trilevel Slicer Operation ................................................................................................................................................... 54
5.8.7 Bilevel/Trilevel Selection ................................................................................................................................................... 56
5.8.8 Trilevel Slicer Readbacks................................................................................................................................................... 57
5.8.9 Programming Trilevel Slicers ............................................................................................................................................ 59
5.8.9.1 Upper Slice Levels...................................................................................................................................................................59
5.8.9.2 Lower Slice Levels ..................................................................................................................................................................62
5.8.10 Fast Blanking Configuration........................................................................................................................................ 64
5.8.11 SCART Source Selection Control ................................................................................................................................. 65
5.8.12 SCART Fast Blank Timing........................................................................................................................................... 65
5.9 ANTI ALIASING FILTERS ....................................................................................................................................................................... 66
5.9.1 Description......................................................................................................................................................................... 66
6STANDARD DEFINITION PROCESSOR ........................................................................................................................... 69
6.1 SDP BLOCK............................................................................................................................................................................................ 69
6.2 SDP SYNCHRONIZATION PROCESSING................................................................................................................................................ 69
6.3 SDP GENERAL SETUP............................................................................................................................................................................ 70
6.3.1 Autodetection of SDP Modes ............................................................................................................................................ 70
6.3.2 Pedestal Configuration in SDP Modes.............................................................................................................................. 72
6.4 SDP STATUS REGISTERS ....................................................................................................................................................................... 73
6.4.1 SDP Autodetection Result ................................................................................................................................................. 73
6.4.2 SDP Video Detection ......................................................................................................................................................... 73
6.4.3 Input Status ....................................................................................................................................................................... 74
6.4.4 Macrovision Status............................................................................................................................................................ 77
6.4.5 Synctip Noise Measurement, Noisy and Very Noisy Signal Detection ............................................................................ 78
6.4.6 Additional SDP Status Registers ....................................................................................................................................... 79
6.5 SDP COLOR CONTROLS........................................................................................................................................................................ 80
6.5.1 Contrast ............................................................................................................................................................................. 81
6.5.2 Brightness........................................................................................................................................................................... 81
6.5.3 Saturation.......................................................................................................................................................................... 81
6.5.4 Hue..................................................................................................................................................................................... 81

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6.6 SDP GAIN OPERATION......................................................................................................................................................................... 81
6.6.1 SDP Luma Gain ................................................................................................................................................................ 82
6.6.2 Chroma Gain..................................................................................................................................................................... 84
6.6.3 Peak White Feature........................................................................................................................................................... 85
6.6.4 Peak Chroma ..................................................................................................................................................................... 86
6.6.5 Color Kill............................................................................................................................................................................ 86
6.7 3D COMB ............................................................................................................................................................................................... 87
6.7.1 3D Comb Activation ......................................................................................................................................................... 87
6.7.2 3D Comb Sensitivity.......................................................................................................................................................... 92
6.8 YSHAPING FILTER................................................................................................................................................................................ 92
6.8.1 Input Shaping Filter Enables........................................................................................................................................... 101
6.9 CHROMA SHAPING FILTER ................................................................................................................................................................. 103
6.10 SPLIT FILTER SELECTION ............................................................................................................................................................... 107
6.11 IF FILTER COMPENSATION............................................................................................................................................................ 108
6.12 LUMA TRANSIENT IMPROVEMENT AND CHROMA TRANSIENT IMPROVEMENT ....................................................................... 109
6.13 RINGING REDUCTION .................................................................................................................................................................... 114
6.14 HORIZONTAL AND VERTICAL PEAKING....................................................................................................................................... 115
6.14.1Horizontal Peaking..................................................................................................................................................... 115
6.14.2 Vertical Peaking ......................................................................................................................................................... 118
6.15 FRAME SYNCHRONIZATION (FRAME TIME BASE CORRECTION) ............................................................................................... 121
6.16 FREE RUN MODE............................................................................................................................................................................ 122
6.17 LETTERBOX DETECTION................................................................................................................................................................ 123
6.17.1 Detection at Start of Field .......................................................................................................................................... 124
6.17.2 Detection at End of Field............................................................................................................................................ 124
6.17.3 Detection at Mid Range.............................................................................................................................................. 124
6.18 SDP SYNCHRONIZATION OUTPUT SIGNALS................................................................................................................................ 125
6.18.1 HSync Timing Configuration..................................................................................................................................... 125
6.18.2 VSync and FIELD Configuration............................................................................................................................... 126
6.18.3 DE Configuration ....................................................................................................................................................... 129
6.18.4 CSync Signal Configuration ....................................................................................................................................... 131
6.18.5 Manual Color Space Conversion Matrix................................................................................................................... 132
6.18.5.1 CSC Manual Programming...............................................................................................................................................135
7HDMI RECEIVER................................................................................................................................................................ 136
7.1 MODES OF OPERATION....................................................................................................................................................................... 136
7.1.1 HDMI Mux Mode ........................................................................................................................................................... 136
7.1.2 HDMI Non-Mux Mode................................................................................................................................................... 136
7.2 +5 VCABLE DETECT........................................................................................................................................................................... 137
7.3 HOT PLUG ASSERT .............................................................................................................................................................................. 138
7.4 E-EDID/REPEATER CONTROLLER..................................................................................................................................................... 141
7.5 E-EDID DATA CONFIGURATION ...................................................................................................................................................... 142
7.5.1 E-EDID Support for Cable Supply Mode........................................................................................................................ 144
7.6 5VSUPPLY .......................................................................................................................................................................................... 144
7.7 TRANSITIONING FROM CABLE SUPPLY MODE................................................................................................................................. 144
7.8 SPI INTERFACE .................................................................................................................................................................................... 145
7.8.1 SPI EEPROM Data Structure ......................................................................................................................................... 146
7.9 STRUCTURE OF INTERNAL E-EDID FOR PORT A ............................................................................................................................. 147
7.10 STRUCTURE OF INTERNAL E-EDID OF PORTS B, C, AND D ....................................................................................................... 147
7.11 SPA CONFIGURATION................................................................................................................................................................... 150
7.12 EXTERNAL E-EDID ....................................................................................................................................................................... 150
7.13 TMDS EQUALIZATION.................................................................................................................................................................. 150
7.13.1 Equalizer Read back................................................................................................................................................... 150

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7.13.2 Manual Operation...................................................................................................................................................... 150
7.14 PORT SELECTION............................................................................................................................................................................ 151
7.15 FAST SWITCHING AND BACKGROUND PORT SELECTION ........................................................................................................... 151
7.16 TMDS CLOCK ACTIVITY DETECTION ......................................................................................................................................... 153
7.16.1 Clock and Data Termination Control ....................................................................................................................... 154
7.17 TMDS MEASUREMENT ................................................................................................................................................................. 155
7.17.1 TMDS Measurement After TMDS PLL..................................................................................................................... 155
7.18 DEEP COLOR MODE SUPPORT ...................................................................................................................................................... 158
7.19 VIDEO FIFO................................................................................................................................................................................... 160
7.20 PIXEL REPETITION ......................................................................................................................................................................... 161
7.21 ARC SUPPORT................................................................................................................................................................................ 163
7.22 3D VIDEO SUPPORT ................................................................................................................................................................ 165
7.23 HDCP SUPPORT ............................................................................................................................................................................ 165
7.23.1 HDCP Decryption Engine .......................................................................................................................................... 165
7.23.2 Internal HDCP Key OTP ROM ................................................................................................................................. 167
7.23.3 HDCP Keys Access Flags ............................................................................................................................................ 167
7.24 HDMI SYNCHRONIZATION PARAMETERS................................................................................................................................... 169
7.24.1 Horizontal Filter and Measurements ........................................................................................................................ 169
7.24.2 Primary Port Horizontal Filter Measurements ......................................................................................................... 169
7.24.3 Background Port Horizontal Filter Measurements................................................................................................... 171
7.24.4 Horizontal Filter Locking Mechanism....................................................................................................................... 172
7.24.5 Vertical Filters and Measurements............................................................................................................................ 172
7.24.6 Primary Port Vertical Filter Measurements .............................................................................................................. 172
7.24.7 Background Port Vertical Filter Measurements........................................................................................................ 176
7.24.8 Vertical Filter Locking Mechanism............................................................................................................................ 177
7.25 AUDIO CONTROL AND CONFIGURATION .................................................................................................................................... 177
7.25.1 Audio DPLL................................................................................................................................................................ 178
7.25.2 Locking Mechanism.................................................................................................................................................... 178
7.25.3 ACR Parameters Loading Method............................................................................................................................. 178
7.25.4 Audio DPLL Coast Feature........................................................................................................................................ 179
7.26 AUDIO FIFO .................................................................................................................................................................................. 179
7.27 AUDIO PACKET TYPE FLAGS......................................................................................................................................................... 181
7.28 AUDIO OUTPUT INTERFACE ......................................................................................................................................................... 183
7.28.1 I2S/SPDIF Audio Interface and Output Controls ..................................................................................................... 184
7.28.2 DSD Audio Interface and Output Controls............................................................................................................... 187
7.28.3 DST Audio Interface and Output Controls ............................................................................................................... 189
7.28.4 HBR Interface and Output Controls.......................................................................................................................... 190
7.29 MCLKOUT SETTING .................................................................................................................................................................... 191
7.30 AUDIO CHANNEL MODE............................................................................................................................................................... 191
7.31 AUDIO MUTING ............................................................................................................................................................................. 192
7.31.1 Audio Mute Configuration ........................................................................................................................................ 192
7.31.2 Internal Mute Status .................................................................................................................................................. 194
7.31.3 AV Mute Status .......................................................................................................................................................... 194
7.31.4 Audio Stream with Incorrect Parity Error................................................................................................................. 194
7.32 AUDIO CLOCK REGENERATION PARAMETERS............................................................................................................................. 195
7.32.1 ACR Parameters Readbacks....................................................................................................................................... 195
7.32.2 Monitoring ACR Parameters ..................................................................................................................................... 195
7.33 CHANNEL STATUS.......................................................................................................................................................................... 196
7.33.1 Validity Status Flag.................................................................................................................................................... 196
7.33.2 General Control and Mode Information ................................................................................................................... 197
7.33.3 Category Code ............................................................................................................................................................ 198

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7.33.4 Source Number and Channel Number ...................................................................................................................... 198
7.33.5 Sampling and Frequency Accuracy............................................................................................................................ 198
7.33.6 Word Length............................................................................................................................................................... 199
7.33.7 Channel Status Copyright Value Assertion ............................................................................................................... 199
7.33.8 Monitoring Change of Audio Sampling Frequency................................................................................................... 200
7.34 PACKETS AND INFOFRAMES REGISTERS....................................................................................................................................... 200
7.34.1 InfoFrames Registers .................................................................................................................................................. 201
7.34.2 InfoFrame Collection Mode ....................................................................................................................................... 201
7.34.3 InfoFrame Checksum Error Flags .............................................................................................................................. 201
7.34.4 AVI InfoFrame Registers ............................................................................................................................................ 202
7.34.5 Audio InfoFrame Registers......................................................................................................................................... 203
7.34.6 SPD InfoFrame Registers............................................................................................................................................ 204
7.34.7 MPEG Source InfoFrame Registers............................................................................................................................ 204
7.34.8 Vendor Specific InfoFrame Registers ......................................................................................................................... 205
7.34.9 Multiple InfoFrames Support ( THX Media Director™)............................................................................................ 206
7.35 PACKET REGISTERS ........................................................................................................................................................................ 207
7.35.1 ACP Packet Registers.................................................................................................................................................. 207
7.35.2 ISRC Packet Registers................................................................................................................................................. 208
7.35.3 Gamut Metadata Packets........................................................................................................................................... 210
7.36 CUSTOMIZING PACKET/INFOFRAME STORAGE REGISTERS........................................................................................................ 211
7.37 BACKGROUND PORT INFOFRAME AND PACKET SUPPORT........................................................................................................... 213
7.38 REPEATER SUPPORT....................................................................................................................................................................... 214
7.38.1 Repeater Routines Performed by the E-EDID/Repeater Controller .......................................................................... 214
7.38.2 Repeater Actions Required by External Controller ................................................................................................... 215
7.38.3 HDCP Registers Available in Repeater Map ............................................................................................................. 216
7.39 INTERFACE TO DCM SECTION ..................................................................................................................................................... 221
7.40 COLOR SPACE INFORMATION SENT TO THE CP SECTION .......................................................................................................... 222
7.41 STATUS REGISTERS......................................................................................................................................................................... 222
7.42 HDMI RECEIVER SECTION RESET STRATEGY.............................................................................................................................. 225
7.43 HDMI PACKET DETECTION FLAG RESET.................................................................................................................................... 225
8DECIMATION CONTROLS, COLOR SPACE CONVERSION, AND COLOR CONTROLS......................................... 226
8.1 DCM CONFIGURATION..................................................................................................................................................................... 226
8.2 MANUAL FILTER COEFFICIENT PROGRAMMING ............................................................................................................................... 227
8.2.1 DCM Channel Power Down Control............................................................................................................................. 229
8.3 COLOR SPACE CONVERSION MATRIX ............................................................................................................................................... 230
8.3.1 CP CSC Selection............................................................................................................................................................. 230
8.3.2 Selecting Automatic or Manual CP CSC Conversion Mode .......................................................................................... 231
8.3.3 Automatic Color Space Conversion Matrix.................................................................................................................... 231
8.3.4 Manual Color Space Conversion Matrix........................................................................................................................ 233
8.3.4.1 CSC Manual Programming....................................................................................................................................................236
8.3.4.2 CSC Example.........................................................................................................................................................................237
8.3.5 CSC in Pass-through Mode ............................................................................................................................................. 238
8.4 COLOR CONTROLS .............................................................................................................................................................................. 238
9COMPONENT PROCESSOR.............................................................................................................................................. 241
9.1 INTRODUCTION TO COMPONENT PROCESSOR ................................................................................................................................. 241
9.2 CLAMP OPERATION ............................................................................................................................................................................ 242
9.3 CP GAIN OPERATION ........................................................................................................................................................................... 244
9.3.1 Features of Manual Gain Control................................................................................................................................... 244
9.3.2 Features of Automatic Gain Control .............................................................................................................................. 244
9.3.3 Manual Gain and Automatic Gain Control Selection ................................................................................................... 244

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9.3.4 Manual Gain Control...................................................................................................................................................... 245
9.3.5 Manual Gain Filter Mode............................................................................................................................................... 247
9.3.6 Automatic Gain Control ................................................................................................................................................. 247
9.3.6.1 Readback Signals from AGC Block.......................................................................................................................................249
9.4 CP OFFSET BLOCK .............................................................................................................................................................................. 252
9.5 CP DATA PATH FOR ANALOG MODE................................................................................................................................................ 253
9.5.1 Pregain Block................................................................................................................................................................... 253
9.6 SYNC PROCESSED BY CP SECTION ..................................................................................................................................................... 258
9.6.1 Sync Extracted by Sync Slicer Section ............................................................................................................................. 258
9.6.2 External Sync and Sync from HDMI Section ................................................................................................................. 259
9.6.2.1 Signals Routing to Synchronization Channels.......................................................................................................................259
9.6.2.2 XTAL Clock Registering and Glitch Rejection Filter............................................................................................................260
9.6.2.3 Signal Routed to SSPD Blocks ..............................................................................................................................................261
9.6.3 Final Sync Muxing Stage................................................................................................................................................. 262
9.7 SYNCHRONIZATION PROCESSING CHANNEL MUX........................................................................................................................... 262
9.7.1 Synchronization Source Polarity Detector...................................................................................................................... 263
9.7.1.1 SSPD Readback Signals.........................................................................................................................................................267
9.7.2 Standard Detection and Identification........................................................................................................................... 271
9.7.3 Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism.................................................................. 274
9.7.3.1 STDI Horizontal Locking Operation......................................................................................................................................274
9.7.3.2 STDI Vertical Locking...........................................................................................................................................................274
9.7.3.3 STDI Usage............................................................................................................................................................................277
9.7.3.4 STDI Readback Values for SD, PR, and HD.........................................................................................................................277
9.7.3.5 STDI Readback Values for Graphics Standards ....................................................................................................................278
9.8 CP OUTPUT SYNCHRONIZATION SIGNAL POSITIONING ................................................................................................................. 278
9.8.1 CP Primary Synchronization Signals.............................................................................................................................. 279
9.8.2 HSync Timing Controls................................................................................................................................................... 280
9.8.3 VSync Timing Controls ................................................................................................................................................... 283
9.8.4 DE Timing Controls ........................................................................................................................................................ 285
9.8.5 FIELD Timing Controls .................................................................................................................................................. 287
9.8.6 HCOUNT Timing Control.............................................................................................................................................. 296
9.9 CP DATA PROCESSING DELAY CONTROLS ....................................................................................................................................... 296
9.10 CP HORIZONTAL LOCK STATUS ................................................................................................................................................... 296
9.11 NOISE AND CALIBRATION ............................................................................................................................................................. 298
9.11.1 Measurement Window............................................................................................................................................... 298
9.11.2 Noise Measurement.................................................................................................................................................... 298
9.11.3 Calibration Measurement.......................................................................................................................................... 299
9.12 FREE RUN MODE............................................................................................................................................................................ 299
9.12.1 Free Run Mode Thresholds ........................................................................................................................................ 299
9.12.1.1 Horizontal Free Run Conditions.......................................................................................................................................299
9.12.2 Vertical Run Conditions............................................................................................................................................. 301
9.12.3 Free Run Default Color Output ................................................................................................................................. 303
9.13 CP STATUS ..................................................................................................................................................................................... 304
9.14 AUTO GRAPHICS MODE ................................................................................................................................................................ 305
9.14.1 Primary Auto Graphics Controls ............................................................................................................................... 305
9.14.2 Graphics Controls....................................................................................................................................................... 308
10 VBI DATA PROCESSOR .................................................................................................................................................... 310
10.1 VDP CONFIGURATION.................................................................................................................................................................. 310
10.1.1 VDP Default Configuration ....................................................................................................................................... 310
10.1.2 VDP Manual Configuration ...................................................................................................................................... 312
10.2 TELETEXT SYSTEM IDENTIFICATION ............................................................................................................................................ 313
10.3 VDP DECODED DATA READBACK REGISTERS ............................................................................................................................ 314
10.3.1 Teletext Readback Registers ....................................................................................................................................... 314

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10.3.2 CGMS and WSS Readback Registers ......................................................................................................................... 314
10.3.3 Closed Captioning Readback Registers ...................................................................................................................... 315
10.3.4 VITC Readback Registers ........................................................................................................................................... 316
10.3.5 VPS, PDC, UTC, Gemstar and CGMS Type B Readback Registers.......................................................................... 317
10.4 READBACK REGISTERS................................................................................................................................................................... 320
10.5 USER INTERFACE FOR I2CREADBACK REGISTERS ....................................................................................................................... 320
10.5.1 VDP Register Readback Protocols.............................................................................................................................. 320
10.5.1.1 Data Available Updates ....................................................................................................................................................320
10.5.2Content Based Data Update ...................................................................................................................................... 321
10.6 INTERRUPT BASED READING OF VDP READBACK REGISTERS ................................................................................................... 321
10.7 SPI READBACK REGISTERS ........................................................................................................................................................... 322
10.7.1 SPI Data Formats – Slave Mode ............................................................................................................................... 322
10.7.2 SPI Data Formats – Master Mode ........................................................................................................................... 324
10.7.3 Configuring Master Mode on the SPI Port ................................................................................................................ 326
10.7.4 SPI VDP Controls and Readbacks ............................................................................................................................ 328
10.7.5 ADV7850 VDP Interrupt Generation ....................................................................................................................... 330
11 AUDIO CODEC................................................................................................................................................................... 333
11.1 AUDIO CODEC OVERVIEW............................................................................................................................................................. 333
11.2 ANALOG AUDIO MUX FUNCTIONALITY..................................................................................................................................... 333
11.2.1 Analog Audio ADC Input Selection........................................................................................................................... 334
11.2.2 Analog Audio Mux Output Selection ........................................................................................................................ 334
11.2.3 Analog Audio Mux Input/Mux Output Configuration Overview ............................................................................ 335
11.3 AUDIO CODEC FUNCTIONALITY................................................................................................................................................... 336
11.3.1 Audio PLL................................................................................................................................................................... 336
11.3.2 VREF_AUDIO, FILTA and FILTD (Location)......................................................................................................... 337
11.3.3 DAC and Headphone Outputs................................................................................................................................... 338
11.3.3.1 Audio Codec DAC Output................................................................................................................................................338
11.3.3.2 Audio Codec Headphone Output......................................................................................................................................338
11.3.4 Volume Controls......................................................................................................................................................... 340
11.4 AUDIO POWER UP/DOWN CONTROLS ........................................................................................................................................ 341
12 MEMORY CONTROLLER .................................................................................................................................................. 344
12.1 MEMORY REQUIREMENTS ............................................................................................................................................................. 344
12.2 GENERAL CONTROLS ..................................................................................................................................................................... 344
12.2.1 Reset ............................................................................................................................................................................ 344
12.2.2 Output Enables........................................................................................................................................................... 344
12.3 DRIVE STRENGTH CONTROLS ....................................................................................................................................................... 345
12.4 DDR2BIST TEST ............................................................................................................................................................................. 345
12.5 EXTERNAL MEMORY LAYOUT GUIDELINES .................................................................................................................................. 347
13 HDMI TRANSMITTER....................................................................................................................................................... 349
13.1 GENERAL OPERATION ................................................................................................................................................................... 349
13.2 GENERAL CONTROLS ..................................................................................................................................................................... 349
13.3 HDMI DVI SELECTION ................................................................................................................................................................ 350
13.4 AV MUTE ....................................................................................................................................................................................... 351
13.5 TX SQUELCH FEATURE.................................................................................................................................................................. 351
13.6 SOURCE PRODUCT DESCRIPTION INFOFRAME............................................................................................................................ 352
13.7 SPARE PACKETS.............................................................................................................................................................................. 353
13.8 SYSTEM MONITORING ................................................................................................................................................................... 354
13.8.1 General Status and Interrupts.................................................................................................................................... 354
13.9 EDID/HDCP CONTROLLER STATUS ........................................................................................................................................... 355

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13.10 EDID/HDCP CONTROLLER ERROR CODES ................................................................................................................................ 355
13.11 VIDEO SETUP.................................................................................................................................................................................. 356
13.11.1 Input Format .............................................................................................................................................................. 356
13.11.2 Video Mode Detection................................................................................................................................................ 356
13.11.3 Pixel Repetition........................................................................................................................................................... 357
13.11.4 Video Related Packets and InfoFrames ..................................................................................................................... 358
13.11.5 AVI InfoFrame ........................................................................................................................................................... 358
13.11.6 MPEG InfoFrame ....................................................................................................................................................... 359
13.11.7 Gamut Metadata........................................................................................................................................................ 360
13.12 AUDIO SETUP ................................................................................................................................................................................. 362
13.12.1 Input Format .............................................................................................................................................................. 362
13.12.2 I2S Audio .................................................................................................................................................................... 363
13.12.3 SPDIF Audio............................................................................................................................................................... 368
13.12.4 DSD Audio.................................................................................................................................................................. 369
13.12.5 HBR Audio ................................................................................................................................................................. 369
13.12.6 N and CTS Parameters............................................................................................................................................... 370
13.12.7 N Parameter ............................................................................................................................................................... 371
13.12.8 CTS Parameter ........................................................................................................................................................... 371
13.12.9 Recommended N and Expected CTS Values ............................................................................................................. 371
13.12.10 Audio Sample Packets ................................................................................................................................................ 373
13.12.11 Audio InfoFrame........................................................................................................................................................ 377
13.12.12 Audio Content Protection Packet .............................................................................................................................. 378
13.12.13 ISRC Packet ................................................................................................................................................................ 379
13.13 EDID HANDLING .......................................................................................................................................................................... 380
13.13.1 Reading the EDID ...................................................................................................................................................... 380
13.13.2 EDID Definitions........................................................................................................................................................ 381
13.13.3 Additional Segments................................................................................................................................................... 381
13.13.4 EDID_TRIES Control................................................................................................................................................. 382
13.13.5 EDID_REREAD Control............................................................................................................................................ 382
13.14 HDCP HANDLING......................................................................................................................................................................... 382
13.14.1 One Sink And No Upstream Devices ......................................................................................................................... 382
13.14.2 Multiple Sinks and No Upstream Devices ................................................................................................................. 384
13.14.3 Software Implementation........................................................................................................................................... 385
13.14.4 AV Mute ..................................................................................................................................................................... 386
14 REGISTER ACCESS AND SERIAL PORTS DESCRIPTION............................................................................................ 388
14.1 MAIN I2CPORT.............................................................................................................................................................................. 388
14.1.1 Register Access ............................................................................................................................................................ 388
14.1.2 Protocol for Main I2C Port ......................................................................................................................................... 389
14.2 DDC PORTS ................................................................................................................................................................................... 389
14.2.1 I2C Protocols for Access to the Internal E-EDID ....................................................................................................... 389
14.2.2 I2C Protocols for Access to HDCP Registers............................................................................................................... 390
14.2.3 DDC Port A ................................................................................................................................................................ 390
14.2.4 DDC Port B................................................................................................................................................................. 390
14.2.5 DDC Port C ................................................................................................................................................................ 391
14.2.6 DDC Port D ................................................................................................................................................................ 391
15 INTERRUPTS ...................................................................................................................................................................... 392
15.1 INTERRUPT ARCHITECTURE OVERVIEW ...................................................................................................................................... 392
15.2 INTERRUPT PINS............................................................................................................................................................................. 392
15.2.1 Interrupt Duration ..................................................................................................................................................... 392

ADV7850
Rev. A May 2012
10
15.2.2 Interrupt Drive Level.................................................................................................................................................. 392
15.2.3 Interrupt Manual Assertion....................................................................................................................................... 393
15.2.4 Multiple Interrupt Events........................................................................................................................................... 394
15.3 RX SECTION .................................................................................................................................................................................... 394
15.4 DESCRIPTION OF RX INTERRUPT BITS.......................................................................................................................................... 398
15.4.1 General Operation...................................................................................................................................................... 398
15.4.2 Analog/HDMI Video Mode ....................................................................................................................................... 398
15.4.3 Macrovision Detection ............................................................................................................................................... 398
15.4.4 VDP Operation........................................................................................................................................................... 398
15.4.5 HDMI Only Mode ...................................................................................................................................................... 398
15.5 ADDITIONAL EXPLANATIONS ....................................................................................................................................................... 400
15.5.1 afe_interrupt_raw ...................................................................................................................................................... 400
15.5.2 stdi_data_valid_raw .................................................................................................................................................. 402
15.5.3 cp_lock, cp_unlock...................................................................................................................................................... 402
15.5.4Video 3D Detection .................................................................................................................................................... 403
15.5.5 HDMI Interrupts Validity Checking Process............................................................................................................. 403
15.5.5.1 Group 1 HDMI Interrupts.................................................................................................................................................403
15.5.5.2 Group 2 HDMI Interrupts.................................................................................................................................................403
15.5.5.3 Group 3 HDMI Interrupts.................................................................................................................................................403
15.5.6 Storing Masked Interrupts ......................................................................................................................................... 404
15.5.6.1 Interrupt Status Registers..................................................................................................................................................404
15.5.7 Processing Analog Front End Interrupts.................................................................................................................... 425
15.6 TX CORE.......................................................................................................................................................................................... 426
15.6.1 Interrupt Architecture Overview................................................................................................................................ 426
15.6.1.1 Interrupt Bits.....................................................................................................................................................................427
15.6.1.2 Interrupt Mask Bits...........................................................................................................................................................428
16 APPENDIX A ....................................................................................................................................................................... 429
16.1 PCB LAYOUT RECOMMENDATIONS............................................................................................................................................. 429
16.2 ANALOGUE INTERFACE INPUTS.................................................................................................................................................... 429
16.3 POWER SUPPLY BYPASSING........................................................................................................................................................... 429
16.3.1 Power Supply Sequencing........................................................................................................................................... 430
16.3.1.1 Power Up Sequence..........................................................................................................................................................430
16.3.1.2 Power Down Sequence.....................................................................................................................................................430
16.4 DIGITAL OUTPUTS (DATA AND CLOCKS).................................................................................................................................... 431
16.5 DIGITAL INPUTS............................................................................................................................................................................. 431
16.6 XTAL AND LOAD CAP VALUE SELECTION.................................................................................................................................. 431
17 APPENDIX B ....................................................................................................................................................................... 433
17.1 ADV7850 TYPICAL CONNECTION DIAGRAMS ........................................................................................................................... 433
18 APPENDIX C ....................................................................................................................................................................... 440
18.1 PACKAGE OUTLINE DRAWING ..................................................................................................................................................... 440
18.2 ORDERING GUIDE.......................................................................................................................................................................... 440
19 APPENDIX D....................................................................................................................................................................... 441
19.1 RECOMMENDED UNUSED PIN CONFIGURATIONS....................................................................................................................... 441
LIST OF FIGURES......................................................................................................................................................................... 450
LIST OF TABLES........................................................................................................................................................................... 454
LIST OF EQUATIONS .................................................................................................................................................................. 457
REVISION HISTORY ................................................................................................................................................................... 458