Analog Devices ADV7619 Installation manual

Hardware User Guide
UG-237
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
Dual Port Xpressview™ Advantiv HDMI Receiver Functionality and Features
SCOPE
This user guide provides a detailed description of the Advantiv™ ADV7619 functionality and features.
DISCLAIMER
Information furnished by Analog Devices, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective owners.
ADV7619
DPLL
CEC
CONTROLLER
5V DETECT
AND HPD
CONTROLLER
CONTROL
INTERFACE
I
2
C
XTALP P0 TO P11
P12 TO P23
AP1/I2S_TDM
AP2
AP3
AP4
P24 TO P35
LLC
AP5
SCLK/INT2
MCLK/INT2
AP0
HS/CS
VS/FIELD/ALSB
DE
INT1
XTALN
RXB_5V
RXA_5V
HPA_A/INT2
HPA_B
EDID
REPEATER
CONTROLLER
PLL
EQUALIZER SAMPLER
HDCP
EEPROM
XPressView™
FAST SWITCHING
HDCP
ENGINE
DATA
PREPROCESSOR
AND COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
BACKEND
COLOR SPACE
CONVERSION
PACKET
PROCESSOR
PACKET/
INFOFRAME
MEMORY
HDMI
PROCESSOR
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
RXA_0±
RXA_2±
RXA_1±
SCL
SDA
CS
CEC
RXA_C±
CONTROL
AND DATA
3Gbs VIDEO PATH
PLL
EQUALIZER SAMPLER
RXB_0±
RXB_2±
RXB_1±
RXB_C±
A
B
C
AUDIO OUTPUT FORMATTER VIDEO OUTPUT FORMATTER
INTERRUPT
CONTROLLER
(INT1, INT2)
AUDIO
PROCESSOR
MUTE
12
12
12
P36 TO P47
12
09581-001
Figure 1. Functional Block Diagram
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS. Rev. A | Page 1 of 204

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TABLE OF CONTENTS
Scope .................................................................................................. 1
Disclaimer.......................................................................................... 1
Revision History ............................................................................... 3
Using the ADV7619 Hardware User Guide.................................. 4
Number Notations........................................................................ 4
Register Access Conventions ...................................................... 4
Acronyms and Abbreviations ..................................................... 4
Field Function Descriptions........................................................ 6
References...................................................................................... 6
Introduction to the ADV7619 ........................................................ 7
HDMI Receiver............................................................................. 7
Component Processor ................................................................. 7
Main Features of ADV7619 ........................................................ 7
Functional Block Diagram .......................................................... 9
Pin Configuration and Function Descriptions....................... 10
Global Control Registers ............................................................... 15
ADV7619 Revision Identification............................................ 15
Power-Down Controls............................................................... 15
Global Pin Control..................................................................... 17
Primary Mode and Video Standard ............................................. 22
Primary Mode and Video Standard Controls......................... 22
HDMI Decimation Modes ........................................................ 24
Primary Mode and Video Standard Configuration for HDMI
Free Run....................................................................................... 24
Recommended Settings for HDMI Inputs.............................. 25
Pixel Port Configuration................................................................ 27
Pixel Port Output Modes........................................................... 27
DDR Output Interface ............................................................... 28
LLC Controls............................................................................... 29
DLL on LLC Clock Path ............................................................ 29
HDMI Receiver............................................................................... 30
+5 V Cable Detect ...................................................................... 30
Hot Plug Assert........................................................................... 31
E-EDID/Repeater Controller.................................................... 33
E-EDID Data Configuration..................................................... 33
Transitioning of Power Modes.................................................. 35
Structure of Internal E-EDID for Port A................................. 35
Structure of Internal E-EDID for Port B ................................. 36
TMDS Equalization.................................................................... 39
Port Selection .............................................................................. 39
Fast Switching and Background Port Selection...................... 39
TMDS Clock Activity Detection.............................................. 40
HDMI/DVI Status Bits .............................................................. 41
Video 3D Detection ................................................................... 42
TMDS Measurement.................................................................. 42
Deep Color Mode Support........................................................ 45
Video FIFO.................................................................................. 46
Pixel Repetition .......................................................................... 47
HDCP Support ........................................................................... 49
HDMI Synchronization Parameters ........................................ 52
Audio Control and Configuration ........................................... 58
Audio FIFO ................................................................................. 60
Audio Packet Type Flags ........................................................... 61
Audio Output Interface ............................................................. 63
MCLKOUT Setting .................................................................... 71
Audio Channel Mode ................................................................ 71
Audio Muting.............................................................................. 71
Audio Clock Regeneration Parameters ................................... 76
Channel Status ............................................................................ 77
Packets and InfoFrames Registers............................................ 81
Packet Registers .......................................................................... 88
Customizing Packet/InfoFrame Storage Registers................. 92
Repeater Support........................................................................ 93
Interface to DPP Section ......................................................... 100
Pass Through Mode ................................................................. 101
Color Space Information Sent to the DPP and CP
Sections...................................................................................... 102
Status Registers ......................................................................... 102
HDMI Section Reset Strategy................................................. 105
HDMI Packet Detection Flag Reset....................................... 105
Data Preprocessor and Color Space Conversion and Color
Controls ......................................................................................... 106
Color Space Conversion Matrix ............................................. 106
Color Controls.......................................................................... 115
Component Processor ................................................................. 117
Introduction to the Component Processor........................... 117
Clamp Operation...................................................................... 117
CP Gain Operation .................................................................. 119
CP Offset Block ........................................................................ 122
AV Code Block ......................................................................... 124

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CP Data Path for HDMI Modes............................................. 125
Sync Processed by CP Section................................................ 129
CP Output Synchronization Signal Positioning................... 136
CP HDMI Controls.................................................................. 148
Free Run Mode ......................................................................... 148
CP Status ................................................................................... 152
CP Core Bypassing....................................................................... 152
Consumer Electronics Control................................................... 153
Main Controls........................................................................... 153
CEC Transmit Section ............................................................. 154
CEC Receive Section................................................................ 156
Antiglitch Filter Module.......................................................... 161
Typical Operation Flow........................................................... 162
Low Power CEC Message Monitoring .................................. 165
Interrupts....................................................................................... 167
Interrupt Architecture Overview........................................... 167
Interrupt Pins ............................................................................170
Description of Interrupt Bits ...................................................173
Additional Explanations ..........................................................174
Register Access and Serial Ports Description............................189
Main I2C Port.............................................................................189
DDC Ports..................................................................................191
Appendix A....................................................................................193
PCB Layout Recommendations ..............................................193
Power Supply Bypassing...........................................................193
Digital Outputs (Data and Clocks).........................................193
Digital Inputs.............................................................................194
XTAL and Load Cap Value Selection .....................................194
Appendix B ....................................................................................195
Recommended Unused Pin Configurations .........................195
Appendix C ....................................................................................198
Pixel Output Formats ...............................................................198
REVISION HISTORY
12/11—Rev. 0 to Rev. A
Changes to the Fourth Paragraph of the Introduction to the
ADV7619 Section..............................................................................7
Changes to Video Output Formats Section...................................8
Changes to Pin 113 Description....................................................13
Changes to Table 7 ..........................................................................25
Added Endnote 1 and Endnote 2 to OP_FORMAT_SEL[7:0], IO,
Address 0x03[7:0] Section..............................................................27
Changes to DLL on LLC Clock Path Section ..............................29
Changes to CS_DATA[27:24], Sampling Fequency, HDMI Map,
Address 0x39[3:0] Section..............................................................80
Changes to Check the Value of Each Coefficient Section........114
Changes to CP_HUE[7:0], Addr 44 (CP), Address 0x3D[7:0]
Section ............................................................................................116
Changes to CP Core Bypassing Section .....................................152
Changes to INT2_POL, IO, Address 0x41[2] Section..............171
Added Endnote 1 to Table 76 ......................................................198
Added Endnote 1 to Table 81 ......................................................203
8/11—Revision 0: Initial Version

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USING THE ADV7619 HARDWARE USER GUIDE
NUMBER NOTATIONS
Table 1.
Notation Description
Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
V[X:Y] Bit field representation covering Bit X to Bit Y of a value or a field (V).
0xNN Hexadecimal (base-16) numbers are preceded by the prefix ‘0x’.
0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’.
NN Decimal (base-10) are represented using no additional prefixes or suffixes.
REGISTER ACCESS CONVENTIONS
Table 2.
Mode Description
R/W Memory location has read and write access.
R Memory location is read access only. A read always returns 0 unless otherwise specified.
W Memory location is write access only.
ACRONYMS AND ABBREVIATIONS
Table 3.
Acronym/Abbreviation Description
ACP Audio content protection.
AGC Automatic gain control.
Ainfo HDCP register. Refer to HDCP documentation.
AKSV HDCP transmitter key selection vector. Refer to HDCP documentation.
An 64-bit pseudo-random value generated by HDCP cipher function of Device A.
AP Audio output pin.
AVI Auxiliary video information.
BCAPS HDCP register. Refer to HDCP documentation.
BKSV HDCP receiver key selection vector. Refer to HDCP documentation.
CP Component processor.
CSC Color space converter/conversion.
DDR Double data rate.
DE Data enable.
DLL Delay locked loop.
DPP Data preprocessor.
DVI Digital visual interface.
EAV End of active video.
EMC Electromagnetic compatibility.
EQ Equalizer.
HD High definition.
HDCP High bandwidth digital content protection.
HDMI® High bandwidth multimedia interface.
HDTV High definition television.
HPA Hot plug assert.
HPD Hot plug detect.
HSync Horizontal synchronization.
IC Integrated circuit.
ISRC International standard recording code.
I2S Inter IC sound.
I2C Inter integrated circuit.

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Acronym/Abbreviation Description
KSV Key selection vector.
LLC Line locked clock.
LSB Least significant bit.
L-PCM Linear pulse coded modulated.
Mbps Megabit per second.
MPEG Moving picture expert group.
ms Millisecond.
MSB Most significant bit.
NC No connect.
OTP One-time programmable.
Pj’ HDCP enhanced link verification response. Refer to HDCP documentation.
Ri’ HDCP link verification response. Refer to HDCP documentation.
Rx Receiver.
SAV Start of active video.
SDR Single data rate.
SHA-1 Refer to HDCP documentation.
SMPTE Society of Motion Picture and Television Engineers.
SOG Sync on green.
SOY Sync on Y.
SPA Source physical address.
SPD Source production descriptor.
STDI Standard detection and identification.
TDM Time division multiplexed.
TMDS Transition minimized differential signaling.
Tx Transmitter.
VBI Video blanking interval.
VSync Vertical synchronization.
XTAL Crystal oscillator.

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FIELD FUNCTION DESCRIPTIONS
Throughout this user guide, a series of function tables are provided. The function of a field is described in a table preceded by the bit
name, a short function description, the I2C map, the register location within the I2C map, and a detailed description of the field.
The detailed description consists of:
•For a readable field, the values the field can take
•For a writable field, the values the field can be set to
Example Field Function Description
This section provides an example of a field function table followed by a description of each part of the table.
PRIM_MODE[3:0], IO Map, Address 0x01[3:0].
A control to select the primary mode of operation of the decoder.
Function
PRIM_MODE[3:0] Description
0000 Reserved
0001 Reserved
0010 Reserved
0011 Reserved
0100 Reserved
0101 HDMI-Comp
0110 (default) HDMI-GR
0111 to 1111 Reserved
In this example
•The name of the field is PRIM_MODE and it is four bit long.
•Address 0x01 is the I2C location of the field in big endian format (MSB first, LSB last).
•The address is followed by a detailed description of the field.
•The first column of the table lists values the field can take or can be set to. These values are in binary format if not preceded by 0x or
in hexadecimal format if preceded by 0x.
•The second column describes the function of each field for each value the field can take or can be set to. Values are in binary format.
REFERENCES
CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006.
Digital Content Protection (DCP) LLC, High-Bandwidth Digital Content Protection System, Revision 1.4, July 8, 2009.
HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.4a, March 4, 2010.
ITU, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating
at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998.

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INTRODUCTION TO THE ADV7619
The ADV7619 is a high quality, 3Gbps high bandwidth, 2:1 multiplexed High-Definition Multimedia Interface (HDMI®) receiver.
The ADV7619 incorporates a dual input HDMI receiver that supports all mandatory 3D TV formats defined in HDMI 1.4a specification,
HDTV formats up to 1080p deep color 12-bit per channel or 2160p8bit color per channel and display resolutions up to 4k by 2k (3840 x
2160 at 30 Hz).
The ADV7619 also integrates an CEC controller that supports the capability discovery and control (CDC) feature.
The ADV7619 incorporates Xpressview™ fast switching on both input HDMI ports. Using Analog Devices’ hardware-based HDCP engine
that minimizes software overhead, Xpressview™ technology allows fast switching between both HDMI input ports in less than 1 second.
Each HDMI port has dedicated +5V Detect and Hot Plug Assert pins. The HDMI receiver also includes an integrated equalizer that
ensures robust operation of the interface with long cables.
Fabricated in an advanced CMOS process, the ADV7619 is provided in a 14 mm × 14 mm, 128-pin surface-mount TQFP_EP, RoHS-
compliant package and is specified over 0°C to +70°C temperature range.
HDMI RECEIVER
The HDMI receiver on the ADV7619 supports 3Gbps data bandwidth allowing for video resolutions up to 4k by 2k. incorporates a fast
switching feature that allows inactive ports to be HDCP authenticated to provide rapid switching between encrypted HDMI sources. The
ADV7619 HDMI receiver incorporates active equalization of the HDMI data signals to compensate for the losses inherent in HDMI and
DVI cabling, especially at longer lengths and higher frequencies. The equalizer is highly effective and is capable of equalizing for long
cables to achieve robust receiver performance.
With the inclusion of HDCP, displays can receive encrypted video content. The HDMI interface of the ADV7619 allows a video receiver
to authenticate, decrypt encoded data and renew that authentication during transmission, as specified by the HDCP v1.4 protocol for
both active and background HDMI ports.
The ADV7619 offers a flexible audio output port for audio data extraction from the HDMI stream. HDMI audio formats, including Super
Audio CD (SACD) via DSD and HBR are supported by ADV7619. The HDMI receiver has advanced audio functionality, such as a mute
controller, that prevents audible extraneous noise in the audio output. Additionally ADV7619 can be set to output Time Division
Multiplexed I2S, which provides four multiplexed I2S channels.
COMPONENT PROCESSOR
The ADV7619 contains component processor (CP), which processes the video data up to 1080p 36-bitdeep color. The CP section
provides color adjustment features, such as brightness, saturation, and hue. The color space conversion (CSC) matrix allows the color
space to be changed as required. The standard detection and identification (STDI) block allows the detection of video timings.
MAIN FEATURES OF ADV7619
HDMI Receiver
•HDMI 1.4a features supported
•3D HDMI 1.4a video format support
•Full colorimetry including sYCC601, Adobe RGB, Adobe YCC601, xvYCC extended gamut color
•CEC 1.4-compatible
•HDCP 1.4 support
•3D Video Support including Frame packing for all 3D formats up to a 297 MHz TMDS clock
•Xpressview™ fast switching between HDMI ports
•Supports display resolutions up to 4k by 2k (4096 x 2160 at 30 Hz)
•Supports all display resolutions up to UXGA (1600 x 1200 at 60Hz, 10-bit)
•Supports many audio formats including DSD, HBR, S/PDIF (IEC60958-compatible) with sampling with sampling frequency up to
192 kHz
•Programmable front-end equalization for long cable lengths
•Audio mute for removing extraneous noise
•Programmable interrupt generator to detect HDMI packets
•Internal EDID support
•Repeater support (up to 127 KSVs)

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Component Video Processing
•Support video formats only up to 1080p 36-bit deep color and graphics up to UXGA 10-bit
•An any-to-any 3 × 3 CSC matrix support YCrCb to RGB and RGB to YCrCb
•Provides color controls, such as saturation, brightness, hue, and contrast
•STDI block that enables format detection
•Free run output mode provides stable timing when no video input is present
Video Output Formats
•Double data rate (DDR) 8-/10-/12-bit 4:2:2 YCrCb1
•Pseudo DDR (CCIR-656 type stream) 8-/10-/12-bit 4:2:2 YCrCb for 525i, 625i, 525P, and 625P
•SDR 16-/20-/24-bit 4:2:2 YCrCb for all standards
•SDR 24-/30-/36-bit 4:4:4 YCrCb/RGB for all HDMI standards
•DDR 12-/24-/30-/36-bit 4:4:4 RGB
•Interleaved 2x SDR 24 bit 422 YCrCb
•Interleaved 2x SDR 24 bit 444 YCrCb/RGB
1Double data rate (DDR) is supported only up to 50 MHz (an equivalent to data rate clocked with 100 MHz clock in SDR mode).

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Additional Features
•HS, VS, FIELD, and DE output signals with programmable position, polarity, and width
•Numerous interrupt sources available for the INT1 and INT2 interrupt request output pins, available via one of the selected pins, that
is, SCLK/INT2, MCLK/INT2, or HPA_A/INT2
•Temperature range of 0°C to +70°C
•14 mm × 14 mm, 128-pin TQFP_EP package
FUNCTIONAL BLOCK DIAGRAM
ADV7619
DPLL
CEC
CONTROLLER
5V DETECT
AND HPD
CONTROLLER
CONTROL
INTERFACE
I
2
C
XTALP P0 TO P11
P12 TO P23
AP1/I2S_TDM
AP2
AP3
AP4
P24 TO P35
LLC
AP5
SCLK/INT2
MCLK/INT2
AP0
HS/CS
VS/FIELD/ALSB
DE
INT1
XTALN
RXB_5V
RXA_5V
HPA_A/INT2
HPA_B
EDID
REPEATER
CONTROLLER
PLL
EQUALIZER SAMPLER
HDCP
EEPROM
XPressView™
FAST SWITCHING
HDCP
ENGINE
DATA
PREPROCESSOR
AND COLOR
SPACE
CONVERSION
COMPONENT
PROCESSOR
BACKEND
COLOR SPACE
CONVERSION
PACKET
PROCESSOR
PACKET/
INFOFRAME
MEMORY
HDMI
PROCESSOR
DDCA_SDA
DDCA_SCL
DDCB_SDA
DDCB_SCL
RXA_0±
RXA_2±
RXA_1±
SCL
SDA
CS
CEC
RXA_C±
CONTROL
AND DATA
3Gbs VIDEO PATH
PLL
EQUALIZER SAMPLER
RXB_0±
RXB_2±
RXB_1±
RXB_C±
A
B
C
AUDIO OUTPUT FORMATTER VIDEO OUTPUT FORMATTER
INTERRUPT
CONTROLLER
(INT1, INT2)
AUDIO
PROCESSOR
MUTE
12
12
12
P36 TO P47
12
09581-001
Figure 2. Functional Block Diagram

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. NC = NO CONNECT. DO NOT CONENCT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE CONNECTED TO GROUND.
2
3
4
7
6
5
1
8
9
CVDD
RXA_C–
RXA_C+
RXA_0+
RXA_0–
TVDD
GND
TVDD
RXA_1–
10
RXA_1+
12
RXA_2–
13
RXA_2+
14
CVDD
15
GND
16
TEST1
17
DVDD
18
TEST2
19
CVDD
20
RXB_C–
21
RXB_C+
22
TVDD
23
RXB_0–
24
RXB_0+
25
TVDD
26
RXB_1–
27
RXB_1+
28
TVDD
29
RXB_2–
30
RXB_2+
31
CVDD
32
GND
11
TVDD
95 VS/FIELD/ALSB
94 HS
93 DE
90 P1
91 P0
92 DVDDIO
96 NC
89 P2
88 P3
87 P4
85 P6
84 P7
83 P8
82 P9
81 P10
80 P11
79 DVDD
78 P12
77 DVDDIO
76 P13
75 P14
74 P15
73 P16
72 P17
71 P18
70 P19
69 P20
68 P21
67 P22
66 P23
65 DVDDIO
86 P5
33
NC
34
DVDD
35
P47
36
P46
37
P45
38
P44
39
P43
40
DVDDIO
41
P42
42
P41
43
P40
44
P39
45
P38
46
P37
47
P36
48
P35
49
P34
50
P33
51
P32
52
DVDDIO
53
DVDD
54
P31
55
P30
56
P29
57
P28
58
P27
59
P26
60
P25
61
P24
62
LLC
63
DVDD
64
DVDD
128 NC 127 NC
126 RXA_5V
125 HPA_A/INT2 124 DDCA_SDA
123 DDCA_SCL
122 RXB_5V 121 HPA_B
120 DDCB_SDA
119 DDCB_SCL 118 CEC
117 DVDD 116 XTALN 115 XTALP
114 PVDD 113 CS 112 RESET
111 INT1
110 SCL
109 SDA
108 DVDD
107 MCLK/INT2 106 AP5 105 SCLK/INT2 104 AP4
103 AP3
102 AP2
101 AP1/I2S_TDM 100 AP0
99 NC
98 NC
97 NC
PIN 1
ADV7619
TOP VIEW
(Not to Scale)
09581-002
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Type Description
0 GND Ground Ground.
1 GND Ground Ground.
2 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
3 RXA_C− HDMI input Digital Input Clock Complement of Port A in the HDMI Interface.
4 RXA_C+ HDMI input Digital Input Clock True of Port A in the HDMI Interface.
5 TVDD Power Terminator Supply Voltage (3.3 V).
6 RXA_0− HDMI input Digital Input Channel 0 Complement of Port A in the HDMI Interface.
7 RXA_0+ HDMI input Digital Input Channel 0 True of Port A in the HDMI Interface.
8 TVDD Power Terminator Supply Voltage (3.3 V).
9 RXA_1− HDMI input Digital Input Channel 1 Complement of Port A in the HDMI Interface.
10 RXA_1+ HDMI input Digital Input Channel 1 True of Port A in the HDMI Interface.

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Pin No. Mnemonic Type Description
11 TVDD Power Terminator Supply Voltage (3.3 V).
12 RXA_2− HDMI input Digital Input Channel 2 Complement of Port A in the HDMI Interface.
13 RXA_2+ HDMI input Digital Input Channel 2 True of Port A in the HDMI Interface.
14 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
15 GND Ground Ground.
16 TEST1 Test This pin must be left floating.
17 DVDD Power Digital Core Supply Voltage (1.8 V)
18 TEST2 Test This pin must be left floating.
19 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
20 RXB_C− HDMI input Digital Input Clock Complement of Port B in the HDMI Interface.
21 RXB_C+ HDMI input Digital Input Clock True of Port B in the HDMI Interface.
22 TVDD Power Terminator Supply Voltage (3.3 V).
23 RXB_0− HDMI input Digital Input Channel 0 Complement of Port B in the HDMI Interface.
24 RXB_0+ HDMI input Digital Input Channel 0 True of Port B in the HDMI Interface.
25 TVDD Power Terminator Supply Voltage (3.3 V).
26 RXB_1− HDMI input Digital Input Channel 1 Complement of Port B in the HDMI Interface.
27 RXB_1+ HDMI input Digital Input Channel 1 True of Port B in the HDMI Interface.
28 TVDD Power Terminator Supply Voltage (3.3 V).
29 RXB_2− HDMI input Digital Input Channel 2 Complement of Port B in the HDMI Interface.
30 RXB_2+ HDMI input Digital Input Channel 2 True of Port B in the HDMI Interface.
31 CVDD Power HDMI Analog Block Supply Voltage (1.8 V).
32 GND Ground Ground.
33 NC No connect No connect.
34 DVDD Power Digital Core Supply Voltage (1.8 V).
35 P47 Digital video
output
Video Pixel Output Port.
36 P46 Digital video
output
Video Pixel Output Port.
37 P45 Digital video
output
Video Pixel Output Port.
38 P44 Digital video
output
Video Pixel Output Port.
39 P43 Digital video
output
Video Pixel Output Port.
40 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
41 P42 Digital video
output
Video Pixel Output Port.
42 P41 Digital video
output
Video Pixel Output Port.
43 P40 Digital video
output
Video Pixel Output Port.
44 P39 Digital video
output
Video Pixel Output Port.
45 P38 Digital video
output
Video Pixel Output Port.
46 P37 Digital video
output
Video Pixel Output Port.
47 P36 Digital video
output
Video Pixel Output Port.
48 P35 Digital video
output
Video Pixel Output Port.
49 P34 Digital video
output
Video Pixel Output Port.
50 P33 Digital video
output
Video Pixel Output Port.
51 P32 Digital video
output
Video Pixel Output Port.
52 DVDDIO Power Digital I/O Supply Voltage (3.3 V).

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Pin No. Mnemonic Type Description
53 DVDD Power Digital Core Supply Voltage (1.8 V).
54 P31 Digital video
output
Video Pixel Output Port.
55 P30 Digital video
output
Video Pixel Output Port.
56 P29 Digital video
output
Video Pixel Output Port.
57 P28 Digital video
output
Video Pixel Output Port.
58 P27 Digital video
output
Video Pixel Output Port.
59 P26 Digital video
output
Video Pixel Output Port.
60 P25 Digital video
output
Video Pixel Output Port.
61 P24 Digital video
output
Video Pixel Output Port.
62 LLC Digital video
output
Pixel Output Clock for the Pixel Data (Range is 13.5 MHz to 170 MHz).
63 DVDD Power Digital Core Supply Voltage (1.8 V).
64 DVDD Power Digital Core Supply Voltage (1.8 V).
65 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
66 P23 Digital video
output
Video Pixel Output Port.
67 P22 Digital video
output
Video Pixel Output Port.
68 P21 Digital video
output
Video Pixel Output Port.
69 P20 Digital video
output
Video Pixel Output Port.
70 P19 Digital video
output
Video Pixel Output Port.
71 P18 Digital video
output
Video Pixel Output Port.
72 P17 Digital video
output
Video Pixel Output Port.
73 P16 Digital video
output
Video Pixel Output Port.
74 P15 Digital video
output
Video Pixel Output Port.
75 P14 Digital video
output
Video Pixel Output Port.
76 P13 Digital video
output
Video Pixel Output Port.
77 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
78 P12 Digital video
output
Video Pixel Output Port.
79 DVDD Power Digital Core Supply Voltage (1.8 V).
80 P11 Digital video
output
Video Pixel Output Port.
81 P10 Digital video
output
Video Pixel Output Port.
82 P9 Digital video
output
Video Pixel Output Port.
83 P8 Digital video
output
Video Pixel Output Port.
84 P7 Digital video
output
Video Pixel Output Port.
85 P6 Digital video
output
Video Pixel Output Port.
86 P5 Digital video
output
Video Pixel Output Port.

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Pin No. Mnemonic Type Description
87 P4 Digital video
output
Video Pixel Output Port.
88 P3 Digital video
output
Video Pixel Output Port.
89 P2 Digital video
output
Video Pixel Output Port.
90 P1 Digital video
output
Video Pixel Output Port.
91 P0 Digital video
output
Video Pixel Output Port.
92 DVDDIO Power Digital I/O Supply Voltage (3.3 V).
93 DE Miscellaneous
digital
DE (data enable) is a signal that indicates active pixel data.
94 HS Digital video
output
HS is a horizontal synchronization output signal.
95 VS
/
FIELD/ALSB Digital video
output
VS is a vertical synchronization output signal. FIELD is a field synchronization output signal
in all interlaced video modes. VS or FIELD can be configured for this pin. The ALSB allows
selection of the I2C address.
96 NC No connect No connect.
97 NC No connect No connect.
98 NC No connect No connect.
99 NC No connect No connect.
100 AP0 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output
(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I2S.
101 AP1
/
I2S_TDM Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output
(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or Time-Division-Multiplexed I2S.
102 AP2 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output
(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I2S.
103 AP3 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output
(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I2S.
104 AP4 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output
(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I2S.
105 SCLK/INT2 Miscellaneous
digital
A dual function pin that can be configured to output Audio Serial Clock or an Interrupt2
signal.
106 AP5 Miscellaneous Audio Output Pin. Pins AP0-AP5 can be configured to output SPDIF Digital Audio Output
(SPDIF), High Bit Rate (HBR), Direct Stream Digital (DSD) or I2S. Additionally pin AP5 can be
configured to provide LRCLK.
107 MCLK/INT2 Miscellaneous A dual function pin that can be configured to output Audio Master Clock or an Interrupt2
signal.
108 DVDD Power Digital Core Supply Voltage (1.8 V).
109 SDA Miscellaneous
digital
I2C Port Serial Data Input/Output Pin. SDA is the data line for the control port.
110 SCL Miscellaneous
digital
I2C Port Serial Clock Input. SCL is the clock line for the control port.
111 INT1 Miscellaneous
digital
Interrupt. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user configuration.
112 RESET Miscellaneous
digital
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7619 circuitry.
113 CS Miscellaneous
digital
Chip Select. This pin has an internal pull-down. Pulling this line up causes I2C state machine
to ignore I2C transmission.
114 PVDD Power PLL Supply Voltage (1.8 V).
115 XTALP Miscellaneous
analog
Input Pin for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock Oscillator Source
to Clock the ADV7619.
116 XTALN Miscellaneous
analog
Crystal Input. Input pin for 28.63636 MHz crystal.
117 DVDD Power Digital Core Supply Voltage (1.8 V).
118 CEC Digital
input/output
Consumer Electronic Control Channel.
119 DDCB_SCL HDMI input HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.
120 DDCB_SDA HDMI input HDCP Slave Serial Data Port B. DDCB_SDA is a 3.3 V input that is 5 V tolerant.

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Pin No. Mnemonic Type Description
121 HPA_B Miscellaneous
digital
Hot Plug Assert signal output for HDMI Port B.
122 RXB_5
V
HDMI input 5 V Detect Pin for Port B in the HDMI Interface.
123 DDCA_SCL HDMI input HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.
124 DDCA_SDA HDMI input HDCP Slave Serial Data Port A. DDCA_SDA is a 3.3 V input that is 5 V tolerant.
125 HPA_A/INT2 Miscellaneous
digital
A dual function pin that can be configured to output Hot Plug Assert signal (for HDMI Port A)
or an Interrupt2 signal.
126 RXA_5
V
HDMI input 5 V Detect Pin for Port A in the HDMI Interface.
127 NC No connect No connect.
128 NC No connect No connect.

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GLOBAL CONTROL REGISTERS
The register control bits described in this section deal with the general control of the chip, and the CP and the HDMI receiver sections of
the ADV7619.
ADV7619 REVISION IDENTIFICATION
RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0] (Read Only)
Chip revision code.
Function
RD_INFO[15:0] Description
0x20C0 ADV7619
POWER-DOWN CONTROLS
Primary Power-Down Controls
POWER_DOWN is the main power-down control. It is the main control for power-down Mode 0 and Mode 1. See the Power-Down
Modes section for more details.
POWER_DOWN, IO, Address 0x0C[5]
A control to enable power-down mode. This is the main I2C power-down control.
Function
POWER_DOWN Description
0 Chip operational
1 (default) Enables chip power down
Secondary Power-Down Controls
The following controls allow various sections of the ADV7619 to be powered down.
It is possible to stop the clock to the CP to reduce power for a power-sensitive application. The CP_PWRDN bit enables this power-save
mode. The HDMI block is not affected by this power-save mode. This allows the use of limited HDMI, STDI monitoring features while
reducing the power consumption. For full processing of the HDMI input, the CP core needs to be powered up.
CP_PWRDN, IO, Address 0x0C[2]
A power-down control for the CP core.
Function
CP_PWRDN Description
0 (default) Powers up clock to CP core.
1 Powers down clock to CP core. HDMI block not affected by this bit.
XTAL_PDN
XTAL_PDN allows the user to power down the XTAL clock in the following sections:
•STDI blocks
•Free run synchronization generation block
•I2C sequencer block, which is used for the configuration of the gain, clamp, and offset
•CP and HDMI section
The XTAL clock is also provided to the HDCP engine, EDID, and the repeater controller within the HDMI receiver. The XTAL clock
within these sections is not affected by XTAL_PDN.
XTAL_PDN, IO, Address 0x0B[0]
A power-down control for the XTAL in the digital blocks.
Function
XTAL_PDN Description
0 (default) Powers up XTAL buffer to digital core
1 Powers down XTAL buffer to digital core

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CORE_PDN
CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections:
•CP block
•Digital section of the HDMI block
CORE_PDN, IO, Address 0x0B[1]
A power-down control for the DPP, CP core, and digital sections of the HDMI core.
Function
CORE_PDN Description
0 (default) Powers up CP and digital sections of HDMI block
1 Powers down CP and digital section of HDMI block
Power-Down Modes
The ADV7619 supports the following power-down modes:
•Power-Down Mode 0
•Power-Down Mode 1
Table 5 shows the power-down and normal modes of ADV7619.
Table 5. Power-Down Modes
POWER_DOWN Bit CEC_POWER_UP Bit CEC EDID Power-Down Mode
0 0 Disabled Enabled Power-Down Mode 0
0 1 Enabled Enabled Power-Down Mode 1
1 0 Disabled Enabled1Normal mode
1 1 Enabled Enabled1Normal mode
1Dependent on the values of EDID_X_ENABLE_CPU and EDID_X_ENABLE for the HDMI port (where X is A).
Power-Down Mode 0
In Power-Down Mode 0, selected sections and pads are kept active to provide EDID and +5 V antiglitch filter functionality.
In Power-Down Mode 0, the sections of the ADV7619 are disabled except for the following blocks:
•I2C slave section
•EDID/repeater controller
•EDID ring oscillator
The ring oscillator provides a clock to the EDID/repeater controller (refer to the E-EDID/Repeater Controller section) and the +5 V
power supply antiglitch filter. The clock output from the ring oscillator runs at approximately 50 MHz.
The following pads only are enabled in Power-Down Mode 0:
•I2C pads
•SDA
•SCL
•+5 V pads
•RXA_5V
•RXB_5V
•HPA_A
•HPA_B
•DDC pads
•DDCA_SCL
•DDCA_SDA
•DDCB_SCL
•DDCB_SDA
•Reset pad RESET
Power-Down Mode 0 is initiated through a software (I2C register) configuration.

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Entering Power-Down Mode 0 via Software
The ADV7619 can be put into Power-Down Mode 0 by setting POWER_DOWN to 1 (default value) and CEC_POWER_UP to 0. This
method allows an external processor to put the system in which the ADV7619 is integrated into standby mode. In this case, the CP and
HDMI cores of the ADV7619 are kept powered up from the main power (for example, ac power) and set in or out of power-down Mode 0
through the POWER_DOWN bit.
Power-Down Mode 1
Power-Down Mode 1 is enabled when the following conditions are met:
•POWER_DOWN bit is set to 1
•CEC section is enabled by setting CEC_POWER_UP to 1
Power-Down Mode 1 provides the same functionality as Power-Down Mode 0, with the addition of the following sections:
•XTAL clock
•CEC section
•Interrupt controller section
The following pads are enabled in Power-Down Mode 1:
•Same pads as enabled in Power-Down Mode 0
•CEC pad
•INT1 and INT2 interrupt pads
The internal EDID is also accessible through the DDC bus for Port A and Port B in Power-Down Mode 0 and Power-Down Mode 1.
GLOBAL PIN CONTROL
RESET Pin
The ADV7619 can be reset by a low reset pulse on the reset pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the
low pulse before an I2C write is performed to the ADV7619.
Reset Controls
MAIN_RESET, IO, Address 0xFF[7] (Self-Clearing)
Main reset where I2C registers are reset to their default values.
Function
MAIN_RESET Description
0 (default) Normal operation
1 Applies main I2C reset
Tristate Output Drivers
PADS_ PDN , IO, Address 0x0C[0]
A power-down control for pads of the digital outputs. When enabled, the pads are tristated and the input path is disabled. This control
applies to the DE, HS, VS/FIELD/ALSB, INT1, and LLC pads and to the P0 to P47 pixel pads.
Function
PADS_PDN Description
0 (default) Powers up pads of digital output pins
1 Powers down pads of digital output pins
DDC_PWRDN[7:0], Addr 68 (HDMI), Address 0x73[7:0]
A power-down control for DDC pads.
Function
DDC_PWRDN[7:0] Description
00000000 (default) Powers up DDC pads
xxxxxxx1 Powers down DDC pads on Port A
xxxxxx1x Powers down DDC pads on Port B

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TRI_PIX
This bit allows the user to tristate the output driver of pixel outputs. Upon setting TRI_PIX, the pixel output P[35:0] is tristated.
TRI_PIX, IO, Address 0x15[1]
A control to tristate the pixel data on the pixel pins, P[47:0].
Function
TRI_PIX Description
0 Pixel bus active
1 (default) Tristates pixel bus
Tristate LLC Driver
TRI_LLC, IO, Address 0x15[2]
A control to tristate the output pixel clock on the LLC pin.
Function
TRI_LLC Description
0 LLC pin active
1 (default) Tristates LLC pin
Tristate Synchronization Output Drivers
The following output synchronization signals are tristated when TRI_SYNCS is set:
•VS/FIELD/ALSB
•HS
•DE
The drive strength controls for these signals are provided via the DR_STR_SYNC bits. The ADV7619 does not support tristating via a
dedicated pin.
TRI_SYNCS, IO, Address 0x15[3]
Synchronization output pins tristate control. The synchronization pins under this control are HS, VS/FIELD/ALSB, and DE.
Function
TRI_SYNCS Description
0 Sync output pins active
1 (default) Tristates sync output pins
Tristate Audio Output Drivers
TRI_AUDIO, IO Map, Address 0x15, [4]
TRI_AUDIO allows the user to tristate the drivers of the following audio output signals:
•AP0
•AP1/I2S_TDM
•AP2
•AP3
•AP4
•AP5
•SCLK/INT2
•MCLK/INT2
The drive strength for the output pins can be controlled by the DR_STR[1:0] bits. The ADV7619 does not support tristating via a
dedicated pin.

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TRI_AUDIO, IO, Address 0x15[4]
A control to tristate the audio output interface pins (AP0, AP1/I2S_TDM, AP2, …, AP5).
Function
TRI_AUDIO Description
0 Audio output pins active
1 (default) Tristates audio output pins
Drive Strength Selection
DR_STR
It may be desirable to strengthen or weaken the drive strength of the output drivers for Electromagnetic Compatibility (EMC) and
crosstalk reasons. This section describes the controls to adjust the output drivers used by the CP and HDMI modes.
The drive strenth DR_STR_SYNC[1:0] bits allow the user to select the strength of the following synchronization signals:
•DE
•HS
•VS/FIELD
The DR_STR[1:0] drive strength bits affect output drivers for the following output pins:
•P[47:0]
•AP0, AP1/I2S_TDM, AP2-AP5
•SCLK
•SDA
•SCL
The drive strength DR_STR_CLK[1:0] bits affect output driver for LLC line.
DR_STR[1:0], IO, Address 0x14[5:4]
A control to set the drive strength of the data output drivers.
Function
DR_STR[1:0] Description
00 Reserved
01 Medium low (2×)
10 (default) Medium high (3×)
11 High (4×)
DR_STR_CLK[1:0], IO, Address 0x14[3:2]
A control to set the drive strength control for the output pixel clock out signal on the LLC pin.
Function
DR_STR_CLK[1:0] Description
00 Reserved
01 Medium low (2×) for LLC up to 60 MHz
10 (default) Medium high (3×) for LLC from 44 MHz to 105 MHz
11 High (4×) for LLC greater than 100 MHz
DR_STR_SYNC[1:0], IO, Address 0x14[1:0]
A control to set the drive strength of the synchronization pins, HS, VS/FIELD/ALSB, and DE.
Function
DR_STR_SYNC[1:0] Description
00 Reserved
01 Medium low (2×)
10 (default) Medium high (3×)
11 High (4×)

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Output Synchronization Selection
VS_OUT_SEL, IO, Address 0x06[7]
A control to select the VSync or FIELD signal to be output on the VS/FIELD/ALSB pin.
Function
VS_OUT_SEL Description
0 Selects FIELD output on VS/FIELD/ALSB pin
1 (default) Selects VSync output on VS/FIELD/ALSB pin
F_OUT_SEL, IO, Address 0x05[4]
A control to select the DE or FIELD signal to be output on the DE pin.
Function
F_OUT_SEL Description
0 (default) Selects DE output on DE pin
1 Selects FIELD output on DE pin
Output Synchronization Signals Polarity
INV_LLC_POL, IO Map, Address 0x06, [0]
The polarity of the pixel clock provided by the ADV7619 via the LLC pin can be inverted using the INV_LLC_POL bit. Note that this
inversion affects only the LLC output pin. The other output pins are not affected by INV_LLC_POL.
Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of the downstream
devices processing the output data of the ADV7619. It is expected that these parameters must be matched regardless of the type of video
data that is transmitted. Therefore, INV_LLC_POL is designed to be mode independent.
INV_LLC_POL, IO, Address 0x06[0]
A control to select the polarity of the LLC.
Function
INV_LLC_POL Description
0 (default) Does not invert LLC
1 Inverts LLC
The output synchronization signals HS, VS/FIELD/ALSB, and DE can be inverted using the following control bits:
•INV_HS_POL
•INV_VS_POL
•INV_F_POL
INV_HS_POL, IO, Address 0x06[1]
A control to select the polarity of the HS signal.
Function
INV_HS_POL Description
0 (default) Negative polarity HS
1 Positive polarity HS
INV_VS_POL, IO, Address 0x06[2]
A control to select the polarity of the VS/FIELD/ALSB signal.
Function
INV_VS_POL Description
0 (default) Negative polarity VS/FIELD/ALSB
1 Positive polarity VS/FIELD/ALSB