ARM DSTREAM-ST User manual

ARM® DSTREAM-ST
Version 1.0
System and Interface Design Reference Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
ARM 100893_0100_00_en

ARM® DSTREAM-ST
System and Interface Design Reference Guide
Copyright © 2017 ARM Limited or its affiliates. All rights reserved.
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0100-00 31 March 2017 Non-Confidential First release
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Product Status
The information in this document is Final, that is for a developed product.
Web Address
http://www.arm.com
Conformance Notices
This section contains conformance notices.
Federal Communications Commission Notice
This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).
Class A
Important: This is a Class A device. In residential areas, this device may cause radio interference. The user should take the
necessary precautions, if appropriate.
CE Declaration of Conformity
The system should be powered down when not in use.
It is recommended that ESD precautions be taken when handling DSTREAM-ST equipment.
The DSTREAM-ST modules generate, use, and can radiate radio frequency energy and may cause harmful interference to radio
communications. There is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful
interference to radio reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct
the interference by one or more of the following measures:
• Ensure attached cables do not lie across the target board.
• Increase the distance between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult ARM Support for help.
Note
It is recommended that wherever possible shielded interface cables be used.
ARM® DSTREAM-ST
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Contents
ARM® DSTREAM-ST System and Interface Design
Reference Guide
Preface
About this book ..................................................... ..................................................... 10
Chapter 1 ARM® DSTREAM-ST system design guidelines
1.1 Reset signals ..................................................... ..................................................... 1-13
1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips
(SoC) ........................................................... ........................................................... 1-15
1.3 Physical and electrical connection guidelines ............................ ............................ 1-17
Chapter 2 ARM® DSTREAM-ST target interface connections
2.1 About the ARM® JTAG 20 connector pinouts and interface signals ............ ............ 2-20
2.2 About the CoreSight™ 20 connector pinouts and interface signals .......................... 2-22
2.3 About Serial Wire Debug (SWD) ...................................... ...................................... 2-25
2.4 About trace signals .................................................................................................. 2-27
2.5 About JTAG port timing characteristics ................................. ................................. 2-28
2.6 About JTAG port buffering ........................................... ........................................... 2-30
2.7 I/O diagrams for the DSTREAM-ST connectors ...................................................... 2-34
2.8 Voltage domains of the DSTREAM-ST unit .............................. .............................. 2-36
2.9 Series termination .................................................................................................... 2-37
Chapter 3 ARM® DSTREAM-ST USER Input/Output (IO) connections
3.1 About the USER I/O connector pinouts ................................. ................................. 3-39
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Chapter 4 Target board design for tracing with ARM® DSTREAM-ST
4.1 Overview of high-speed design ....................................... ....................................... 4-42
4.2 PCB track impedance .............................................................................................. 4-43
4.3 Signal requirements ................................................ ................................................ 4-44
4.4 Modeling .................................................................................................................. 4-45
Chapter 5 Reference
5.1 About adaptive clocking to synchronize the JTAG port ..................... ..................... 5-47
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List of Figures
ARM® DSTREAM-ST System and Interface Design
Reference Guide
Figure 1-1 Example reset circuit logic ..................................................................................................... 1-14
Figure 1-2 TAP Controllers serially chained within an ASIC ................................................................... 1-15
Figure 1-3 Typical JTAG connection scheme .......................................................................................... 1-17
Figure 1-4 Target interface logic levels ................................................................................................... 1-18
Figure 2-1 ARM JTAG 20 connector pinout ............................................................................................ 2-20
Figure 2-2 CoreSight 20 connector pinout .............................................................................................. 2-22
Figure 2-3 Typical SWD connections ...................................................................................................... 2-25
Figure 2-4 SWD timing diagrams ............................................................................................................ 2-26
Figure 2-5 Clock waveforms ................................................................................................................... 2-27
Figure 2-6 JTAG port timing diagram ...................................................................................................... 2-28
Figure 2-7 JTAG connection without buffers ........................................................................................... 2-30
Figure 2-8 JTAG connection with TDO buffer ......................................................................................... 2-30
Figure 2-9 Daisy-chained JTAG connection without buffers ................................................................... 2-31
Figure 2-10 Daisy-chained JTAG connection with TCK buffers ................................................................ 2-32
Figure 2-11 JTAG connection with de-skewed buffers .............................................................................. 2-33
Figure 2-12 Input ....................................................................................................................................... 2-34
Figure 2-13 Output .................................................................................................................................... 2-34
Figure 2-14 Input/Output ........................................................................................................................... 2-34
Figure 2-15 Reset output .......................................................................................................................... 2-34
Figure 2-16 Reset output with feedback ................................................................................................... 2-34
Figure 2-17 VTRef input ............................................................................................................................ 2-35
Figure 2-18 VTRef input (decoupled) ........................................................................................................ 2-35
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Figure 2-19 AC Ground ............................................................................................................................. 2-35
Figure 3-1 USER I/O connector pinouts ................................................................................................. 3-39
Figure 4-1 Track impedance ................................................................................................................... 4-43
Figure 4-2 Data waveforms ..................................................................................................................... 4-44
Figure 5-1 Basic JTAG port synchronizer ............................................................................................... 5-48
Figure 5-2 Timing diagram for the Basic JTAG synchronizer .................................................................. 5-48
Figure 5-3 JTAG port synchronizer for single rising-edge D-type ASIC design rules ............................. 5-48
Figure 5-4 Timing diagram for the D-type JTAG synchronizer ................................................................ 5-49
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List of Tables
ARM® DSTREAM-ST System and Interface Design
Reference Guide
Table 2-1 ARM JTAG 20 interface pinout table ..................................................................................... 2-20
Table 2-2 ARM JTAG 20 signals ............................................................................................................ 2-20
Table 2-3 CoreSight 20 interface pinout table ....................................................................................... 2-22
Table 2-4 CoreSight 20 signals ............................................................................................................. 2-23
Table 2-5 SWD timing requirements ...................................................................................................... 2-26
Table 2-6 TRACECLK frequencies ........................................................................................................ 2-27
Table 2-7 DSTREAM-ST JTAG Characteristics ..................................................................................... 2-29
Table 2-8 Typical series terminating resistor values .............................................................................. 2-37
Table 3-1 USER I/O pin connections ..................................................................................................... 3-39
Table 4-1 Data setup and hold .............................................................................................................. 4-44
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Preface
This preface introduces the ARM® DSTREAM-ST System and Interface Design Reference Guide.
It contains the following:
•About this book on page 10.
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About this book
DSTREAM-ST System and Interface Design Reference Guide describes the interfaces of the
DSTREAM-ST debug and trace unit, with details about designing ARM® architecture-based ASICs and
PCBs. This document is written for those using DSTREAM-ST or those designing PCBs.
Using this book
This book is organized into the following chapters:
Chapter 1 ARM® DSTREAM-ST system design guidelines
The ARM® DSTREAM-ST debug and trace unit enables powerful software debug and
optimization on an ARM processor-based hardware target. Use the information in this chapter to
design your own ARM-architecture-based devices and Printed Circuit Boards (PCBs) that can be
debugged using the DSTREAM-ST unit.
Chapter 2 ARM® DSTREAM-ST target interface connections
This chapter describes the target connector pinouts and their interface signals available on the
ARM DSTREAM-ST unit.
Chapter 3 ARM® DSTREAM-ST USER Input/Output (IO) connections
This chapter describes the additional input and output connections provided in the ARM
DSTREAM-ST unit.
Chapter 4 Target board design for tracing with ARM® DSTREAM-ST
This chapter describes some considerations for the design of a target board that can be connected
to the DSTREAM-ST trace feature.
Chapter 5 Reference
Lists other information that might be useful when working with DSTREAM-ST.
Glossary
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those
terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning
differs from the generally accepted meaning.
See the ARM Glossary for more information.
Typographic conventions
italic
Introduces special terminology, denotes cross-references, and citations.
bold
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms
in descriptive lists, where appropriate.
monospace
Denotes text that you can enter at the keyboard, such as commands, file and program names,
and source code.
monospace
Denotes a permitted abbreviation for a command or option. You can enter the underlined text
instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
<and>
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Preface
About this book
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SMALL CAPITALS
Used in body text for a few terms that have specific technical meanings, that are defined in the
ARM Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and
UNPREDICTABLE.
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Preface
About this book
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Chapter 1
ARM® DSTREAM-ST system design guidelines
The ARM® DSTREAM-ST debug and trace unit enables powerful software debug and optimization on
an ARM processor-based hardware target. Use the information in this chapter to design your own ARM-
architecture-based devices and Printed Circuit Boards (PCBs) that can be debugged using the
DSTREAM-ST unit.
It contains the following sections:
•1.1 Reset signals on page 1-13.
•1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips (SoC)
on page 1-15.
•1.3 Physical and electrical connection guidelines on page 1-17.
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1.1 Reset signals
All ARM processors have a main processor reset that might be called nRESET, BnRES, or HRESET.
This is asserted by one or more of these conditions:
• Power on reset.
• Manual push-button reset.
• Remote reset from the debugger (using DSTREAM-ST).
• Watchdog circuit reset (if appropriate to the application).
Any ARM processor including the JTAG interface has a second reset input called nTRST (TAP Reset).
This resets the debug logic, the Test Access Port (TAP) controller, and the boundary scan cells. It is
activated by remote JTAG reset (from DSTREAM-ST).
Note
ARM strongly recommends that the nRESET and nTRST signals are separately available on the JTAG
connector. If the nRESET and nTRST signals are linked together, resetting the system also resets the
TAP controller. This means that:
• It is not possible to debug a system from reset, because any breakpoints previously set are lost.
• You might have to start the debug session from the beginning, because DSTREAM-ST might not
recover when the TAP controller state is changed.
DSTREAM-ST reset signals
The DSTREAM-ST unit has two reset signals connected to the debug target hardware, nTRST and
nSRST.
What the signals do:
•nTRST drives the JTAG nTRST signal on the ARM processor. It is an output that is activated
whenever the debug software has to re-initialize the debug interface in the target system.
•nSRST is a bidirectional signal that both drives and senses the system reset signal on the target. By
default, this output is driven LOW by the debugger to re-initialize the target system.
Note
It is expected that the assertion of the nSRST line by the DSTREAM-ST unit will cause a warm reset
of the target system. If the nSRST line triggers a power-on reset (POR), then the debug connection
might be lost.
The target hardware must pull the reset lines to their inactive state to assure normal operation when the
JTAG interface is disconnected. In the DSTREAM-ST unit, the strong pull-up/pull-down resistance is
approximately 33Ω, and the weak pull-up/pull-down resistance is approximately 4.7kΩ.
As it is possible to alter the drive strength for nTRST and nSRST, target assemblies with various
different reset configurations can be supported.
Example reset circuits
The diagram shows a typical reset circuit logic for the ARM reset signals and the DSTREAM-ST reset
signals.
1 ARM® DSTREAM-ST system design guidelines
1.1 Reset signals
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TRST
RESET
RST
RST
GndGnd
ARM
Processor
VDD
VDD
TAP RESET
SYSTEM RESET
Open-drain
reset devices
e.g. STM1001
To other
logic
VDD
VDD
nTRST
nSRST
Manual
reset
10K
10K
100R
100nF
Signals from JTAG connector
Figure 1-1 Example reset circuit logic
1 ARM® DSTREAM-ST system design guidelines
1.1 Reset signals
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1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-
Chips (SoC)
Use the information in this section to work with Application-Specific Integrated Circuits (ASIC) or
System-on-Chips (SoCs).
This section contains the following subsections:
•1.2.1 ASICs containing multiple devices on page 1-15.
•1.2.2 Boundary scan test vectors on page 1-16.
1.2.1 ASICs containing multiple devices
If your system contains multiple devices that each have a JTAG Test Access Port (TAP) controller, you
must serially chain them so that DSTREAM-ST can communicate with all of them simultaneously. The
chaining can either be within the ASIC, or externally.
Note
There is no support in DSTREAM-ST for multiplexing TCK, TMS, TDI, TDO, and RTCK between
several different processors.
TAP controllers serially chained within the ASIC
The JTAG standard originally described serially chaining multiple devices on a PCB. This concept can
be extended to serially chaining multiple TAP controllers within an ASIC, as shown in the following
figure:
TDI
TDI TDO
TAP
Controller
TCK
nTRST
TMS
TDO
TDI
Second Tap Device
TDO
TCK
nTRST
TMS
TCK
nTRST
TMS
TAP
Controller
First Tap Device
Figure 1-2 TAP Controllers serially chained within an ASIC
This configuration does not increase the package pin count. It does increase JTAG propagation delays,
but this impact can be small if unaddressed TAP controllers are placed into bypass mode.
TAP controllers serially chained externally
You can use separate pins on the ASIC for each JTAG port, and serially chain them externally (for
example on the PCB). This configuration can simplify device testing, and gives the greatest flexibility on
the PCB. However, this is at the cost of many pins on the device package.
1 ARM® DSTREAM-ST system design guidelines
1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips (SoC)
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1.2.2 Boundary scan test vectors
If you use the JTAG boundary scan test methodology to apply production test vectors, you might want to
have independent external access to each Test Access Port (TAP) controller. This avoids the requirement
to merge test vectors for more than one block in the device.
One solution to this is to adopt a hybrid approach, using a pin on the package that switches elements of
the device into a test mode. You can use this to break the internal daisy chaining of TDO and TDI
signals, and to multiplex out independent JTAG ports on pins that are used for another purpose during
normal operation.
1 ARM® DSTREAM-ST system design guidelines
1.2 Working with Application-Specific Integrated Circuits (ASIC) or System-on-Chips (SoC)
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1.3 Physical and electrical connection guidelines
Use the guidelines below to define physical and electrical connections on your target board.
JTAG connection scheme
The diagram shows a typical JTAG connection scheme.
TRST
RESET
ARM
Processor/
ASIC
10K
Signals from JTAG connector
TDI
TMS
TCK
RTCK
TDO
DBGRQ
DBGACK
10K
Gnd Gnd
Reset
circuit
22R
22R
0R
10K
10K
10K
10K
10K
VDD
Gnd
VTREF
TDI
TMS
TCK
RTCK
nTRST
nSRST
DBGRQ
TDO
DBGACK
GND
Figure 1-3 Typical JTAG connection scheme
Note
• The signals TDI, TMS, TCK, RTCK and TDO are typically pulled up on the target board to keep
them stable when the debug equipment is not connected.
•DBGRQ and DBGACK if present, are typically pulled down on the target.
• If there is no RTCK signal provided on the processor, it can either be pulled to a fixed logic level or
connected to the TCK signal to provide a direct loop-back.
• All pull-up and pull-down resistors must be in the range 1K-100KΩ.
• The VTRef signal is typically connected directly to the VDD rail. If you use a series resistor to
protect against short-circuits, it must have a value no greater than 100Ω.
• To improve signal integrity, it is good practice to provide an impedance matching resistor on the
TDO and RTCK outputs of the processor. The value of these resistors, added to the impedance of the
driver must be approximately equal to 50Ω.
Target interface logic levels
DSTREAM-ST is designed to interface with a wide range of target system logic levels. It does this by
adapting its output drive and input threshold to a reference voltage supplied by the target system.
VTRef feeds the reference voltage to the DSTREAM-ST unit. This voltage is clipped internally at
approximately 3.4V, and is used as the output high voltage (Voh) for logic 1s (ones) on TCK, TDI, and
TMS.
For logic 0s (zeroes), 0V is used as the output low voltage. The input logic threshold voltage (Vi(th)) for
the TDO, RTCK, and nSRST input is 50% of the Voh level, and so is clipped to approximately 1.7V.
The relationships of Voh and Vi(th) to VTRef are shown in the following figure:
1 ARM® DSTREAM-ST system design guidelines
1.3 Physical and electrical connection guidelines
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0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0 1 2 3 4 5 6
Target VTref (V)
Voh & Vi(th) (V)
Voutput high Level - Voh
Vinput threshold - Vi (th)
Figure 1-4 Target interface logic levels
DSTREAM-ST can adapt interface levels down to VTRef of 1.2V.
By default, the nTRST and nSRST signals are pulled-up by 4.7K resistors within DSTREAM-ST and
driven (strong) low during resets. This allows the reset signals to be driven by other open-drain devices
or switches on the target board. The polarity and high/low drive strengths can be configured within the
software.
The input and output characteristics of the DSTREAM-ST unit are compatible with logic levels from
TTL-compatible, or CMOS logic in target systems. When assessing compatibility with other logic
systems, the output impedance of all signals is approximately 50Ω.
1 ARM® DSTREAM-ST system design guidelines
1.3 Physical and electrical connection guidelines
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Chapter 2
ARM® DSTREAM-ST target interface connections
This chapter describes the target connector pinouts and their interface signals available on the ARM
DSTREAM-ST unit.
It contains the following sections:
•2.1 About the ARM® JTAG 20 connector pinouts and interface signals on page 2-20.
•2.2 About the CoreSight™ 20 connector pinouts and interface signals on page 2-22.
•2.3 About Serial Wire Debug (SWD) on page 2-25.
•2.4 About trace signals on page 2-27.
•2.5 About JTAG port timing characteristics on page 2-28.
•2.6 About JTAG port buffering on page 2-30.
•2.7 I/O diagrams for the DSTREAM-ST connectors on page 2-34.
•2.8 Voltage domains of the DSTREAM-ST unit on page 2-36.
•2.9 Series termination on page 2-37.
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2.1 About the ARM® JTAG 20 connector pinouts and interface signals
The ARM JTAG 20 connector is a 20-way 2.54mm pitch connector. You can use it in either standard
JTAG (IEEE 1149.1) mode or Serial Wire Debug (SWD) mode.
The following figure shows the ARM JTAG 20 connector pinout:
2
4
6
8
10
12
16
18
20
14
1
3
5
7
9
11
15
17
19
13
Figure 2-1 ARM JTAG 20 connector pinout
ARM® JTAG 20 pinouts
The table shows the ARM JTAG 20 pinouts as used on the target board.
Table 2-1 ARM JTAG 20 interface pinout table
Pin Signal name I/O
diagram
Pin Signal name I/O
diagram
1VTRef F 2 NC NA
3nTRST D 4 GND H
5TDI B 6 GND H
7TMS/SWDIO B/C 8 GND H
9TCK/SWCLK B 10 GND H
11 RTCK A 12 GND H
13 TDO/SWO A 14 GND H
15 nSRST E 16 GND H
17 DBGRQ B 18 GND H
19 DBGACK A 20 GND H
ARM® JTAG 20 interface signals
The table describes the signals on the ARM JTAG 20 interface.
Table 2-2 ARM JTAG 20 signals
Signal I/O Description
TDI Output The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the
target.
TDO Input The Test Data Out pin receives serial data from the target during debugging. You are advised to series
terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
2 ARM® DSTREAM-ST target interface connections
2.1 About the ARM® JTAG 20 connector pinouts and interface signals
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