Artesyn MVME5500 User manual

MVME5500 Single Board Computer
Programmer’s Reference Guide
P/N: 6806800H16C
July 2014

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Contents
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 3
About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1 Board Description and Memory Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.1 Default Processor Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.3.2 MOTLoad’s Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3.3 Default PCI Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3.4 MOTLoad’s PCI Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.3.5 PCI I/O Space Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.6 System I/O Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.3.7 System Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.8 System Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3.9 System Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.10 Presence Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.3.11 Configuration Header/Switch Register (S1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3.12 Time Base Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.3.13 Geographical Address Register (S2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.3.14 COM1 & COM2 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . 28
1.3.15 Real-Time Clock and NVRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.4 ISA Local Resource Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2 Programming Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 PCI Configuration Space and IDSEL Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.4 Two-Wire Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5 GT-64260B Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.6 GT-64260B GPP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.7 GT-64260B Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.8 GT-64260B Device Controller Bank Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.9 System Clock Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.10 VPD and User Configuration EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Contents

MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
Contents
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Contents
Contents
2.11 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.12 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.13 PCI Arbitration Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.14 Other Software Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.14.1 CPU Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.14.2 Processor Type Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.14.3 Processor PLL Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.14.4 L1, L2, L3 Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A Vital Product Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A.1 Flash Memory Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
A.2 L3 Cache Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
B Related Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
B.1 Artesyn Embedded Technologies - Embedded Computing Documentation . . . . . . . . . . . . . . . . 49
B.2 Manufacturer’s Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
B.3 Related Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Safety Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Sicherheitshinweise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

List of Tables
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 5
Table P-1 Supported Model Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 1-1 MVME5500 Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 1-2 Default Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1-3 MOTLoad’s Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 1-4 Default PCI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 1-5 MOTLoad’s PCI 0 Domain Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-6 MOTLoad’s PCI 1 Domain Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1-7 PCI 0 Domain I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-8 PCI 1 Domain I/O Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-9 Device Bank 1 I/O Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 1-10 System Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-11 System Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-12 System Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-13 Presence Detect Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-14 Configuration Header/Switch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 1-15 TBEN Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 1-16 Geographical Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 2-1 IDSEL Mapping for PCI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 2-2 GT-64260B External GPP Interrupt Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 2-3 I2C Bus Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 2-4 GT-64260B GPP Pin Function Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 2-5 GT-64260B Power-Up Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 2-6 Device Bank Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 2-7 Device Bank Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 2-8 PCI Arbiter Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-9 Processor L3CR Register Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table A-1 Flash 0 Memory Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table A-2 Flash 1 Memory Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table A-3 L3 Cache Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications . . . . . . . . . . . . . . 49
Table B-2 Manufacturers’ Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table B-3 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
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List of Tables

List of Figures
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 7
Figure 1-1 MVME5500 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 1-2 Configuration Header/Switch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 1-3 Geographical Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
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List of Figures

MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 9
About this Manual
The MVME5500 Single Board Computer Programmer’s Reference Guide provides general
programming information, including memory maps, interrupts, and register data for the
MVME5500 family of boards. This document should be used by anyone who wants general, as
well as technical information about the MVME5500 products.
As of the printing date of this manual, the MVME5500 supports the models listed below.
Overview of Contents
This manual is divided into the following chapters and appendices:
Chapter 1, Board Description and Memory Maps, provides a brief product description and a
block diagram. The remainder of the chapter provides information on memory maps and
system and configuration registers.
Chapter 2, Programming Details, provides additional programming information including
IDSEL mapping, interrupt assignments for the GT-64260B system processor, two-wire
serial interface addressing, and other device and system considerations.
Appendix A, Vital Product Data, provides a listing of vital product data (VPD) related to this
product.
Appendix B, Related Documentation, provides a listing of related manuals, vendor
documentation, and industry specifications.
Table P-1 Supported Model Numbers
Model Number Description
MVME5500-0161R 1 GHz MPC7457 processor, 512 MB SDRAM,
Scanbe handles
MVME5500-0163R 1 GHz MPC7457 processor, 512 MB SDRAM,
IEEE handles

MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
About this Manual
10
About this Manual
Conventions
The following table describes the conventions used throughout this manual.
Notation Description
0x00000000 Typical notation for hexadecimal numbers (digits are
0 through F), for example used for addresses and
offsets
0b0000 Same for binary numbers (digits are 0 and 1)
bold Used to emphasize a word
Screen Usedforon-screenoutputandcoderelatedelements
or commands in body text
Courier + Bold Used to characterize user input and to separate it
from system output
Reference Used for references and for table and figure
descriptions
File > Exit Notation for selecting a submenu
<text> Notation for variables and keys
[text] Notation for software buttons to click on the screen
and parameter description
... Repeated item for example node 1, node 2, ..., node
12
.
.
.
Omission of information from example/command
that is not necessary at the time being
.. Ranges, for example: 0..4 means one of the integers
0,1,2,3, and 4 (used in registers)
| Logical OR

About this Manual
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 11
Summary of Changes
This manual has been revised and replaces all prior editions.
Indicates a hazardous situation which, if not avoided,
could result in death or serious injury
Indicates a hazardous situation which, if not avoided,
may result in minor or moderate injury
Indicates a property damage message
No danger encountered. Pay attention to important
information
Notation Description
Part Number Publication Date Description
V5500A/PG2 October 2003 Motorola format; Corrected the PCI 0 and 1
domain memory space sizes in Table 1-3 on page
17.
6806800H16A October 2009 Updated to Emerson format
6806800H16B September 2013 Updated Table "Supported Model Numbers" on
page 9, Table "Processor L3CR Register
Assignments" on page 43, Table "L3 Cache
Configuration Data" on page 47and Table
"Manufacturers’ Documents" on page 50.
6806800H16C July 2014 Re branded to Artesyn template.

MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
About this Manual
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About this Manual

Chapter 1
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 13
Board Description and Memory Maps
1.1 Introduction
This chapter briefly describes the board level hardware features of the MVME5500 Single Board
Computer, including a table of features and a block diagram. The remainder of the chapter
provides memory map information including a default memory map, MOTLoad’s processor
memory map, a default PCI memory map, MOTLoad’s PCI memory map, a PCI I/O memory
map, and system I/O memory maps.
Programmable registers in the GT-64260B system controller are documented in publication
MV-S100414-00 Rev A, which is obtainable from Marvell Technologies, Ltd. Refer to Appendix
B, Related Documentation for more information.
1.2 Overview
TheMVME5500 is a single-boardcomputerbasedon the PowerPCMPC7457 processorand the
Marvell GT-64260B host bridge with a dual PCI interface and memory controller. On-board
payload includes two PMC slots, two SDRAM banks, an expansion connector for two additional
banks of SDRAM, 8MB boot Flash ROM, one 10/100/1000 Ethernet port, one 10/100 Ethernet
port, 32MB expansion Flash ROM, two serial ports, and an NVRAM and real-time clock.
The following table lists the features of the MVME5500.
Table 1-1 MVME5500 Features Summary
Feature Description
Processor Single 1 GHz MPC7457 processor
Bus clock frequency at 133 MHz
L3 Cache 2 MB using SDR SRAM
Bus clock frequency at 200 MHz
Flash 8MB Flash soldered on board
32MB expansion Flash soldered on board
System Memory Two banks on-board for 512 MB using 256 Mb devices
Expansion connector for a mezzanine board with two banks for
512 MB using 256 Mb devices
Double-bit-error detect, single-bit-error correct across 72 bits
Bus clock frequency at 133 MHz

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
14
Memory Controller Provided by GT-64260B
Supports one to four banks of SDRAM at up to 1 GB per bank
Processor Host Bridge Provided by GT-64260B
Supports MPX mode or 60x mode
PCI Interfaces Provided by GT-64260B
Two independent 64-bit interfaces, one compliant to PCI spec rev 2.1
(Bus 0.0) and the other compliant to PCI spec rev 2.2 (Bus 1.0)
Bus clock frequency at 66 MHz
Interrupt Controller Provided by GT-64260B
Interrupt sources internal to GT-64260B
Up to 32 external interrupt inputs
Up to seven interrupt outputs
Counters/Timers Eight 32-bit counters/timers in GT-64260B
I2C Provided by GT-64260B
Master or slave capable
On-boardserialEEPROMsforVPD,SPD,GT-64260B init, anduserdata
storage
NVRAM 32 KB provided by MK48T37
Real Time Clock Provided by MK48T37
Watchdog Timers One in GT-64260B
One in MK48T37
Each watchdog timer can generate interrupt or reset, software
selectable
On-board Peripheral
Support
One 10/100/1000BaseT Ethernet interface, one 10/100BaseT
Ethernet interface
Dual 16C550 compatible UARTs
PCI Mezzanine Cards Two PMC sites (one shared with the expansion memory and has IPMC
capability)
PCI Expansion One expansion connector for interface to PMCspan
Miscellaneous Reset/Abort switch
Front panel status indicators, Run and Board Fail
Table 1-1 MVME5500 Features Summary (continued)
Feature Description

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 15
Form Factor Standard VME
Figure 1-1 MVME5500 Block Diagram
Table 1-1 MVME5500 Features Summary (continued)
Feature Description

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
16
1.3 Memory Maps
1.3.1 Default Processor Memory Map
When power is first applied or a hard reset has occurred, the GT-64260B has a default address
map. Table 1-2 shows the default processor memory map.
Table 1-2 Default Processor Memory Map
Processor Address
Start
Processor Address
End Size Definition
0000 0000 007F FFFF 8 MB SDRAM Bank 0
0080 0000 00FF FFFF 8 MB SDRAM Bank 1
0100 0000 017F FFFF 8 MB SDRAM Bank 2
0180 0000 01FF FFFF 8 MB SDRAM Bank 3
0200 0000 0FFF FFFF 224 MB Unassigned
1000 0000 11FF FFFF 32 MB PCI Bus 0 I/O Space
1200 0000 13FF FFFF 32 MB PCI Bus 0 Memory Space 0
1400 0000 1BFF FFFF 128 MB Unassigned
1C00 0000 1C7F FFFF 8 MB Device Port CS0
1C80 0000 1CFF FFFF 8 MB Device Port CS1
1D00 0000 1DFF FFFF 16 MB Device Port CS2
1E00 0000 1FFF FFFF 32 MB Unassigned
2000 0000 21FF FFFF 32 MB PCI Bus 1 I/O
2200 0000 23FF FFFF 32 MB PCI Bus 1 Memory Space 0
2400 0000 25FF FFFF 32 MB PCI Bus 1 Memory Space 1
2600 0000 27FF FFFF 32 MB PCI Bus 1 Memory Space 2
2800 0000 29FF FFFF 32 MB PCI Bus 1 Memory Space 3
2A00 0000 F0FF FFFF 3184 MB Unassigned
F100 0000 F100 FFFF 64 KB Internal Registers1
F101 0000 F1FF FFFF 16 MB -
64 KB
Unassigned

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 17
1.3.2 MOTLoad’s Processor Memory Map
MOTLoad’s processor memory map is given in the following table.
F200 0000 F3FF FFFF 32 MB PCI Bus 0 Memory Space 1
F400 0000 F5FF FFFF 32 MB PCI Bus 0 Memory Space 2
F600 0000 F7FF FFFF 32 MB PCI Bus 0 Memory Space 3
F800 0000 FEFF FFFF 112 MB Unassigned
FF00 0000 FF7F FFFF 8MB Device Port CS3
FF80 0000 FFFF FFFF 8 MB Boot Flash Bank2
1. Set by configuration resistors.
2. Selects Flash 0 or Flash 1 depending on the state of the Flash boot bank select jumper.
Table 1-2 Default Processor Memory Map (continued)
Processor Address
Start
Processor Address
End Size Definition
Table 1-3 MOTLoad’s Processor Memory Map
Processor Address
Start
Processor Address
End Size Definition
0000 0000 7FFF FFFF 2 GB On-Board SDRAM1
8000 0000 DFFF FFFF 1.5 GB PCI 0 Domain Memory Space
E000 0000 EFFF FFFF 256 MB PCI 1 Domain Memory Space
F000 0000 F07F FFFF 8 MB PCI 0 Domain I/O Space2
F080 0000 F0FF FFFF 8 MB PCI 1 Domain I/O Space2
F100 0000 F10F FFFF 1 MB GT-64260B Internal Registers
F110 0000 F11F FFFF 1 MB GT-64260B Device Bus
Registers3
F120 0000 F1FF FFFF 14 MB Reserved
F200 0000 FE00 0000 32 MB Flash Bank 04
FF80 0000 FFFF FFFF 8 MB Flash Bank 14

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
18
1.3.3 Default PCI Memory Map
Table 1-4 is the default PCI memory map for each PCI bus following reset.
1. Maximum size is 2 GB. Actual size depends on the amount of memory installed.
2. Zero-based I/O space.
3. Device chip select 1.
4. Flash 0/Flash 1 can be mapped to device chip select 0 or BOOT chip select depending on the state of the
Flash boot bank select header.
Table 1-4 Default PCI Memory Map
PCI Address Start PCI Address End Size Definition
0000 0000 007F FFFF 8 MB SDRAM Bank 0
0080 0000 00FF FFFF 8 MB SDRAM Bank 1
0100 0000 017F FFFF 8 MB SDRAM Bank 2
0180 0000 01FF FFFF 8 MB SDRAM Bank 3
0200 0000 0FFF FFFF 224 MB Unassigned
1000 0000 11FF FFFF 32 MB PCI Bus 1 P2P I/O Space
1200 0000 13FF FFFF 32 MB PCI Bus 1 P2P Memory Space 0
1400 0000 1400 FFFF 64 KB Internal Registers
1401 0000 1BFF FFFF 128 MB -
64 KB
Unassigned
1C00 0000 1C7F FFFF 8 MB Device Port CS0
1C80 0000 1CFF FFFF 8 MB Device Port CS1
1D00 0000 1DFF FFFF 16 MB Device Port CS2
1E00 0000 1FFF FFFF 32 MB Unassigned
2000 0000 21FF FFFF 32 MB PCI Bus 0 P2P I/O Space
2200 0000 23FF FFFF 32 MB PCI Bus 0 P2P Memory Space 0
2400 0000 25FF FFFF 32 MB PCI Bus 0 P2P Memory Space 1
2600 0000 F1FF FFFF 32 MB Unassigned

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C) 19
1.3.4 MOTLoad’s PCI Memory Maps
MOTLoad’s PCI memory map for each PCI domain is shown in the following tables.
F200 0000 F3FF FFFF 3264 MB PCI Bus 1 P2P Memory Space 1
F400 0000 FEFF FFFF 32 MB Unassigned
FF00 0000 FF7F FFFF 176 MB Device Port CS3
FF80 0000 FFFF FFFF 8 MB Boot Flash Bank
Table 1-4 Default PCI Memory Map (continued)
PCI Address Start PCI Address End Size Definition
Table 1-5 MOTLoad’s PCI 0 Domain Memory Map
PCI 0 Memory Address
Start
PCI 0 Memory Address
End Size Definition
0000 0000 7FFF FFFF 2 GB Onboard SDRAM
8000 0000 DFFF FFFF 768 MB Local PCI 0 Domain Memory
Space
F000 0000 FFFF FFFF 256 MB Reserved
Table 1-6 MOTLoad’s PCI 1 Domain Memory Map
PCI 1 Memory Address
Start
PCI 1 Memory Address
End Size Definition
0000 0000 7FFF FFFF 2 GB Onboard SDRAM
E000 0000 EFFF FFFF 1 GB Local PCI 1 Domain Memory
Space
F000 0000 FFFF FFFF 256 MB Reserved

Board Description and Memory Maps
MVME5500 Single Board Computer Programmer’s Reference Guide (6806800H16C)
20
1.3.5 PCI I/O Space Maps
The PCI I/O space map for each PCI domain is shown in the following tables.
1.3.6 System I/O Memory Map
System resources for the MVME5500 board including system control and status registers,
NVRAM/RTC, and the 16550 UARTs are mapped into a 1 MB address range assigned to device
bank 1. The region defined by device bank 1 resides within the GT-64260B device bus register’s
space listed in Table 1-3 on page 17. The memory map is defined in the following table:
Table 1-7 PCI 0 Domain I/O Map
PCI 0 I/O Address Start PCI 0 I/O Address End Size Definition
0000 0000 007F FFFF 8 MB Local PCI Domain I/O Space
Table 1-8 PCI 1 Domain I/O Map
PCI 0 I/O Address Start PCI 0 I/O Address End Size Definition
0000 0000 007F FFFF 8 MB Local PCI Domain I/O Space
Table 1-9 Device Bank 1 I/O Memory Map
Device Bank1 Address Offset Definition
0 0000 System Status Register 1
0 0001 System Status Register 2
0 0002 System Status Register 3
0 0003 Reserved
0 0004 Presence Detect Register
0 0005 Software Readable Header/Switch
0 0006 Timebase Enable Register
0 0007 Geographical Address Register (VME board)
0 0008 - 0 FFFF Reserved for future on-board registers
1 0000 - 1 7FFF M48T37V NVRAM/RTC